| | 1 | /** @file\r |
| | 2 | *\r |
| | 3 | * Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r |
| | 4 | *\r |
| | 5 | * This program and the accompanying materials\r |
| | 6 | * are licensed and made available under the terms and conditions of the BSD License\r |
| | 7 | * which accompanies this distribution. The full text of the license may be found at\r |
| | 8 | * http://opensource.org/licenses/bsd-license.php\r |
| | 9 | *\r |
| | 10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| | 11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| | 12 | *\r |
| | 13 | **/\r |
| | 14 | \r |
| | 15 | \r |
| | 16 | #ifndef __PL061_GPIO_H__\r |
| | 17 | #define __PL061_GPIO_H__\r |
| | 18 | \r |
| | 19 | #include <Protocol/EmbeddedGpio.h>\r |
| | 20 | \r |
| | 21 | // PL061 GPIO Registers\r |
| | 22 | #define PL061_GPIO_DATA_REG_OFFSET ((UINTN) 0x000)\r |
| | 23 | #define PL061_GPIO_DATA_REG ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x000)\r |
| | 24 | #define PL061_GPIO_DIR_REG ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x400)\r |
| | 25 | #define PL061_GPIO_IS_REG ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x404)\r |
| | 26 | #define PL061_GPIO_IBE_REG ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x408)\r |
| | 27 | #define PL061_GPIO_IEV_REG ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x40C)\r |
| | 28 | #define PL061_GPIO_IE_REG ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x410)\r |
| | 29 | #define PL061_GPIO_RIS_REG ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x414)\r |
| | 30 | #define PL061_GPIO_MIS_REG ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x410)\r |
| | 31 | #define PL061_GPIO_IC_REG ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x41C)\r |
| | 32 | #define PL061_GPIO_AFSEL_REG ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x420)\r |
| | 33 | \r |
| | 34 | #define PL061_GPIO_PERIPH_ID0 ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFE0)\r |
| | 35 | #define PL061_GPIO_PERIPH_ID1 ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFE4)\r |
| | 36 | #define PL061_GPIO_PERIPH_ID2 ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFE8)\r |
| | 37 | #define PL061_GPIO_PERIPH_ID3 ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFEC)\r |
| | 38 | \r |
| | 39 | #define PL061_GPIO_PCELL_ID0 ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFF0)\r |
| | 40 | #define PL061_GPIO_PCELL_ID1 ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFF4)\r |
| | 41 | #define PL061_GPIO_PCELL_ID2 ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFF8)\r |
| | 42 | #define PL061_GPIO_PCELL_ID3 ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFFC)\r |
| | 43 | \r |
| | 44 | \r |
| | 45 | // GPIO pins are numbered 0..7\r |
| | 46 | #define LAST_GPIO_PIN 7\r |
| | 47 | \r |
| | 48 | // All bits low except one bit high, native bit length\r |
| | 49 | #define GPIO_PIN_MASK(Pin) (1UL << ((UINTN)(Pin)))\r |
| | 50 | \r |
| | 51 | #endif // __PL061_GPIO_H__\r |
projects / mirror_edk2.git / blame_incremental