| | 1 | /** @file PL111Lcd.h |
| | 2 | |
| | 3 | Copyright (c) 2011, ARM Ltd. All rights reserved.<BR> |
| | 4 | This program and the accompanying materials |
| | 5 | are licensed and made available under the terms and conditions of the BSD License |
| | 6 | which accompanies this distribution. The full text of the license may be found at |
| | 7 | http://opensource.org/licenses/bsd-license.php |
| | 8 | |
| | 9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, |
| | 10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. |
| | 11 | |
| | 12 | **/ |
| | 13 | |
| | 14 | #ifndef _PL111LCD_H__ |
| | 15 | #define _PL111LCD_H__ |
| | 16 | |
| | 17 | /********************************************************************** |
| | 18 | * |
| | 19 | * This header file contains all the bits of the PL111 that are |
| | 20 | * platform independent. |
| | 21 | * |
| | 22 | **********************************************************************/ |
| | 23 | |
| | 24 | // Controller Register Offsets |
| | 25 | #define PL111_REG_LCD_TIMING_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x000) |
| | 26 | #define PL111_REG_LCD_TIMING_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x004) |
| | 27 | #define PL111_REG_LCD_TIMING_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x008) |
| | 28 | #define PL111_REG_LCD_TIMING_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x00C) |
| | 29 | #define PL111_REG_LCD_UP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x010) |
| | 30 | #define PL111_REG_LCD_LP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x014) |
| | 31 | #define PL111_REG_LCD_CONTROL ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x018) |
| | 32 | #define PL111_REG_LCD_IMSC ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x01C) |
| | 33 | #define PL111_REG_LCD_RIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x020) |
| | 34 | #define PL111_REG_LCD_MIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x024) |
| | 35 | #define PL111_REG_LCD_ICR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x028) |
| | 36 | #define PL111_REG_LCD_UP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x02C) |
| | 37 | #define PL111_REG_LCD_LP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x030) |
| | 38 | #define PL111_REG_LCD_PALETTE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x200) |
| | 39 | |
| | 40 | // Identification Register Offsets |
| | 41 | #define PL111_REG_CLCD_PERIPH_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE0) |
| | 42 | #define PL111_REG_CLCD_PERIPH_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE4) |
| | 43 | #define PL111_REG_CLCD_PERIPH_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE8) |
| | 44 | #define PL111_REG_CLCD_PERIPH_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFEC) |
| | 45 | #define PL111_REG_CLCD_P_CELL_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF0) |
| | 46 | #define PL111_REG_CLCD_P_CELL_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF4) |
| | 47 | #define PL111_REG_CLCD_P_CELL_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF8) |
| | 48 | #define PL111_REG_CLCD_P_CELL_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFFC) |
| | 49 | |
| | 50 | /**********************************************************************/ |
| | 51 | |
| | 52 | // Register components (register bits) |
| | 53 | |
| | 54 | // This should make life easier to program specific settings in the different registers |
| | 55 | // by simplifying the setting up of the individual bits of each register |
| | 56 | // and then assembling the final register value. |
| | 57 | |
| | 58 | /**********************************************************************/ |
| | 59 | |
| | 60 | // Register: PL111_REG_LCD_TIMING_0 |
| | 61 | #define HOR_AXIS_PANEL(hbp,hfp,hsw,hor_res) (UINT32)(((UINT32)(hbp) << 24) | ((UINT32)(hfp) << 16) | ((UINT32)(hsw) << 8) | (((UINT32)((hor_res)/16)-1) << 2)) |
| | 62 | |
| | 63 | // Register: PL111_REG_LCD_TIMING_1 |
| | 64 | #define VER_AXIS_PANEL(vbp,vfp,vsw,ver_res) (UINT32)(((UINT32)(vbp) << 24) | ((UINT32)(vfp) << 16) | ((UINT32)(vsw) << 10) | ((ver_res)-1)) |
| | 65 | |
| | 66 | // Register: PL111_REG_LCD_TIMING_2 |
| | 67 | #define PL111_BIT_SHIFT_PCD_HI 27 |
| | 68 | #define PL111_BIT_SHIFT_BCD 26 |
| | 69 | #define PL111_BIT_SHIFT_CPL 16 |
| | 70 | #define PL111_BIT_SHIFT_IOE 14 |
| | 71 | #define PL111_BIT_SHIFT_IPC 13 |
| | 72 | #define PL111_BIT_SHIFT_IHS 12 |
| | 73 | #define PL111_BIT_SHIFT_IVS 11 |
| | 74 | #define PL111_BIT_SHIFT_ACB 6 |
| | 75 | #define PL111_BIT_SHIFT_CLKSEL 5 |
| | 76 | #define PL111_BIT_SHIFT_PCD_LO 0 |
| | 77 | |
| | 78 | #define PL111_BCD (1 << 26) |
| | 79 | #define PL111_IPC (1 << 13) |
| | 80 | #define PL111_IHS (1 << 12) |
| | 81 | #define PL111_IVS (1 << 11) |
| | 82 | |
| | 83 | #define CLK_SIG_POLARITY(hor_res) (UINT32)(PL111_BCD | PL111_IPC | PL111_IHS | PL111_IVS | (((hor_res)-1) << 16)) |
| | 84 | |
| | 85 | // Register: PL111_REG_LCD_TIMING_3 |
| | 86 | #define PL111_BIT_SHIFT_LEE 16 |
| | 87 | #define PL111_BIT_SHIFT_LED 0 |
| | 88 | |
| | 89 | #define PL111_CTRL_WATERMARK (1 << 16) |
| | 90 | #define PL111_CTRL_LCD_V_COMP (1 << 12) |
| | 91 | #define PL111_CTRL_LCD_PWR (1 << 11) |
| | 92 | #define PL111_CTRL_BEPO (1 << 10) |
| | 93 | #define PL111_CTRL_BEBO (1 << 9) |
| | 94 | #define PL111_CTRL_BGR (1 << 8) |
| | 95 | #define PL111_CTRL_LCD_DUAL (1 << 7) |
| | 96 | #define PL111_CTRL_LCD_MONO_8 (1 << 6) |
| | 97 | #define PL111_CTRL_LCD_TFT (1 << 5) |
| | 98 | #define PL111_CTRL_LCD_BW (1 << 4) |
| | 99 | #define PL111_CTRL_LCD_1BPP (0 << 1) |
| | 100 | #define PL111_CTRL_LCD_2BPP (1 << 1) |
| | 101 | #define PL111_CTRL_LCD_4BPP (2 << 1) |
| | 102 | #define PL111_CTRL_LCD_8BPP (3 << 1) |
| | 103 | #define PL111_CTRL_LCD_16BPP (4 << 1) |
| | 104 | #define PL111_CTRL_LCD_24BPP (5 << 1) |
| | 105 | #define PL111_CTRL_LCD_16BPP_565 (6 << 1) |
| | 106 | #define PL111_CTRL_LCD_12BPP_444 (7 << 1) |
| | 107 | #define PL111_CTRL_LCD_BPP(Bpp) ((Bpp) << 1) |
| | 108 | #define PL111_CTRL_LCD_EN 1 |
| | 109 | |
| | 110 | /**********************************************************************/ |
| | 111 | |
| | 112 | // Register: PL111_REG_LCD_TIMING_0 |
| | 113 | #define PL111_LCD_TIMING_0_HBP(hbp) (((hbp) & 0xFF) << 24) |
| | 114 | #define PL111_LCD_TIMING_0_HFP(hfp) (((hfp) & 0xFF) << 16) |
| | 115 | #define PL111_LCD_TIMING_0_HSW(hsw) (((hsw) & 0xFF) << 8) |
| | 116 | #define PL111_LCD_TIMING_0_PPL(ppl) (((hsw) & 0x3F) << 2) |
| | 117 | |
| | 118 | // Register: PL111_REG_LCD_TIMING_1 |
| | 119 | #define PL111_LCD_TIMING_1_VBP(vbp) (((vbp) & 0xFF) << 24) |
| | 120 | #define PL111_LCD_TIMING_1_VFP(vfp) (((vfp) & 0xFF) << 16) |
| | 121 | #define PL111_LCD_TIMING_1_VSW(vsw) (((vsw) & 0x3F) << 10) |
| | 122 | #define PL111_LCD_TIMING_1_LPP(lpp) ((lpp) & 0xFC) |
| | 123 | |
| | 124 | // Register: PL111_REG_LCD_TIMING_2 |
| | 125 | #define PL111_BIT_MASK_PCD_HI 0xF8000000 |
| | 126 | #define PL111_BIT_MASK_BCD 0x04000000 |
| | 127 | #define PL111_BIT_MASK_CPL 0x03FF0000 |
| | 128 | #define PL111_BIT_MASK_IOE 0x00004000 |
| | 129 | #define PL111_BIT_MASK_IPC 0x00002000 |
| | 130 | #define PL111_BIT_MASK_IHS 0x00001000 |
| | 131 | #define PL111_BIT_MASK_IVS 0x00000800 |
| | 132 | #define PL111_BIT_MASK_ACB 0x000007C0 |
| | 133 | #define PL111_BIT_MASK_CLKSEL 0x00000020 |
| | 134 | #define PL111_BIT_MASK_PCD_LO 0x0000001F |
| | 135 | |
| | 136 | // Register: PL111_REG_LCD_TIMING_3 |
| | 137 | #define PL111_BIT_MASK_LEE 0x00010000 |
| | 138 | #define PL111_BIT_MASK_LED 0x0000007F |
| | 139 | |
| | 140 | #endif /* _PL111LCD_H__ */ |
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