| 1 | /** @file\r |
| 2 | *\r |
| 3 | * Copyright (c) 2011, ARM Limited. All rights reserved.\r |
| 4 | * \r |
| 5 | * This program and the accompanying materials \r |
| 6 | * are licensed and made available under the terms and conditions of the BSD License \r |
| 7 | * which accompanies this distribution. The full text of the license may be found at \r |
| 8 | * http://opensource.org/licenses/bsd-license.php \r |
| 9 | *\r |
| 10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r |
| 11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r |
| 12 | *\r |
| 13 | **/\r |
| 14 | \r |
| 15 | #include <Library/ArmPlatformLib.h>\r |
| 16 | #include <Library/DebugLib.h>\r |
| 17 | #include <Library/PcdLib.h>\r |
| 18 | #include <Library/MemoryAllocationLib.h>\r |
| 19 | #include <Library/IoLib.h>\r |
| 20 | \r |
| 21 | #include <BeagleBoard.h>\r |
| 22 | \r |
| 23 | #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 4\r |
| 24 | \r |
| 25 | /**\r |
| 26 | Return the Virtual Memory Map of your platform\r |
| 27 | \r |
| 28 | This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.\r |
| 29 | \r |
| 30 | @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-\r |
| 31 | Virtual Memory mapping. This array must be ended by a zero-filled\r |
| 32 | entry\r |
| 33 | \r |
| 34 | **/\r |
| 35 | VOID\r |
| 36 | ArmPlatformGetVirtualMemoryMap (\r |
| 37 | IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap\r |
| 38 | )\r |
| 39 | {\r |
| 40 | ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;\r |
| 41 | UINTN Index = 0;\r |
| 42 | ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;\r |
| 43 | \r |
| 44 | ASSERT(VirtualMemoryMap != NULL);\r |
| 45 | \r |
| 46 | VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));\r |
| 47 | if (VirtualMemoryTable == NULL) {\r |
| 48 | return;\r |
| 49 | }\r |
| 50 | \r |
| 51 | if (FeaturePcdGet(PcdCacheEnable) == TRUE) {\r |
| 52 | CacheAttributes = DDR_ATTRIBUTES_CACHED;\r |
| 53 | } else {\r |
| 54 | CacheAttributes = DDR_ATTRIBUTES_UNCACHED;\r |
| 55 | }\r |
| 56 | \r |
| 57 | // ReMap (Either NOR Flash or DRAM)\r |
| 58 | VirtualMemoryTable[Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);\r |
| 59 | VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase);\r |
| 60 | VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize);\r |
| 61 | VirtualMemoryTable[Index].Attributes = CacheAttributes;\r |
| 62 | \r |
| 63 | // SOC Registers. L3 interconnects\r |
| 64 | VirtualMemoryTable[++Index].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE;\r |
| 65 | VirtualMemoryTable[Index].VirtualBase = SOC_REGISTERS_L3_PHYSICAL_BASE;\r |
| 66 | VirtualMemoryTable[Index].Length = SOC_REGISTERS_L3_PHYSICAL_LENGTH;\r |
| 67 | VirtualMemoryTable[Index].Attributes = SOC_REGISTERS_L3_ATTRIBUTES;\r |
| 68 | \r |
| 69 | // SOC Registers. L4 interconnects\r |
| 70 | VirtualMemoryTable[++Index].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE;\r |
| 71 | VirtualMemoryTable[Index].VirtualBase = SOC_REGISTERS_L4_PHYSICAL_BASE;\r |
| 72 | VirtualMemoryTable[Index].Length = SOC_REGISTERS_L4_PHYSICAL_LENGTH;\r |
| 73 | VirtualMemoryTable[Index].Attributes = SOC_REGISTERS_L4_ATTRIBUTES;\r |
| 74 | \r |
| 75 | // End of Table\r |
| 76 | VirtualMemoryTable[++Index].PhysicalBase = 0;\r |
| 77 | VirtualMemoryTable[Index].VirtualBase = 0;\r |
| 78 | VirtualMemoryTable[Index].Length = 0;\r |
| 79 | VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r |
| 80 | \r |
| 81 | ASSERT((Index + 1) == MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);\r |
| 82 | \r |
| 83 | *VirtualMemoryMap = VirtualMemoryTable;\r |
| 84 | }\r |