| 1 | /** @file\r |
| 2 | C Entry point for the SEC. First C code after the reset vector.\r |
| 3 | \r |
| 4 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r |
| 5 | \r |
| 6 | This program and the accompanying materials\r |
| 7 | are licensed and made available under the terms and conditions of the BSD License\r |
| 8 | which accompanies this distribution. The full text of the license may be found at\r |
| 9 | http://opensource.org/licenses/bsd-license.php\r |
| 10 | \r |
| 11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| 13 | \r |
| 14 | **/\r |
| 15 | \r |
| 16 | #include <PiPei.h>\r |
| 17 | \r |
| 18 | #include <Library/DebugLib.h>\r |
| 19 | #include <Library/PrePiLib.h>\r |
| 20 | #include <Library/PcdLib.h>\r |
| 21 | #include <Library/IoLib.h>\r |
| 22 | #include <Library/OmapLib.h>\r |
| 23 | #include <Library/ArmLib.h>\r |
| 24 | #include <Library/PeCoffGetEntryPointLib.h>\r |
| 25 | #include <Library/DebugAgentLib.h>\r |
| 26 | \r |
| 27 | #include <Ppi/GuidedSectionExtraction.h>\r |
| 28 | #include <Guid/LzmaDecompress.h>\r |
| 29 | #include <Omap3530/Omap3530.h>\r |
| 30 | \r |
| 31 | #include "LzmaDecompress.h"\r |
| 32 | \r |
| 33 | VOID\r |
| 34 | PadConfiguration (\r |
| 35 | VOID\r |
| 36 | );\r |
| 37 | \r |
| 38 | VOID\r |
| 39 | ClockInit (\r |
| 40 | VOID\r |
| 41 | );\r |
| 42 | \r |
| 43 | \r |
| 44 | VOID\r |
| 45 | TimerInit (\r |
| 46 | VOID\r |
| 47 | )\r |
| 48 | {\r |
| 49 | UINTN Timer = FixedPcdGet32(PcdOmap35xxFreeTimer);\r |
| 50 | UINT32 TimerBaseAddress = TimerBase(Timer);\r |
| 51 | \r |
| 52 | // Set source clock for GPT3 & GPT4 to SYS_CLK\r |
| 53 | MmioOr32 (CM_CLKSEL_PER, CM_CLKSEL_PER_CLKSEL_GPT3_SYS | CM_CLKSEL_PER_CLKSEL_GPT4_SYS);\r |
| 54 | \r |
| 55 | // Set count & reload registers\r |
| 56 | MmioWrite32 (TimerBaseAddress + GPTIMER_TCRR, 0x00000000);\r |
| 57 | MmioWrite32 (TimerBaseAddress + GPTIMER_TLDR, 0x00000000);\r |
| 58 | \r |
| 59 | // Disable interrupts\r |
| 60 | MmioWrite32 (TimerBaseAddress + GPTIMER_TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_DISABLE | TIER_MAT_IT_DISABLE);\r |
| 61 | \r |
| 62 | // Start Timer\r |
| 63 | MmioWrite32 (TimerBaseAddress + GPTIMER_TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);\r |
| 64 | \r |
| 65 | //Disable OMAP Watchdog timer (WDT2)\r |
| 66 | MmioWrite32 (WDTIMER2_BASE + WSPR, 0xAAAA);\r |
| 67 | DEBUG ((EFI_D_ERROR, "Magic delay to disable watchdog timers properly.\n"));\r |
| 68 | MmioWrite32 (WDTIMER2_BASE + WSPR, 0x5555);\r |
| 69 | }\r |
| 70 | \r |
| 71 | VOID\r |
| 72 | UartInit (\r |
| 73 | VOID\r |
| 74 | )\r |
| 75 | {\r |
| 76 | UINTN Uart = FixedPcdGet32(PcdOmap35xxConsoleUart);\r |
| 77 | UINT32 UartBaseAddress = UartBase(Uart);\r |
| 78 | \r |
| 79 | // Set MODE_SELECT=DISABLE before trying to initialize or modify DLL, DLH registers.\r |
| 80 | MmioWrite32 (UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_DISABLE);\r |
| 81 | \r |
| 82 | // Put device in configuration mode.\r |
| 83 | MmioWrite32 (UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_ENABLE);\r |
| 84 | \r |
| 85 | // Programmable divisor N = 48Mhz/16/115200 = 26\r |
| 86 | MmioWrite32 (UartBaseAddress + UART_DLL_REG, 3000000/FixedPcdGet64 (PcdUartDefaultBaudRate)); // low divisor\r |
| 87 | MmioWrite32 (UartBaseAddress + UART_DLH_REG, 0); // high divisor\r |
| 88 | \r |
| 89 | // Enter into UART operational mode.\r |
| 90 | MmioWrite32 (UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_DISABLE | UART_LCR_CHAR_LENGTH_8);\r |
| 91 | \r |
| 92 | // Force DTR and RTS output to active\r |
| 93 | MmioWrite32 (UartBaseAddress + UART_MCR_REG, UART_MCR_RTS_FORCE_ACTIVE | UART_MCR_DTR_FORCE_ACTIVE);\r |
| 94 | \r |
| 95 | // Clear & enable fifos\r |
| 96 | MmioWrite32 (UartBaseAddress + UART_FCR_REG, UART_FCR_TX_FIFO_CLEAR | UART_FCR_RX_FIFO_CLEAR | UART_FCR_FIFO_ENABLE); \r |
| 97 | \r |
| 98 | // Restore MODE_SELECT \r |
| 99 | MmioWrite32 (UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_UART_16X);\r |
| 100 | }\r |
| 101 | \r |
| 102 | VOID\r |
| 103 | InitCache (\r |
| 104 | IN UINT32 MemoryBase,\r |
| 105 | IN UINT32 MemoryLength\r |
| 106 | );\r |
| 107 | \r |
| 108 | EFI_STATUS\r |
| 109 | EFIAPI\r |
| 110 | ExtractGuidedSectionLibConstructor (\r |
| 111 | VOID\r |
| 112 | );\r |
| 113 | \r |
| 114 | EFI_STATUS\r |
| 115 | EFIAPI\r |
| 116 | LzmaDecompressLibConstructor (\r |
| 117 | VOID\r |
| 118 | );\r |
| 119 | \r |
| 120 | \r |
| 121 | VOID\r |
| 122 | CEntryPoint (\r |
| 123 | IN VOID *MemoryBase,\r |
| 124 | IN UINTN MemorySize,\r |
| 125 | IN VOID *StackBase,\r |
| 126 | IN UINTN StackSize\r |
| 127 | )\r |
| 128 | {\r |
| 129 | VOID *HobBase;\r |
| 130 | \r |
| 131 | // Build a basic HOB list\r |
| 132 | HobBase = (VOID *)(UINTN)(FixedPcdGet32(PcdEmbeddedFdBaseAddress) + FixedPcdGet32(PcdEmbeddedFdSize));\r |
| 133 | CreateHobList (MemoryBase, MemorySize, HobBase, StackBase);\r |
| 134 | \r |
| 135 | //Set up Pin muxing.\r |
| 136 | PadConfiguration ();\r |
| 137 | \r |
| 138 | // Set up system clocking\r |
| 139 | ClockInit ();\r |
| 140 | \r |
| 141 | \r |
| 142 | // Enable program flow prediction, if supported.\r |
| 143 | ArmEnableBranchPrediction ();\r |
| 144 | \r |
| 145 | // Initialize CPU cache\r |
| 146 | InitCache ((UINT32)MemoryBase, (UINT32)MemorySize);\r |
| 147 | \r |
| 148 | // Add memory allocation hob for relocated FD\r |
| 149 | BuildMemoryAllocationHob (FixedPcdGet32(PcdEmbeddedFdBaseAddress), FixedPcdGet32(PcdEmbeddedFdSize), EfiBootServicesData);\r |
| 150 | \r |
| 151 | // Add the FVs to the hob list\r |
| 152 | BuildFvHob (PcdGet32(PcdFlashFvMainBase), PcdGet32(PcdFlashFvMainSize));\r |
| 153 | \r |
| 154 | // Start talking\r |
| 155 | UartInit ();\r |
| 156 | \r |
| 157 | InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL);\r |
| 158 | SaveAndSetDebugTimerInterrupt (TRUE);\r |
| 159 | \r |
| 160 | DEBUG ((EFI_D_ERROR, "UART Enabled\n"));\r |
| 161 | \r |
| 162 | // Start up a free running timer so that the timer lib will work\r |
| 163 | TimerInit ();\r |
| 164 | \r |
| 165 | // SEC phase needs to run library constructors by hand.\r |
| 166 | ExtractGuidedSectionLibConstructor ();\r |
| 167 | LzmaDecompressLibConstructor ();\r |
| 168 | \r |
| 169 | // Build HOBs to pass up our version of stuff the DXE Core needs to save space\r |
| 170 | BuildPeCoffLoaderHob ();\r |
| 171 | BuildExtractSectionHob (\r |
| 172 | &gLzmaCustomDecompressGuid,\r |
| 173 | LzmaGuidedSectionGetInfo,\r |
| 174 | LzmaGuidedSectionExtraction\r |
| 175 | );\r |
| 176 | \r |
| 177 | // Assume the FV that contains the SEC (our code) also contains a compressed FV.\r |
| 178 | DecompressFirstFv ();\r |
| 179 | \r |
| 180 | // Load the DXE Core and transfer control to it\r |
| 181 | LoadDxeCoreFromFv (NULL, 0);\r |
| 182 | \r |
| 183 | // DXE Core should always load and never return\r |
| 184 | ASSERT (FALSE);\r |
| 185 | }\r |
| 186 | \r |