| | 1 | /** @file\r |
| | 2 | Include file for PC-AT compatability.\r |
| | 3 | \r |
| | 4 | Copyright (c) 2006, Intel Corporation. All rights reserved. \r |
| | 5 | This software and associated documentation (if any) is furnished\r |
| | 6 | under a license and may only be used or copied in accordance\r |
| | 7 | with the terms of the license. Except as permitted by such\r |
| | 8 | license, no part of this software or documentation may be\r |
| | 9 | reproduced, stored in a retrieval system, or transmitted in any\r |
| | 10 | form or by any means without the express written consent of\r |
| | 11 | Intel Corporation.\r |
| | 12 | \r |
| | 13 | **/\r |
| | 14 | \r |
| | 15 | #ifndef _PC_AT_H_\r |
| | 16 | #define _PC_AT_H_\r |
| | 17 | \r |
| | 18 | //\r |
| | 19 | // 8254 Timer\r |
| | 20 | //\r |
| | 21 | #define TIMER0_COUNT_PORT 0x40\r |
| | 22 | #define TIMER1_COUNT_PORT 0x41\r |
| | 23 | #define TIMER2_COUNT_PORT 0x42\r |
| | 24 | #define TIMER_CONTROL_PORT 0x43\r |
| | 25 | \r |
| | 26 | //\r |
| | 27 | // 8259 PIC interrupt controller\r |
| | 28 | //\r |
| | 29 | \r |
| | 30 | #define PIC_CONTROL_REGISTER_MASTER 0x20\r |
| | 31 | #define PIC_MASK_REGISTER_MASTER 0x21\r |
| | 32 | #define PIC_CONTROL_REGISTER_SLAVE 0xA0\r |
| | 33 | #define PIC_MASK_REGISTER_SLAVE 0xA1\r |
| | 34 | #define PIC_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER 0x4D0\r |
| | 35 | #define PIC_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE 0x4D1\r |
| | 36 | \r |
| | 37 | #define PIC_EOI 0x20\r |
| | 38 | \r |
| | 39 | //\r |
| | 40 | // 8237 DMA registers\r |
| | 41 | //\r |
| | 42 | #define R_8237_DMA_BASE_CA_CH0 0x00\r |
| | 43 | #define R_8237_DMA_BASE_CA_CH1 0x02\r |
| | 44 | #define R_8237_DMA_BASE_CA_CH2 0x04\r |
| | 45 | #define R_8237_DMA_BASE_CA_CH3 0xd6\r |
| | 46 | #define R_8237_DMA_BASE_CA_CH5 0xc4\r |
| | 47 | #define R_8237_DMA_BASE_CA_CH6 0xc8\r |
| | 48 | #define R_8237_DMA_BASE_CA_CH7 0xcc\r |
| | 49 | \r |
| | 50 | #define R_8237_DMA_BASE_CC_CH0 0x01\r |
| | 51 | #define R_8237_DMA_BASE_CC_CH1 0x03\r |
| | 52 | #define R_8237_DMA_BASE_CC_CH2 0x05\r |
| | 53 | #define R_8237_DMA_BASE_CC_CH3 0xd7\r |
| | 54 | #define R_8237_DMA_BASE_CC_CH5 0xc6\r |
| | 55 | #define R_8237_DMA_BASE_CC_CH6 0xca\r |
| | 56 | #define R_8237_DMA_BASE_CC_CH7 0xce\r |
| | 57 | \r |
| | 58 | #define R_8237_DMA_MEM_LP_CH0 0x87\r |
| | 59 | #define R_8237_DMA_MEM_LP_CH1 0x83\r |
| | 60 | #define R_8237_DMA_MEM_LP_CH2 0x81\r |
| | 61 | #define R_8237_DMA_MEM_LP_CH3 0x82\r |
| | 62 | #define R_8237_DMA_MEM_LP_CH5 0x8B\r |
| | 63 | #define R_8237_DMA_MEM_LP_CH6 0x89\r |
| | 64 | #define R_8237_DMA_MEM_LP_CH7 0x8A\r |
| | 65 | \r |
| | 66 | \r |
| | 67 | #define R_8237_DMA_COMMAND_CH0_3 0x08\r |
| | 68 | #define R_8237_DMA_COMMAND_CH4_7 0xd0\r |
| | 69 | #define B_8237_DMA_COMMAND_GAP 0x10\r |
| | 70 | #define B_8237_DMA_COMMAND_CGE 0x04\r |
| | 71 | \r |
| | 72 | \r |
| | 73 | #define R_8237_DMA_STA_CH0_3 0xd8\r |
| | 74 | #define R_8237_DMA_STA_CH4_7 0xd0\r |
| | 75 | \r |
| | 76 | #define R_8237_DMA_WRSMSK_CH0_3 0x0a\r |
| | 77 | #define R_8237_DMA_WRSMSK_CH4_7 0xd4\r |
| | 78 | #define B_8237_DMA_WRSMSK_CMS 0x04\r |
| | 79 | \r |
| | 80 | \r |
| | 81 | #define R_8237_DMA_CHMODE_CH0_3 0x0b\r |
| | 82 | #define R_8237_DMA_CHMODE_CH4_7 0xd6\r |
| | 83 | #define V_8237_DMA_CHMODE_DEMAND 0x00\r |
| | 84 | #define V_8237_DMA_CHMODE_SINGLE 0x40\r |
| | 85 | #define V_8237_DMA_CHMODE_CASCADE 0xc0\r |
| | 86 | #define B_8237_DMA_CHMODE_DECREMENT 0x20\r |
| | 87 | #define B_8237_DMA_CHMODE_INCREMENT 0x00\r |
| | 88 | #define B_8237_DMA_CHMODE_AE 0x10\r |
| | 89 | #define V_8237_DMA_CHMODE_VERIFY 0\r |
| | 90 | #define V_8237_DMA_CHMODE_IO2MEM 0x04\r |
| | 91 | #define V_8237_DMA_CHMODE_MEM2IO 0x08\r |
| | 92 | \r |
| | 93 | #define R_8237_DMA_CBPR_CH0_3 0x0c\r |
| | 94 | #define R_8237_DMA_CBPR_CH4_7 0xd8\r |
| | 95 | \r |
| | 96 | #define R_8237_DMA_MCR_CH0_3 0x0d\r |
| | 97 | #define R_8237_DMA_MCR_CH4_7 0xda\r |
| | 98 | \r |
| | 99 | #define R_8237_DMA_CLMSK_CH0_3 0x0e\r |
| | 100 | #define R_8237_DMA_CLMSK_CH4_7 0xdc\r |
| | 101 | \r |
| | 102 | #define R_8237_DMA_WRMSK_CH0_3 0x0f\r |
| | 103 | #define R_8237_DMA_WRMSK_CH4_7 0xde\r |
| | 104 | \r |
| | 105 | #endif\r |
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