| | 1 | /** @file\r |
| | 2 | Intel FSP Info Header definition from Intel Firmware Support Package External\r |
| | 3 | Architecture Specification v1.1, April 2015, revision 001.\r |
| | 4 | \r |
| | 5 | Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r |
| | 6 | This program and the accompanying materials\r |
| | 7 | are licensed and made available under the terms and conditions of the BSD License\r |
| | 8 | which accompanies this distribution. The full text of the license may be found at\r |
| | 9 | http://opensource.org/licenses/bsd-license.php.\r |
| | 10 | \r |
| | 11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| | 12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| | 13 | \r |
| | 14 | **/\r |
| | 15 | \r |
| | 16 | #ifndef _FSP_INFO_HEADER_H_\r |
| | 17 | #define _FSP_INFO_HEADER_H_\r |
| | 18 | \r |
| | 19 | #define FSP_HEADER_REVISION_1 1\r |
| | 20 | #define FSP_HEADER_REVISION_2 2\r |
| | 21 | \r |
| | 22 | #define FSPE_HEADER_REVISION_1 1\r |
| | 23 | #define FSPP_HEADER_REVISION_1 1\r |
| | 24 | \r |
| | 25 | ///\r |
| | 26 | /// Fixed FSP header offset in the FSP image\r |
| | 27 | ///\r |
| | 28 | #define FSP_INFO_HEADER_OFF 0x94\r |
| | 29 | \r |
| | 30 | #define OFFSET_IN_FSP_INFO_HEADER(x) (UINT32)&((FSP_INFO_HEADER *)(UINTN)0)->x\r |
| | 31 | \r |
| | 32 | #define FSP_INFO_HEADER_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'H')\r |
| | 33 | \r |
| | 34 | #pragma pack(1)\r |
| | 35 | \r |
| | 36 | typedef struct {\r |
| | 37 | ///\r |
| | 38 | /// Byte 0x00: Signature ('FSPH') for the FSP Information Header\r |
| | 39 | ///\r |
| | 40 | UINT32 Signature;\r |
| | 41 | ///\r |
| | 42 | /// Byte 0x04: Length of the FSP Information Header\r |
| | 43 | ///\r |
| | 44 | UINT32 HeaderLength;\r |
| | 45 | ///\r |
| | 46 | /// Byte 0x08: Reserved\r |
| | 47 | ///\r |
| | 48 | UINT8 Reserved1[3];\r |
| | 49 | ///\r |
| | 50 | /// Byte 0x0B: Revision of the FSP Information Header\r |
| | 51 | ///\r |
| | 52 | UINT8 HeaderRevision;\r |
| | 53 | ///\r |
| | 54 | /// Byte 0x0C: Revision of the FSP binary\r |
| | 55 | ///\r |
| | 56 | UINT32 ImageRevision;\r |
| | 57 | \r |
| | 58 | \r |
| | 59 | ///\r |
| | 60 | /// Byte 0x10: Signature string that will help match the FSP Binary to a supported\r |
| | 61 | /// hardware configuration.\r |
| | 62 | ///\r |
| | 63 | CHAR8 ImageId[8];\r |
| | 64 | ///\r |
| | 65 | /// Byte 0x18: Size of the entire FSP binary\r |
| | 66 | ///\r |
| | 67 | UINT32 ImageSize;\r |
| | 68 | ///\r |
| | 69 | /// Byte 0x1C: FSP binary preferred base address\r |
| | 70 | ///\r |
| | 71 | UINT32 ImageBase;\r |
| | 72 | \r |
| | 73 | \r |
| | 74 | ///\r |
| | 75 | /// Byte 0x20: Attribute for the FSP binary\r |
| | 76 | ///\r |
| | 77 | UINT32 ImageAttribute;\r |
| | 78 | ///\r |
| | 79 | /// Byte 0x24: Offset of the FSP configuration region\r |
| | 80 | ///\r |
| | 81 | UINT32 CfgRegionOffset;\r |
| | 82 | ///\r |
| | 83 | /// Byte 0x28: Size of the FSP configuration region\r |
| | 84 | ///\r |
| | 85 | UINT32 CfgRegionSize;\r |
| | 86 | ///\r |
| | 87 | /// Byte 0x2C: Number of API entries this FSP supports\r |
| | 88 | ///\r |
| | 89 | UINT32 ApiEntryNum;\r |
| | 90 | \r |
| | 91 | \r |
| | 92 | ///\r |
| | 93 | /// Byte 0x30: The offset for the API to setup a temporary stack till the memory\r |
| | 94 | /// is initialized.\r |
| | 95 | ///\r |
| | 96 | UINT32 TempRamInitEntryOffset;\r |
| | 97 | ///\r |
| | 98 | /// Byte 0x34: The offset for the API to initialize the CPU and the chipset (SOC)\r |
| | 99 | ///\r |
| | 100 | UINT32 FspInitEntryOffset;\r |
| | 101 | ///\r |
| | 102 | /// Byte 0x38: The offset for the API to inform the FSP about the different stages\r |
| | 103 | /// in the boot process\r |
| | 104 | ///\r |
| | 105 | UINT32 NotifyPhaseEntryOffset;\r |
| | 106 | \r |
| | 107 | ///\r |
| | 108 | /// Below fields are added in FSP Revision 2\r |
| | 109 | ///\r |
| | 110 | \r |
| | 111 | ///\r |
| | 112 | /// Byte 0x3C: The offset for the API to initialize the memory\r |
| | 113 | ///\r |
| | 114 | UINT32 FspMemoryInitEntryOffset;\r |
| | 115 | ///\r |
| | 116 | /// Byte 0x40: The offset for the API to tear down temporary RAM\r |
| | 117 | ///\r |
| | 118 | UINT32 TempRamExitEntryOffset;\r |
| | 119 | ///\r |
| | 120 | /// Byte 0x44: The offset for the API to initialize the CPU and chipset\r |
| | 121 | ///\r |
| | 122 | UINT32 FspSiliconInitEntryOffset;\r |
| | 123 | \r |
| | 124 | } FSP_INFO_HEADER;\r |
| | 125 | \r |
| | 126 | ///\r |
| | 127 | /// Below structure is added in FSP version 2\r |
| | 128 | ///\r |
| | 129 | #define FSP_INFO_EXTENDED_HEADER_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'E')\r |
| | 130 | \r |
| | 131 | typedef struct {\r |
| | 132 | ///\r |
| | 133 | /// Byte 0x00: Signature ('FSPE') for the FSP Extended Information Header\r |
| | 134 | ///\r |
| | 135 | UINT32 Signature;\r |
| | 136 | ///\r |
| | 137 | /// Byte 0x04: Length of the table in bytes, including all additional FSP producer defined data.\r |
| | 138 | ///\r |
| | 139 | UINT32 Length;\r |
| | 140 | ///\r |
| | 141 | /// Byte 0x08: FSP producer defined revision of the table.\r |
| | 142 | ///\r |
| | 143 | UINT8 Revision;\r |
| | 144 | ///\r |
| | 145 | /// Byte 0x09: Reserved for future use.\r |
| | 146 | ///\r |
| | 147 | UINT8 Reserved;\r |
| | 148 | ///\r |
| | 149 | /// Byte 0x0A: FSP producer identification string \r |
| | 150 | ///\r |
| | 151 | CHAR8 FspProducerId[6];\r |
| | 152 | ///\r |
| | 153 | /// Byte 0x10: FSP producer implementation revision number. Larger numbers are assumed to be newer revisions.\r |
| | 154 | ///\r |
| | 155 | UINT32 FspProducerRevision;\r |
| | 156 | ///\r |
| | 157 | /// Byte 0x14: Size of the FSP producer defined data (n) in bytes.\r |
| | 158 | ///\r |
| | 159 | UINT32 FspProducerDataSize;\r |
| | 160 | ///\r |
| | 161 | /// Byte 0x18: FSP producer defined data of size (n) defined by FspProducerDataSize.\r |
| | 162 | ///\r |
| | 163 | \r |
| | 164 | } FSP_INFO_EXTENDED_HEADER;\r |
| | 165 | \r |
| | 166 | #pragma pack()\r |
| | 167 | \r |
| | 168 | #endif\r |
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