| | 1 | /** @file\r |
| | 2 | The definition for VTD register.\r |
| | 3 | It is defined in "Intel VT for Direct IO Architecture Specification".\r |
| | 4 | \r |
| | 5 | Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r |
| | 6 | This program and the accompanying materials\r |
| | 7 | are licensed and made available under the terms and conditions of the BSD License\r |
| | 8 | which accompanies this distribution. The full text of the license may be found at\r |
| | 9 | http://opensource.org/licenses/bsd-license.php.\r |
| | 10 | \r |
| | 11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| | 12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| | 13 | \r |
| | 14 | **/\r |
| | 15 | \r |
| | 16 | #ifndef __VTD_REG_H__\r |
| | 17 | #define __VTD_REG_H__\r |
| | 18 | \r |
| | 19 | #pragma pack(1)\r |
| | 20 | \r |
| | 21 | //\r |
| | 22 | // Translation Structure Formats\r |
| | 23 | //\r |
| | 24 | #define VTD_ROOT_ENTRY_NUMBER 256\r |
| | 25 | #define VTD_CONTEXT_ENTRY_NUMBER 256\r |
| | 26 | \r |
| | 27 | typedef union {\r |
| | 28 | struct {\r |
| | 29 | UINT32 Present:1;\r |
| | 30 | UINT32 Reserved_1:11;\r |
| | 31 | UINT32 ContextTablePointerLo:20;\r |
| | 32 | UINT32 ContextTablePointerHi:32;\r |
| | 33 | \r |
| | 34 | UINT64 Reserved_64;\r |
| | 35 | } Bits;\r |
| | 36 | struct {\r |
| | 37 | UINT64 Uint64Lo;\r |
| | 38 | UINT64 Uint64Hi;\r |
| | 39 | } Uint128;\r |
| | 40 | } VTD_ROOT_ENTRY;\r |
| | 41 | \r |
| | 42 | typedef union {\r |
| | 43 | struct {\r |
| | 44 | UINT32 LowerPresent:1;\r |
| | 45 | UINT32 Reserved_1:11;\r |
| | 46 | UINT32 LowerContextTablePointerLo:20;\r |
| | 47 | UINT32 LowerContextTablePointerHi:32;\r |
| | 48 | \r |
| | 49 | UINT32 UpperPresent:1;\r |
| | 50 | UINT32 Reserved_65:11;\r |
| | 51 | UINT32 UpperContextTablePointerLo:20;\r |
| | 52 | UINT32 UpperContextTablePointerHi:32;\r |
| | 53 | } Bits;\r |
| | 54 | struct {\r |
| | 55 | UINT64 Uint64Lo;\r |
| | 56 | UINT64 Uint64Hi;\r |
| | 57 | } Uint128;\r |
| | 58 | } VTD_EXT_ROOT_ENTRY;\r |
| | 59 | \r |
| | 60 | typedef union {\r |
| | 61 | struct {\r |
| | 62 | UINT32 Present:1;\r |
| | 63 | UINT32 FaultProcessingDisable:1;\r |
| | 64 | UINT32 TranslationType:2;\r |
| | 65 | UINT32 Reserved_4:8;\r |
| | 66 | UINT32 SecondLevelPageTranslationPointerLo:20;\r |
| | 67 | UINT32 SecondLevelPageTranslationPointerHi:32;\r |
| | 68 | \r |
| | 69 | UINT32 AddressWidth:3;\r |
| | 70 | UINT32 Ignored_67:4;\r |
| | 71 | UINT32 Reserved_71:1;\r |
| | 72 | UINT32 DomainIdentifier:16;\r |
| | 73 | UINT32 Reserved_88:8;\r |
| | 74 | UINT32 Reserved_96:32;\r |
| | 75 | } Bits;\r |
| | 76 | struct {\r |
| | 77 | UINT64 Uint64Lo;\r |
| | 78 | UINT64 Uint64Hi;\r |
| | 79 | } Uint128;\r |
| | 80 | } VTD_CONTEXT_ENTRY;\r |
| | 81 | \r |
| | 82 | typedef union {\r |
| | 83 | struct {\r |
| | 84 | UINT32 Present:1;\r |
| | 85 | UINT32 FaultProcessingDisable:1;\r |
| | 86 | UINT32 TranslationType:3;\r |
| | 87 | UINT32 ExtendedMemoryType:3;\r |
| | 88 | UINT32 DeferredInvalidateEnable:1;\r |
| | 89 | UINT32 PageRequestEnable:1;\r |
| | 90 | UINT32 NestedTranslationEnable:1;\r |
| | 91 | UINT32 PASIDEnable:1;\r |
| | 92 | UINT32 SecondLevelPageTranslationPointerLo:20;\r |
| | 93 | UINT32 SecondLevelPageTranslationPointerHi:32;\r |
| | 94 | \r |
| | 95 | UINT32 AddressWidth:3;\r |
| | 96 | UINT32 PageGlobalEnable:1;\r |
| | 97 | UINT32 NoExecuteEnable:1;\r |
| | 98 | UINT32 WriteProtectEnable:1;\r |
| | 99 | UINT32 CacheDisable:1;\r |
| | 100 | UINT32 ExtendedMemoryTypeEnable:1;\r |
| | 101 | UINT32 DomainIdentifier:16;\r |
| | 102 | UINT32 SupervisorModeExecuteProtection:1;\r |
| | 103 | UINT32 ExtendedAccessedFlagEnable:1;\r |
| | 104 | UINT32 ExecuteRequestsEnable:1;\r |
| | 105 | UINT32 SecondLevelExecuteEnable:1;\r |
| | 106 | UINT32 Reserved_92:4;\r |
| | 107 | UINT32 PageAttributeTable0:3;\r |
| | 108 | UINT32 Reserved_Pat0:1;\r |
| | 109 | UINT32 PageAttributeTable1:3;\r |
| | 110 | UINT32 Reserved_Pat1:1;\r |
| | 111 | UINT32 PageAttributeTable2:3;\r |
| | 112 | UINT32 Reserved_Pat2:1;\r |
| | 113 | UINT32 PageAttributeTable3:3;\r |
| | 114 | UINT32 Reserved_Pat3:1;\r |
| | 115 | UINT32 PageAttributeTable4:3;\r |
| | 116 | UINT32 Reserved_Pat4:1;\r |
| | 117 | UINT32 PageAttributeTable5:3;\r |
| | 118 | UINT32 Reserved_Pat5:1;\r |
| | 119 | UINT32 PageAttributeTable6:3;\r |
| | 120 | UINT32 Reserved_Pat6:1;\r |
| | 121 | UINT32 PageAttributeTable7:3;\r |
| | 122 | UINT32 Reserved_Pat7:1;\r |
| | 123 | \r |
| | 124 | UINT32 PASIDTableSize:4;\r |
| | 125 | UINT32 Reserved_132:8;\r |
| | 126 | UINT32 PASIDTablePointerLo:20;\r |
| | 127 | UINT32 PASIDTablePointerHi:32;\r |
| | 128 | \r |
| | 129 | UINT32 Reserved_192:12;\r |
| | 130 | UINT32 PASIDStateTablePointerLo:20;\r |
| | 131 | UINT32 PASIDStateTablePointerHi:32;\r |
| | 132 | } Bits;\r |
| | 133 | struct {\r |
| | 134 | UINT64 Uint64_1;\r |
| | 135 | UINT64 Uint64_2;\r |
| | 136 | UINT64 Uint64_3;\r |
| | 137 | UINT64 Uint64_4;\r |
| | 138 | } Uint256;\r |
| | 139 | } VTD_EXT_CONTEXT_ENTRY;\r |
| | 140 | \r |
| | 141 | typedef union {\r |
| | 142 | struct {\r |
| | 143 | UINT32 Present:1;\r |
| | 144 | UINT32 Reserved_1:2;\r |
| | 145 | UINT32 PageLevelCacheDisable:1;\r |
| | 146 | UINT32 PageLevelWriteThrough:1;\r |
| | 147 | UINT32 Reserved_5:6;\r |
| | 148 | UINT32 SupervisorRequestsEnable:1;\r |
| | 149 | UINT32 FirstLevelPageTranslationPointerLo:20;\r |
| | 150 | UINT32 FirstLevelPageTranslationPointerHi:32;\r |
| | 151 | } Bits;\r |
| | 152 | UINT64 Uint64;\r |
| | 153 | } VTD_PASID_ENTRY;\r |
| | 154 | \r |
| | 155 | typedef union {\r |
| | 156 | struct {\r |
| | 157 | UINT32 Reserved_0:32;\r |
| | 158 | UINT32 ActiveReferenceCount:16;\r |
| | 159 | UINT32 Reserved_48:15;\r |
| | 160 | UINT32 DeferredInvalidate:1;\r |
| | 161 | } Bits;\r |
| | 162 | UINT64 Uint64;\r |
| | 163 | } VTD_PASID_STATE_ENTRY;\r |
| | 164 | \r |
| | 165 | typedef union {\r |
| | 166 | struct {\r |
| | 167 | UINT32 Present:1;\r |
| | 168 | UINT32 ReadWrite:1;\r |
| | 169 | UINT32 UserSupervisor:1;\r |
| | 170 | UINT32 PageLevelWriteThrough:1;\r |
| | 171 | UINT32 PageLevelCacheDisable:1;\r |
| | 172 | UINT32 Accessed:1;\r |
| | 173 | UINT32 Dirty:1;\r |
| | 174 | UINT32 PageSize:1; // It is PageAttribute:1 for 4K page entry\r |
| | 175 | UINT32 Global:1;\r |
| | 176 | UINT32 Ignored_9:1;\r |
| | 177 | UINT32 ExtendedAccessed:1;\r |
| | 178 | UINT32 Ignored_11:1;\r |
| | 179 | // NOTE: There is PageAttribute:1 as bit12 for 1G page entry and 2M page entry\r |
| | 180 | UINT32 AddressLo:20;\r |
| | 181 | UINT32 AddressHi:20;\r |
| | 182 | UINT32 Ignored_52:11;\r |
| | 183 | UINT32 ExecuteDisable:1;\r |
| | 184 | } Bits;\r |
| | 185 | UINT64 Uint64;\r |
| | 186 | } VTD_FIRST_LEVEL_PAGING_ENTRY;\r |
| | 187 | \r |
| | 188 | typedef union {\r |
| | 189 | struct {\r |
| | 190 | UINT32 Read:1;\r |
| | 191 | UINT32 Write:1;\r |
| | 192 | UINT32 Execute:1;\r |
| | 193 | UINT32 ExtendedMemoryType:3;\r |
| | 194 | UINT32 IgnorePAT:1;\r |
| | 195 | UINT32 PageSize:1;\r |
| | 196 | UINT32 Ignored_8:3;\r |
| | 197 | UINT32 Snoop:1;\r |
| | 198 | UINT32 AddressLo:20;\r |
| | 199 | UINT32 AddressHi:20;\r |
| | 200 | UINT32 Ignored_52:10;\r |
| | 201 | UINT32 TransientMapping:1;\r |
| | 202 | UINT32 Ignored_63:1;\r |
| | 203 | } Bits;\r |
| | 204 | UINT64 Uint64;\r |
| | 205 | } VTD_SECOND_LEVEL_PAGING_ENTRY;\r |
| | 206 | \r |
| | 207 | //\r |
| | 208 | // Register Descriptions\r |
| | 209 | //\r |
| | 210 | #define R_VER_REG 0x00\r |
| | 211 | #define R_CAP_REG 0x08\r |
| | 212 | #define B_CAP_REG_RWBF BIT4\r |
| | 213 | #define R_ECAP_REG 0x10\r |
| | 214 | #define R_GCMD_REG 0x18\r |
| | 215 | #define B_GMCD_REG_WBF BIT27\r |
| | 216 | #define B_GMCD_REG_SRTP BIT30\r |
| | 217 | #define B_GMCD_REG_TE BIT31\r |
| | 218 | #define R_GSTS_REG 0x1C\r |
| | 219 | #define B_GSTS_REG_WBF BIT27\r |
| | 220 | #define B_GSTS_REG_RTPS BIT30\r |
| | 221 | #define B_GSTS_REG_TE BIT31\r |
| | 222 | #define R_RTADDR_REG 0x20\r |
| | 223 | #define R_CCMD_REG 0x28\r |
| | 224 | #define B_CCMD_REG_CIRG_MASK (BIT62|BIT61)\r |
| | 225 | #define V_CCMD_REG_CIRG_GLOBAL BIT61\r |
| | 226 | #define V_CCMD_REG_CIRG_DOMAIN BIT62\r |
| | 227 | #define V_CCMD_REG_CIRG_DEVICE (BIT62|BIT61)\r |
| | 228 | #define B_CCMD_REG_ICC BIT63\r |
| | 229 | #define R_FSTS_REG 0x34\r |
| | 230 | #define R_FECTL_REG 0x38\r |
| | 231 | #define R_FEDATA_REG 0x3C\r |
| | 232 | #define R_FEADDR_REG 0x40\r |
| | 233 | #define R_FEUADDR_REG 0x44\r |
| | 234 | #define R_AFLOG_REG 0x58\r |
| | 235 | \r |
| | 236 | #define R_IVA_REG 0x00 // + IRO\r |
| | 237 | #define B_IVA_REG_AM_MASK (BIT0|BIT1|BIT2|BIT3|BIT4|BIT5)\r |
| | 238 | #define B_IVA_REG_AM_4K 0 // 1 page\r |
| | 239 | #define B_IVA_REG_AM_2M 9 // 2M page\r |
| | 240 | #define B_IVA_REG_IH BIT6\r |
| | 241 | #define R_IOTLB_REG 0x08 // + IRO\r |
| | 242 | #define B_IOTLB_REG_IIRG_MASK (BIT61|BIT60)\r |
| | 243 | #define V_IOTLB_REG_IIRG_GLOBAL BIT60\r |
| | 244 | #define V_IOTLB_REG_IIRG_DOMAIN BIT61\r |
| | 245 | #define V_IOTLB_REG_IIRG_PAGE (BIT61|BIT60)\r |
| | 246 | #define B_IOTLB_REG_IVT BIT63\r |
| | 247 | \r |
| | 248 | #define R_FRCD_REG 0x00 // + FRO\r |
| | 249 | \r |
| | 250 | typedef union {\r |
| | 251 | struct {\r |
| | 252 | UINT8 ND:3; // Number of domains supported\r |
| | 253 | UINT8 AFL:1; // Advanced Fault Logging\r |
| | 254 | UINT8 RWBF:1; // Required Write-Buffer Flushing\r |
| | 255 | UINT8 PLMR:1; // Protected Low-Memory Region\r |
| | 256 | UINT8 PHMR:1; // Protected High-Memory Region\r |
| | 257 | UINT8 CM:1; // Caching Mode\r |
| | 258 | \r |
| | 259 | UINT8 SAGAW:5; // Supported Adjusted Guest Address Widths\r |
| | 260 | UINT8 Rsvd_13:3;\r |
| | 261 | \r |
| | 262 | UINT8 MGAW:6; // Maximum Guest Address Width\r |
| | 263 | UINT8 ZLR:1; // Zero Length Read\r |
| | 264 | UINT8 Rsvd_23:1;\r |
| | 265 | \r |
| | 266 | UINT16 FRO:10; // Fault-recording Register offset\r |
| | 267 | UINT16 SLLPS:4; // Second Level Large Page Support\r |
| | 268 | UINT16 Rsvd_38:1;\r |
| | 269 | UINT16 PSI:1; // Page Selective Invalidation\r |
| | 270 | \r |
| | 271 | UINT8 NFR:8; // Number of Fault-recording Registers\r |
| | 272 | \r |
| | 273 | UINT8 MAMV:6; // Maximum Address Mask Value\r |
| | 274 | UINT8 DWD:1; // Write Draining\r |
| | 275 | UINT8 DRD:1; // Read Draining\r |
| | 276 | \r |
| | 277 | UINT8 FL1GP:1; // First Level 1-GByte Page Support\r |
| | 278 | UINT8 Rsvd_57:2;\r |
| | 279 | UINT8 PI:1; // Posted Interrupts Support\r |
| | 280 | UINT8 Rsvd_60:4;\r |
| | 281 | } Bits;\r |
| | 282 | UINT64 Uint64;\r |
| | 283 | } VTD_CAP_REG;\r |
| | 284 | \r |
| | 285 | typedef union {\r |
| | 286 | struct {\r |
| | 287 | UINT8 C:1; // Page-walk Coherency\r |
| | 288 | UINT8 QI:1; // Queued Invalidation support\r |
| | 289 | UINT8 DT:1; // Device-TLB support\r |
| | 290 | UINT8 IR:1; // Interrupt Remapping support\r |
| | 291 | UINT8 EIM:1; // Extended Interrupt Mode\r |
| | 292 | UINT8 Rsvd_5:1;\r |
| | 293 | UINT8 PT:1; // Pass Through\r |
| | 294 | UINT8 SC:1; // Snoop Control\r |
| | 295 | \r |
| | 296 | UINT16 IRO:10; // IOTLB Register Offset\r |
| | 297 | UINT16 Rsvd_18:2;\r |
| | 298 | UINT16 MHMV:4; // Maximum Handle Mask Value\r |
| | 299 | \r |
| | 300 | UINT8 ECS:1; // Extended Context Support\r |
| | 301 | UINT8 MTS:1; // Memory Type Support\r |
| | 302 | UINT8 NEST:1; // Nested Translation Support\r |
| | 303 | UINT8 DIS:1; // Deferred Invalidate Support\r |
| | 304 | UINT8 PASID:1; // Process Address Space ID Support\r |
| | 305 | UINT8 PRS:1; // Page Request Support\r |
| | 306 | UINT8 ERS:1; // Execute Request Support\r |
| | 307 | UINT8 SRS:1; // Supervisor Request Support\r |
| | 308 | \r |
| | 309 | UINT32 Rsvd_32:1;\r |
| | 310 | UINT32 NWFS:1; // No Write Flag Support\r |
| | 311 | UINT32 EAFS:1; // Extended Accessed Flag Support\r |
| | 312 | UINT32 PSS:5; // PASID Size Supported\r |
| | 313 | UINT32 Rsvd_40:24;\r |
| | 314 | } Bits;\r |
| | 315 | UINT64 Uint64;\r |
| | 316 | } VTD_ECAP_REG;\r |
| | 317 | \r |
| | 318 | typedef union {\r |
| | 319 | struct {\r |
| | 320 | UINT32 Rsvd_0:12;\r |
| | 321 | UINT32 FILo:20; // FaultInfo\r |
| | 322 | UINT32 FIHi:32; // FaultInfo\r |
| | 323 | \r |
| | 324 | UINT32 SID:16; // Source Identifier\r |
| | 325 | UINT32 Rsvd_80:13;\r |
| | 326 | UINT32 PRIV:1; // Privilege Mode Requested\r |
| | 327 | UINT32 EXE:1; // Execute Permission Requested\r |
| | 328 | UINT32 PP:1; // PASID Present\r |
| | 329 | \r |
| | 330 | UINT32 FR:8; // Fault Reason\r |
| | 331 | UINT32 PV:20; // PASID Value\r |
| | 332 | UINT32 AT:2; // Address Type\r |
| | 333 | UINT32 T:1; // Type (0: Write, 1: Read)\r |
| | 334 | UINT32 F:1; // Fault\r |
| | 335 | } Bits;\r |
| | 336 | UINT64 Uint64[2];\r |
| | 337 | } VTD_FRCD_REG;\r |
| | 338 | \r |
| | 339 | typedef union {\r |
| | 340 | struct {\r |
| | 341 | UINT8 Function:3;\r |
| | 342 | UINT8 Device:5;\r |
| | 343 | UINT8 Bus;\r |
| | 344 | } Bits;\r |
| | 345 | struct {\r |
| | 346 | UINT8 ContextIndex;\r |
| | 347 | UINT8 RootIndex;\r |
| | 348 | } Index;\r |
| | 349 | UINT16 Uint16;\r |
| | 350 | } VTD_SOURCE_ID;\r |
| | 351 | \r |
| | 352 | #pragma pack()\r |
| | 353 | \r |
| | 354 | #endif\r |
| | 355 | \r |
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