[mirror_edk2.git] / IntelSiliconPkg / Include / IndustryStandard / Vtd.h

/** @file\r
  The definition for VTD register.\r
  It is defined in "Intel VT for Direct IO Architecture Specification".\r
\r
  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php.\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef __VTD_REG_H__\r
#define __VTD_REG_H__\r
\r
#pragma pack(1)\r
\r
//\r
// Translation Structure Formats\r
//\r
#define VTD_ROOT_ENTRY_NUMBER       256\r
#define VTD_CONTEXT_ENTRY_NUMBER    256\r
\r
typedef union {\r
  struct {\r
    UINT64  Present:1;\r
    UINT64  Reserved_1:11;\r
    UINT64  ContextTablePointer:52;\r
\r
    UINT64  Reserved_64;\r
  } Bits;\r
  struct {\r
    UINT64  Uint64Lo;\r
    UINT64  Uint64Hi;\r
  } Uint128;\r
} VTD_ROOT_ENTRY;\r
\r
typedef union {\r
  struct {\r
    UINT64  LowerPresent:1;\r
    UINT64  Reserved_1:11;\r
    UINT64  LowerContextTablePointer:52;\r
\r
    UINT64  UpperPresent:1;\r
    UINT64  Reserved_65:11;\r
    UINT64  UpperContextTablePointer:52;\r
  } Bits;\r
  struct {\r
    UINT64  Uint64Lo;\r
    UINT64  Uint64Hi;\r
  } Uint128;\r
} VTD_EXT_ROOT_ENTRY;\r
\r
typedef union {\r
  struct {\r
    UINT64  Present:1;\r
    UINT64  FaultProcessingDisable:1;\r
    UINT64  TranslationType:2;\r
    UINT64  Reserved_4:8;\r
    UINT64  SecondLevelPageTranslationPointer:52;\r
\r
    UINT64  AddressWidth:3;\r
    UINT64  Ignored_67:4;\r
    UINT64  Reserved_71:1;\r
    UINT64  DomainIdentifier:16;\r
    UINT64  Reserved_88:40;\r
  } Bits;\r
  struct {\r
    UINT64  Uint64Lo;\r
    UINT64  Uint64Hi;\r
  } Uint128;\r
} VTD_CONTEXT_ENTRY;\r
\r
typedef union {\r
  struct {\r
    UINT64  Present:1;\r
    UINT64  FaultProcessingDisable:1;\r
    UINT64  TranslationType:3;\r
    UINT64  ExtendedMemoryType:3;\r
    UINT64  DeferredInvalidateEnable:1;\r
    UINT64  PageRequestEnable:1;\r
    UINT64  NestedTranslationEnable:1;\r
    UINT64  PASIDEnable:1;\r
    UINT64  SecondLevelPageTranslationPointer:52;\r
\r
    UINT64  AddressWidth:3;\r
    UINT64  PageGlobalEnable:1;\r
    UINT64  NoExecuteEnable:1;\r
    UINT64  WriteProtectEnable:1;\r
    UINT64  CacheDisable:1;\r
    UINT64  ExtendedMemoryTypeEnable:1;\r
    UINT64  DomainIdentifier:16;\r
    UINT64  SupervisorModeExecuteProtection:1;\r
    UINT64  ExtendedAccessedFlagEnable:1;\r
    UINT64  ExecuteRequestsEnable:1;\r
    UINT64  SecondLevelExecuteEnable:1;\r
    UINT64  Reserved_92:4;\r
    UINT64  PageAttributeTable0:3;\r
    UINT64  Reserved_Pat0:1;\r
    UINT64  PageAttributeTable1:3;\r
    UINT64  Reserved_Pat1:1;\r
    UINT64  PageAttributeTable2:3;\r
    UINT64  Reserved_Pat2:1;\r
    UINT64  PageAttributeTable3:3;\r
    UINT64  Reserved_Pat3:1;\r
    UINT64  PageAttributeTable4:3;\r
    UINT64  Reserved_Pat4:1;\r
    UINT64  PageAttributeTable5:3;\r
    UINT64  Reserved_Pat5:1;\r
    UINT64  PageAttributeTable6:3;\r
    UINT64  Reserved_Pat6:1;\r
    UINT64  PageAttributeTable7:3;\r
    UINT64  Reserved_Pat7:1;\r
\r
    UINT64  PASIDTableSize:4;\r
    UINT64  Reserved_132:8;\r
    UINT64  PASIDTablePointer:52;\r
\r
    UINT64  Reserved_192:12;\r
    UINT64  PASIDStateTablePointer:52;\r
  } Bits;\r
  struct {\r
    UINT64  Uint64_1;\r
    UINT64  Uint64_2;\r
    UINT64  Uint64_3;\r
    UINT64  Uint64_4;\r
  } Uint256;\r
} VTD_EXT_CONTEXT_ENTRY;\r
\r
typedef union {\r
  struct {\r
    UINT64  Present:1;\r
    UINT64  Reserved_1:2;\r
    UINT64  PageLevelCacheDisable:1;\r
    UINT64  PageLevelWriteThrough:1;\r
    UINT64  Reserved_5:6;\r
    UINT64  SupervisorRequestsEnable:1;\r
    UINT64  FirstLevelPageTranslationPointer:52;\r
  } Bits;\r
  UINT64    Uint64;\r
} VTD_PASID_ENTRY;\r
\r
typedef union {\r
  struct {\r
    UINT64  Reserved_0:32;\r
    UINT64  ActiveReferenceCount:16;\r
    UINT64  Reserved_48:15;\r
    UINT64  DeferredInvalidate:1;\r
  } Bits;\r
  UINT64    Uint64;\r
} VTD_PASID_STATE_ENTRY;\r
\r
typedef union {\r
  struct {\r
    UINT64  Present:1;\r
    UINT64  ReadWrite:1;\r
    UINT64  UserSupervisor:1;\r
    UINT64  PageLevelWriteThrough:1;\r
    UINT64  PageLevelCacheDisable:1;\r
    UINT64  Accessed:1;\r
    UINT64  Dirty:1;\r
    UINT64  PageSize:1; // It is PageAttribute:1 for 4K page entry\r
    UINT64  Global:1;\r
    UINT64  Ignored_9:1;\r
    UINT64  ExtendedAccessed:1;\r
    UINT64  Ignored_11:1;\r
    // NOTE: There is PageAttribute:1 as bit12 for 1G page entry and 2M page entry\r
    UINT64  Address:40;\r
    UINT64  Ignored_52:11;\r
    UINT64  ExecuteDisable:1;\r
  } Bits;\r
  UINT64    Uint64;\r
} VTD_FIRST_LEVEL_PAGING_ENTRY;\r
\r
typedef union {\r
  struct {\r
    UINT64  Read:1;\r
    UINT64  Write:1;\r
    UINT64  Execute:1;\r
    UINT64  ExtendedMemoryType:3;\r
    UINT64  IgnorePAT:1;\r
    UINT64  PageSize:1;\r
    UINT64  Ignored_8:3;\r
    UINT64  Snoop:1;\r
    UINT64  Address:40;\r
    UINT64  Ignored_52:10;\r
    UINT64  TransientMapping:1;\r
    UINT64  Ignored_63:1;\r
  } Bits;\r
  UINT64    Uint64;\r
} VTD_SECOND_LEVEL_PAGING_ENTRY;\r
\r
//\r
// Register Descriptions\r
//\r
#define R_VER_REG        0x00\r
#define R_CAP_REG        0x08\r
#define   B_CAP_REG_RWBF       BIT4\r
#define R_ECAP_REG       0x10\r
#define R_GCMD_REG       0x18\r
#define   B_GMCD_REG_WBF       BIT27\r
#define   B_GMCD_REG_SRTP      BIT30\r
#define   B_GMCD_REG_TE        BIT31\r
#define R_GSTS_REG       0x1C\r
#define   B_GSTS_REG_WBF       BIT27\r
#define   B_GSTS_REG_RTPS      BIT30\r
#define   B_GSTS_REG_TE        BIT31\r
#define R_RTADDR_REG     0x20\r
#define R_CCMD_REG       0x28\r
#define   B_CCMD_REG_CIRG_MASK    (BIT62|BIT61)\r
#define   V_CCMD_REG_CIRG_GLOBAL  BIT61\r
#define   V_CCMD_REG_CIRG_DOMAIN  BIT62\r
#define   V_CCMD_REG_CIRG_DEVICE  (BIT62|BIT61)\r
#define   B_CCMD_REG_ICC          BIT63\r
#define R_FSTS_REG       0x34\r
#define R_FECTL_REG      0x38\r
#define R_FEDATA_REG     0x3C\r
#define R_FEADDR_REG     0x40\r
#define R_FEUADDR_REG    0x44\r
#define R_AFLOG_REG      0x58\r
\r
#define R_IVA_REG        0x00 // + IRO\r
#define   B_IVA_REG_AM_MASK       (BIT0|BIT1|BIT2|BIT3|BIT4|BIT5)\r
#define   B_IVA_REG_AM_4K         0 // 1 page\r
#define   B_IVA_REG_AM_2M         9 // 2M page\r
#define   B_IVA_REG_IH            BIT6\r
#define R_IOTLB_REG      0x08 // + IRO\r
#define   B_IOTLB_REG_IIRG_MASK   (BIT61|BIT60)\r
#define   V_IOTLB_REG_IIRG_GLOBAL BIT60\r
#define   V_IOTLB_REG_IIRG_DOMAIN BIT61\r
#define   V_IOTLB_REG_IIRG_PAGE   (BIT61|BIT60)\r
#define   B_IOTLB_REG_IVT         BIT63\r
\r
#define R_FRCD_REG       0x00 // + FRO\r
\r
typedef union {\r
  struct {\r
    UINT8         ND:3; // Number of domains supported\r
    UINT8         AFL:1; // Advanced Fault Logging\r
    UINT8         RWBF:1; // Required Write-Buffer Flushing\r
    UINT8         PLMR:1; // Protected Low-Memory Region\r
    UINT8         PHMR:1; // Protected High-Memory Region\r
    UINT8         CM:1; // Caching Mode\r
\r
    UINT8         SAGAW:5; // Supported Adjusted Guest Address Widths\r
    UINT8         Rsvd_13:3;\r
\r
    UINT8         MGAW:6; // Maximum Guest Address Width\r
    UINT8         ZLR:1; // Zero Length Read\r
    UINT8         Rsvd_23:1;\r
\r
    UINT16        FRO:10; // Fault-recording Register offset\r
    UINT16        SLLPS:4; // Second Level Large Page Support\r
    UINT16        Rsvd_38:1;\r
    UINT16        PSI:1; // Page Selective Invalidation\r
\r
    UINT8         NFR:8; // Number of Fault-recording Registers\r
\r
    UINT8         MAMV:6; // Maximum Address Mask Value\r
    UINT8         DWD:1; // Write Draining\r
    UINT8         DRD:1; // Read Draining\r
\r
    UINT8         FL1GP:1; // First Level 1-GByte Page Support\r
    UINT8         Rsvd_57:2;\r
    UINT8         PI:1; // Posted Interrupts Support\r
    UINT8         Rsvd_60:4;\r
  } Bits;\r
  UINT64     Uint64;\r
} VTD_CAP_REG;\r
\r
typedef union {\r
  struct {\r
    UINT8         C:1; // Page-walk Coherency\r
    UINT8         QI:1; // Queued Invalidation support\r
    UINT8         DT:1; // Device-TLB support\r
    UINT8         IR:1; // Interrupt Remapping support\r
    UINT8         EIM:1; // Extended Interrupt Mode\r
    UINT8         Rsvd_5:1;\r
    UINT8         PT:1; // Pass Through\r
    UINT8         SC:1; // Snoop Control\r
\r
    UINT16        IRO:10; // IOTLB Register Offset\r
    UINT16        Rsvd_18:2;\r
    UINT16        MHMV:4; // Maximum Handle Mask Value\r
\r
    UINT8         ECS:1; // Extended Context Support\r
    UINT8         MTS:1; // Memory Type Support\r
    UINT8         NEST:1; // Nested Translation Support\r
    UINT8         DIS:1; // Deferred Invalidate Support\r
    UINT8         PASID:1; // Process Address Space ID Support\r
    UINT8         PRS:1; // Page Request Support\r
    UINT8         ERS:1; // Execute Request Support\r
    UINT8         SRS:1; // Supervisor Request Support\r
\r
    UINT32        Rsvd_32:1;\r
    UINT32        NWFS:1; // No Write Flag Support\r
    UINT32        EAFS:1; // Extended Accessed Flag Support\r
    UINT32        PSS:5; // PASID Size Supported\r
\r
    UINT32        Rsvd_40:24;\r
  } Bits;\r
  UINT64     Uint64;\r
} VTD_ECAP_REG;\r
\r
typedef union {\r
  struct {\r
    UINT64   Rsvd_0:12;\r
    UINT64   FI:52;        // FaultInfo\r
\r
    UINT32   SID:16;       // Source Identifier\r
    UINT32   Rsvd_80:13;\r
    UINT32   PRIV:1;       // Privilege Mode Requested\r
    UINT32   EXE:1;        // Execute Permission Requested\r
    UINT32   PP:1;         // PASID Present\r
\r
    UINT32   FR:8;         // Fault Reason\r
    UINT32   PV:20;        // PASID Value\r
    UINT32   AT:2;         // Address Type\r
    UINT32   T:1;          // Type (0: Write, 1: Read)\r
    UINT32   F:1;          // Fault\r
  } Bits;\r
  UINT64     Uint64[2];\r
} VTD_FRCD_REG;\r
\r
typedef union {\r
  struct {\r
    UINT8    Function:3;\r
    UINT8    Device:5;\r
    UINT8    Bus;\r
  } Bits;\r
  struct {\r
    UINT8    ContextIndex;\r
    UINT8    RootIndex;\r
  } Index;\r
  UINT16     Uint16;\r
} VTD_SOURCE_ID;\r
\r
#pragma pack()\r
\r
#endif\r
\r
Commit	Line	Data
	1	/** @file\r
	2	The definition for VTD register.\r
	3	It is defined in "Intel VT for Direct IO Architecture Specification".\r
	4	\r
	5	Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
	6	This program and the accompanying materials\r
	7	are licensed and made available under the terms and conditions of the BSD License\r
	8	which accompanies this distribution. The full text of the license may be found at\r
	9	http://opensource.org/licenses/bsd-license.php.\r
	10	\r
	11	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	\r
	14	**/\r
	15	\r
	16	#ifndef __VTD_REG_H__\r
	17	#define __VTD_REG_H__\r
	18	\r
	19	#pragma pack(1)\r
	20	\r
	21	//\r
	22	// Translation Structure Formats\r
	23	//\r
	24	#define VTD_ROOT_ENTRY_NUMBER 256\r
	25	#define VTD_CONTEXT_ENTRY_NUMBER 256\r
	26	\r
	27	typedef union {\r
	28	struct {\r
	29	UINT64 Present:1;\r
	30	UINT64 Reserved_1:11;\r
	31	UINT64 ContextTablePointer:52;\r
	32	\r
	33	UINT64 Reserved_64;\r
	34	} Bits;\r
	35	struct {\r
	36	UINT64 Uint64Lo;\r
	37	UINT64 Uint64Hi;\r
	38	} Uint128;\r
	39	} VTD_ROOT_ENTRY;\r
	40	\r
	41	typedef union {\r
	42	struct {\r
	43	UINT64 LowerPresent:1;\r
	44	UINT64 Reserved_1:11;\r
	45	UINT64 LowerContextTablePointer:52;\r
	46	\r
	47	UINT64 UpperPresent:1;\r
	48	UINT64 Reserved_65:11;\r
	49	UINT64 UpperContextTablePointer:52;\r
	50	} Bits;\r
	51	struct {\r
	52	UINT64 Uint64Lo;\r
	53	UINT64 Uint64Hi;\r
	54	} Uint128;\r
	55	} VTD_EXT_ROOT_ENTRY;\r
	56	\r
	57	typedef union {\r
	58	struct {\r
	59	UINT64 Present:1;\r
	60	UINT64 FaultProcessingDisable:1;\r
	61	UINT64 TranslationType:2;\r
	62	UINT64 Reserved_4:8;\r
	63	UINT64 SecondLevelPageTranslationPointer:52;\r
	64	\r
	65	UINT64 AddressWidth:3;\r
	66	UINT64 Ignored_67:4;\r
	67	UINT64 Reserved_71:1;\r
	68	UINT64 DomainIdentifier:16;\r
	69	UINT64 Reserved_88:40;\r
	70	} Bits;\r
	71	struct {\r
	72	UINT64 Uint64Lo;\r
	73	UINT64 Uint64Hi;\r
	74	} Uint128;\r
	75	} VTD_CONTEXT_ENTRY;\r
	76	\r
	77	typedef union {\r
	78	struct {\r
	79	UINT64 Present:1;\r
	80	UINT64 FaultProcessingDisable:1;\r
	81	UINT64 TranslationType:3;\r
	82	UINT64 ExtendedMemoryType:3;\r
	83	UINT64 DeferredInvalidateEnable:1;\r
	84	UINT64 PageRequestEnable:1;\r
	85	UINT64 NestedTranslationEnable:1;\r
	86	UINT64 PASIDEnable:1;\r
	87	UINT64 SecondLevelPageTranslationPointer:52;\r
	88	\r
	89	UINT64 AddressWidth:3;\r
	90	UINT64 PageGlobalEnable:1;\r
	91	UINT64 NoExecuteEnable:1;\r
	92	UINT64 WriteProtectEnable:1;\r
	93	UINT64 CacheDisable:1;\r
	94	UINT64 ExtendedMemoryTypeEnable:1;\r
	95	UINT64 DomainIdentifier:16;\r
	96	UINT64 SupervisorModeExecuteProtection:1;\r
	97	UINT64 ExtendedAccessedFlagEnable:1;\r
	98	UINT64 ExecuteRequestsEnable:1;\r
	99	UINT64 SecondLevelExecuteEnable:1;\r
	100	UINT64 Reserved_92:4;\r
	101	UINT64 PageAttributeTable0:3;\r
	102	UINT64 Reserved_Pat0:1;\r
	103	UINT64 PageAttributeTable1:3;\r
	104	UINT64 Reserved_Pat1:1;\r
	105	UINT64 PageAttributeTable2:3;\r
	106	UINT64 Reserved_Pat2:1;\r
	107	UINT64 PageAttributeTable3:3;\r
	108	UINT64 Reserved_Pat3:1;\r
	109	UINT64 PageAttributeTable4:3;\r
	110	UINT64 Reserved_Pat4:1;\r
	111	UINT64 PageAttributeTable5:3;\r
	112	UINT64 Reserved_Pat5:1;\r
	113	UINT64 PageAttributeTable6:3;\r
	114	UINT64 Reserved_Pat6:1;\r
	115	UINT64 PageAttributeTable7:3;\r
	116	UINT64 Reserved_Pat7:1;\r
	117	\r
	118	UINT64 PASIDTableSize:4;\r
	119	UINT64 Reserved_132:8;\r
	120	UINT64 PASIDTablePointer:52;\r
	121	\r
	122	UINT64 Reserved_192:12;\r
	123	UINT64 PASIDStateTablePointer:52;\r
	124	} Bits;\r
	125	struct {\r
	126	UINT64 Uint64_1;\r
	127	UINT64 Uint64_2;\r
	128	UINT64 Uint64_3;\r
	129	UINT64 Uint64_4;\r
	130	} Uint256;\r
	131	} VTD_EXT_CONTEXT_ENTRY;\r
	132	\r
	133	typedef union {\r
	134	struct {\r
	135	UINT64 Present:1;\r
	136	UINT64 Reserved_1:2;\r
	137	UINT64 PageLevelCacheDisable:1;\r
	138	UINT64 PageLevelWriteThrough:1;\r
	139	UINT64 Reserved_5:6;\r
	140	UINT64 SupervisorRequestsEnable:1;\r
	141	UINT64 FirstLevelPageTranslationPointer:52;\r
	142	} Bits;\r
	143	UINT64 Uint64;\r
	144	} VTD_PASID_ENTRY;\r
	145	\r
	146	typedef union {\r
	147	struct {\r
	148	UINT64 Reserved_0:32;\r
	149	UINT64 ActiveReferenceCount:16;\r
	150	UINT64 Reserved_48:15;\r
	151	UINT64 DeferredInvalidate:1;\r
	152	} Bits;\r
	153	UINT64 Uint64;\r
	154	} VTD_PASID_STATE_ENTRY;\r
	155	\r
	156	typedef union {\r
	157	struct {\r
	158	UINT64 Present:1;\r
	159	UINT64 ReadWrite:1;\r
	160	UINT64 UserSupervisor:1;\r
	161	UINT64 PageLevelWriteThrough:1;\r
	162	UINT64 PageLevelCacheDisable:1;\r
	163	UINT64 Accessed:1;\r
	164	UINT64 Dirty:1;\r
	165	UINT64 PageSize:1; // It is PageAttribute:1 for 4K page entry\r
	166	UINT64 Global:1;\r
	167	UINT64 Ignored_9:1;\r
	168	UINT64 ExtendedAccessed:1;\r
	169	UINT64 Ignored_11:1;\r
	170	// NOTE: There is PageAttribute:1 as bit12 for 1G page entry and 2M page entry\r
	171	UINT64 Address:40;\r
	172	UINT64 Ignored_52:11;\r
	173	UINT64 ExecuteDisable:1;\r
	174	} Bits;\r
	175	UINT64 Uint64;\r
	176	} VTD_FIRST_LEVEL_PAGING_ENTRY;\r
	177	\r
	178	typedef union {\r
	179	struct {\r
	180	UINT64 Read:1;\r
	181	UINT64 Write:1;\r
	182	UINT64 Execute:1;\r
	183	UINT64 ExtendedMemoryType:3;\r
	184	UINT64 IgnorePAT:1;\r
	185	UINT64 PageSize:1;\r
	186	UINT64 Ignored_8:3;\r
	187	UINT64 Snoop:1;\r
	188	UINT64 Address:40;\r
	189	UINT64 Ignored_52:10;\r
	190	UINT64 TransientMapping:1;\r
	191	UINT64 Ignored_63:1;\r
	192	} Bits;\r
	193	UINT64 Uint64;\r
	194	} VTD_SECOND_LEVEL_PAGING_ENTRY;\r
	195	\r
	196	//\r
	197	// Register Descriptions\r
	198	//\r
	199	#define R_VER_REG 0x00\r
	200	#define R_CAP_REG 0x08\r
	201	#define B_CAP_REG_RWBF BIT4\r
	202	#define R_ECAP_REG 0x10\r
	203	#define R_GCMD_REG 0x18\r
	204	#define B_GMCD_REG_WBF BIT27\r
	205	#define B_GMCD_REG_SRTP BIT30\r
	206	#define B_GMCD_REG_TE BIT31\r
	207	#define R_GSTS_REG 0x1C\r
	208	#define B_GSTS_REG_WBF BIT27\r
	209	#define B_GSTS_REG_RTPS BIT30\r
	210	#define B_GSTS_REG_TE BIT31\r
	211	#define R_RTADDR_REG 0x20\r
	212	#define R_CCMD_REG 0x28\r
	213	#define B_CCMD_REG_CIRG_MASK (BIT62\|BIT61)\r
	214	#define V_CCMD_REG_CIRG_GLOBAL BIT61\r
	215	#define V_CCMD_REG_CIRG_DOMAIN BIT62\r
	216	#define V_CCMD_REG_CIRG_DEVICE (BIT62\|BIT61)\r
	217	#define B_CCMD_REG_ICC BIT63\r
	218	#define R_FSTS_REG 0x34\r
	219	#define R_FECTL_REG 0x38\r
	220	#define R_FEDATA_REG 0x3C\r
	221	#define R_FEADDR_REG 0x40\r
	222	#define R_FEUADDR_REG 0x44\r
	223	#define R_AFLOG_REG 0x58\r
	224	\r
	225	#define R_IVA_REG 0x00 // + IRO\r
	226	#define B_IVA_REG_AM_MASK (BIT0\|BIT1\|BIT2\|BIT3\|BIT4\|BIT5)\r
	227	#define B_IVA_REG_AM_4K 0 // 1 page\r
	228	#define B_IVA_REG_AM_2M 9 // 2M page\r
	229	#define B_IVA_REG_IH BIT6\r
	230	#define R_IOTLB_REG 0x08 // + IRO\r
	231	#define B_IOTLB_REG_IIRG_MASK (BIT61\|BIT60)\r
	232	#define V_IOTLB_REG_IIRG_GLOBAL BIT60\r
	233	#define V_IOTLB_REG_IIRG_DOMAIN BIT61\r
	234	#define V_IOTLB_REG_IIRG_PAGE (BIT61\|BIT60)\r
	235	#define B_IOTLB_REG_IVT BIT63\r
	236	\r
	237	#define R_FRCD_REG 0x00 // + FRO\r
	238	\r
	239	typedef union {\r
	240	struct {\r
	241	UINT8 ND:3; // Number of domains supported\r
	242	UINT8 AFL:1; // Advanced Fault Logging\r
	243	UINT8 RWBF:1; // Required Write-Buffer Flushing\r
	244	UINT8 PLMR:1; // Protected Low-Memory Region\r
	245	UINT8 PHMR:1; // Protected High-Memory Region\r
	246	UINT8 CM:1; // Caching Mode\r
	247	\r
	248	UINT8 SAGAW:5; // Supported Adjusted Guest Address Widths\r
	249	UINT8 Rsvd_13:3;\r
	250	\r
	251	UINT8 MGAW:6; // Maximum Guest Address Width\r
	252	UINT8 ZLR:1; // Zero Length Read\r
	253	UINT8 Rsvd_23:1;\r
	254	\r
	255	UINT16 FRO:10; // Fault-recording Register offset\r
	256	UINT16 SLLPS:4; // Second Level Large Page Support\r
	257	UINT16 Rsvd_38:1;\r
	258	UINT16 PSI:1; // Page Selective Invalidation\r
	259	\r
	260	UINT8 NFR:8; // Number of Fault-recording Registers\r
	261	\r
	262	UINT8 MAMV:6; // Maximum Address Mask Value\r
	263	UINT8 DWD:1; // Write Draining\r
	264	UINT8 DRD:1; // Read Draining\r
	265	\r
	266	UINT8 FL1GP:1; // First Level 1-GByte Page Support\r
	267	UINT8 Rsvd_57:2;\r
	268	UINT8 PI:1; // Posted Interrupts Support\r
	269	UINT8 Rsvd_60:4;\r
	270	} Bits;\r
	271	UINT64 Uint64;\r
	272	} VTD_CAP_REG;\r
	273	\r
	274	typedef union {\r
	275	struct {\r
	276	UINT8 C:1; // Page-walk Coherency\r
	277	UINT8 QI:1; // Queued Invalidation support\r
	278	UINT8 DT:1; // Device-TLB support\r
	279	UINT8 IR:1; // Interrupt Remapping support\r
	280	UINT8 EIM:1; // Extended Interrupt Mode\r
	281	UINT8 Rsvd_5:1;\r
	282	UINT8 PT:1; // Pass Through\r
	283	UINT8 SC:1; // Snoop Control\r
	284	\r
	285	UINT16 IRO:10; // IOTLB Register Offset\r
	286	UINT16 Rsvd_18:2;\r
	287	UINT16 MHMV:4; // Maximum Handle Mask Value\r
	288	\r
	289	UINT8 ECS:1; // Extended Context Support\r
	290	UINT8 MTS:1; // Memory Type Support\r
	291	UINT8 NEST:1; // Nested Translation Support\r
	292	UINT8 DIS:1; // Deferred Invalidate Support\r
	293	UINT8 PASID:1; // Process Address Space ID Support\r
	294	UINT8 PRS:1; // Page Request Support\r
	295	UINT8 ERS:1; // Execute Request Support\r
	296	UINT8 SRS:1; // Supervisor Request Support\r
	297	\r
	298	UINT32 Rsvd_32:1;\r
	299	UINT32 NWFS:1; // No Write Flag Support\r
	300	UINT32 EAFS:1; // Extended Accessed Flag Support\r
	301	UINT32 PSS:5; // PASID Size Supported\r
	302	\r
	303	UINT32 Rsvd_40:24;\r
	304	} Bits;\r
	305	UINT64 Uint64;\r
	306	} VTD_ECAP_REG;\r
	307	\r
	308	typedef union {\r
	309	struct {\r
	310	UINT64 Rsvd_0:12;\r
	311	UINT64 FI:52; // FaultInfo\r
	312	\r
	313	UINT32 SID:16; // Source Identifier\r
	314	UINT32 Rsvd_80:13;\r
	315	UINT32 PRIV:1; // Privilege Mode Requested\r
	316	UINT32 EXE:1; // Execute Permission Requested\r
	317	UINT32 PP:1; // PASID Present\r
	318	\r
	319	UINT32 FR:8; // Fault Reason\r
	320	UINT32 PV:20; // PASID Value\r
	321	UINT32 AT:2; // Address Type\r
	322	UINT32 T:1; // Type (0: Write, 1: Read)\r
	323	UINT32 F:1; // Fault\r
	324	} Bits;\r
	325	UINT64 Uint64[2];\r
	326	} VTD_FRCD_REG;\r
	327	\r
	328	typedef union {\r
	329	struct {\r
	330	UINT8 Function:3;\r
	331	UINT8 Device:5;\r
	332	UINT8 Bus;\r
	333	} Bits;\r
	334	struct {\r
	335	UINT8 ContextIndex;\r
	336	UINT8 RootIndex;\r
	337	} Index;\r
	338	UINT16 Uint16;\r
	339	} VTD_SOURCE_ID;\r
	340	\r
	341	#pragma pack()\r
	342	\r
	343	#endif\r
	344	\r