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MdeModulePkg/AtaAtapiPassThru: Ensure GHC.AE bit is always set in Ahci
[mirror_edk2.git] / MdeModulePkg / Bus / Ata / AtaAtapiPassThru / AhciMode.c
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1/** @file\r
2 The file for AHCI mode of ATA host controller.\r
3\r
4 Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>\r
5 (C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>\r
6 This program and the accompanying materials\r
7 are licensed and made available under the terms and conditions of the BSD License\r
8 which accompanies this distribution. The full text of the license may be found at\r
9 http://opensource.org/licenses/bsd-license.php\r
10\r
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15\r
16#include "AtaAtapiPassThru.h"\r
17\r
18/**\r
19 Read AHCI Operation register.\r
20\r
21 @param PciIo The PCI IO protocol instance.\r
22 @param Offset The operation register offset.\r
23\r
24 @return The register content read.\r
25\r
26**/\r
27UINT32\r
28EFIAPI\r
29AhciReadReg (\r
30 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
31 IN UINT32 Offset\r
32 )\r
33{\r
34 UINT32 Data;\r
35\r
36 ASSERT (PciIo != NULL);\r
37\r
38 Data = 0;\r
39\r
40 PciIo->Mem.Read (\r
41 PciIo,\r
42 EfiPciIoWidthUint32,\r
43 EFI_AHCI_BAR_INDEX,\r
44 (UINT64) Offset,\r
45 1,\r
46 &Data\r
47 );\r
48\r
49 return Data;\r
50}\r
51\r
52/**\r
53 Write AHCI Operation register.\r
54\r
55 @param PciIo The PCI IO protocol instance.\r
56 @param Offset The operation register offset.\r
57 @param Data The data used to write down.\r
58\r
59**/\r
60VOID\r
61EFIAPI\r
62AhciWriteReg (\r
63 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
64 IN UINT32 Offset,\r
65 IN UINT32 Data\r
66 )\r
67{\r
68 ASSERT (PciIo != NULL);\r
69\r
70 PciIo->Mem.Write (\r
71 PciIo,\r
72 EfiPciIoWidthUint32,\r
73 EFI_AHCI_BAR_INDEX,\r
74 (UINT64) Offset,\r
75 1,\r
76 &Data\r
77 );\r
78\r
79 return ;\r
80}\r
81\r
82/**\r
83 Do AND operation with the value of AHCI Operation register.\r
84\r
85 @param PciIo The PCI IO protocol instance.\r
86 @param Offset The operation register offset.\r
87 @param AndData The data used to do AND operation.\r
88\r
89**/\r
90VOID\r
91EFIAPI\r
92AhciAndReg (\r
93 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
94 IN UINT32 Offset,\r
95 IN UINT32 AndData\r
96 )\r
97{\r
98 UINT32 Data;\r
99\r
100 ASSERT (PciIo != NULL);\r
101\r
102 Data = AhciReadReg (PciIo, Offset);\r
103\r
104 Data &= AndData;\r
105\r
106 AhciWriteReg (PciIo, Offset, Data);\r
107}\r
108\r
109/**\r
110 Do OR operation with the value of AHCI Operation register.\r
111\r
112 @param PciIo The PCI IO protocol instance.\r
113 @param Offset The operation register offset.\r
114 @param OrData The data used to do OR operation.\r
115\r
116**/\r
117VOID\r
118EFIAPI\r
119AhciOrReg (\r
120 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
121 IN UINT32 Offset,\r
122 IN UINT32 OrData\r
123 )\r
124{\r
125 UINT32 Data;\r
126\r
127 ASSERT (PciIo != NULL);\r
128\r
129 Data = AhciReadReg (PciIo, Offset);\r
130\r
131 Data |= OrData;\r
132\r
133 AhciWriteReg (PciIo, Offset, Data);\r
134}\r
135\r
136/**\r
137 Wait for the value of the specified MMIO register set to the test value.\r
138\r
139 @param PciIo The PCI IO protocol instance.\r
140 @param Offset The MMIO address to test.\r
141 @param MaskValue The mask value of memory.\r
142 @param TestValue The test value of memory.\r
143 @param Timeout The time out value for wait memory set, uses 100ns as a unit.\r
144\r
145 @retval EFI_TIMEOUT The MMIO setting is time out.\r
146 @retval EFI_SUCCESS The MMIO is correct set.\r
147\r
148**/\r
149EFI_STATUS\r
150EFIAPI\r
151AhciWaitMmioSet (\r
152 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
153 IN UINTN Offset,\r
154 IN UINT32 MaskValue,\r
155 IN UINT32 TestValue,\r
156 IN UINT64 Timeout\r
157 )\r
158{\r
159 UINT32 Value;\r
160 UINT64 Delay;\r
161 BOOLEAN InfiniteWait;\r
162\r
163 if (Timeout == 0) {\r
164 InfiniteWait = TRUE;\r
165 } else {\r
166 InfiniteWait = FALSE;\r
167 }\r
168\r
169 Delay = DivU64x32 (Timeout, 1000) + 1;\r
170\r
171 do {\r
172 //\r
173 // Access PCI MMIO space to see if the value is the tested one.\r
174 //\r
175 Value = AhciReadReg (PciIo, (UINT32) Offset) & MaskValue;\r
176\r
177 if (Value == TestValue) {\r
178 return EFI_SUCCESS;\r
179 }\r
180\r
181 //\r
182 // Stall for 100 microseconds.\r
183 //\r
184 MicroSecondDelay (100);\r
185\r
186 Delay--;\r
187\r
188 } while (InfiniteWait || (Delay > 0));\r
189\r
190 return EFI_TIMEOUT;\r
191}\r
192\r
193/**\r
194 Wait for the value of the specified system memory set to the test value.\r
195\r
196 @param Address The system memory address to test.\r
197 @param MaskValue The mask value of memory.\r
198 @param TestValue The test value of memory.\r
199 @param Timeout The time out value for wait memory set, uses 100ns as a unit.\r
200\r
201 @retval EFI_TIMEOUT The system memory setting is time out.\r
202 @retval EFI_SUCCESS The system memory is correct set.\r
203\r
204**/\r
205EFI_STATUS\r
206EFIAPI\r
207AhciWaitMemSet (\r
208 IN EFI_PHYSICAL_ADDRESS Address,\r
209 IN UINT32 MaskValue,\r
210 IN UINT32 TestValue,\r
211 IN UINT64 Timeout\r
212 )\r
213{\r
214 UINT32 Value;\r
215 UINT64 Delay;\r
216 BOOLEAN InfiniteWait;\r
217\r
218 if (Timeout == 0) {\r
219 InfiniteWait = TRUE;\r
220 } else {\r
221 InfiniteWait = FALSE;\r
222 }\r
223\r
224 Delay = DivU64x32 (Timeout, 1000) + 1;\r
225\r
226 do {\r
227 //\r
228 // Access sytem memory to see if the value is the tested one.\r
229 //\r
230 // The system memory pointed by Address will be updated by the\r
231 // SATA Host Controller, "volatile" is introduced to prevent\r
232 // compiler from optimizing the access to the memory address\r
233 // to only read once.\r
234 //\r
235 Value = *(volatile UINT32 *) (UINTN) Address;\r
236 Value &= MaskValue;\r
237\r
238 if (Value == TestValue) {\r
239 return EFI_SUCCESS;\r
240 }\r
241\r
242 //\r
243 // Stall for 100 microseconds.\r
244 //\r
245 MicroSecondDelay (100);\r
246\r
247 Delay--;\r
248\r
249 } while (InfiniteWait || (Delay > 0));\r
250\r
251 return EFI_TIMEOUT;\r
252}\r
253\r
254/**\r
255 Check the memory status to the test value.\r
256\r
257 @param[in] Address The memory address to test.\r
258 @param[in] MaskValue The mask value of memory.\r
259 @param[in] TestValue The test value of memory.\r
260 @param[in, out] Task Optional. Pointer to the ATA_NONBLOCK_TASK used by\r
261 non-blocking mode. If NULL, then just try once.\r
262\r
263 @retval EFI_NOTREADY The memory is not set.\r
264 @retval EFI_TIMEOUT The memory setting retry times out.\r
265 @retval EFI_SUCCESS The memory is correct set.\r
266\r
267**/\r
268EFI_STATUS\r
269EFIAPI\r
270AhciCheckMemSet (\r
271 IN UINTN Address,\r
272 IN UINT32 MaskValue,\r
273 IN UINT32 TestValue,\r
274 IN OUT ATA_NONBLOCK_TASK *Task\r
275 )\r
276{\r
277 UINT32 Value;\r
278\r
279 if (Task != NULL) {\r
280 Task->RetryTimes--;\r
281 }\r
282\r
283 Value = *(volatile UINT32 *) Address;\r
284 Value &= MaskValue;\r
285\r
286 if (Value == TestValue) {\r
287 return EFI_SUCCESS;\r
288 }\r
289\r
290 if ((Task != NULL) && !Task->InfiniteWait && (Task->RetryTimes == 0)) {\r
291 return EFI_TIMEOUT;\r
292 } else {\r
293 return EFI_NOT_READY;\r
294 }\r
295}\r
296\r
297/**\r
298 Check if the device is still on port. It also checks if the AHCI controller\r
299 supports the address and data count will be transferred.\r
300\r
301 @param PciIo The PCI IO protocol instance.\r
302 @param Port The number of port.\r
303\r
304 @retval EFI_SUCCESS The device is attached to port and the transfer data is\r
305 supported by AHCI controller.\r
306 @retval EFI_UNSUPPORTED The transfer address and count is not supported by AHCI\r
307 controller.\r
308 @retval EFI_NOT_READY The physical communication between AHCI controller and device\r
309 is not ready.\r
310\r
311**/\r
312EFI_STATUS\r
313EFIAPI\r
314AhciCheckDeviceStatus (\r
315 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
316 IN UINT8 Port\r
317 )\r
318{\r
319 UINT32 Data;\r
320 UINT32 Offset;\r
321\r
322 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SSTS;\r
323\r
324 Data = AhciReadReg (PciIo, Offset) & EFI_AHCI_PORT_SSTS_DET_MASK;\r
325\r
326 if (Data == EFI_AHCI_PORT_SSTS_DET_PCE) {\r
327 return EFI_SUCCESS;\r
328 }\r
329\r
330 return EFI_NOT_READY;\r
331}\r
332\r
333/**\r
334\r
335 Clear the port interrupt and error status. It will also clear\r
336 HBA interrupt status.\r
337\r
338 @param PciIo The PCI IO protocol instance.\r
339 @param Port The number of port.\r
340\r
341**/\r
342VOID\r
343EFIAPI\r
344AhciClearPortStatus (\r
345 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
346 IN UINT8 Port\r
347 )\r
348{\r
349 UINT32 Offset;\r
350\r
351 //\r
352 // Clear any error status\r
353 //\r
354 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SERR;\r
355 AhciWriteReg (PciIo, Offset, AhciReadReg (PciIo, Offset));\r
356\r
357 //\r
358 // Clear any port interrupt status\r
359 //\r
360 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_IS;\r
361 AhciWriteReg (PciIo, Offset, AhciReadReg (PciIo, Offset));\r
362\r
363 //\r
364 // Clear any HBA interrupt status\r
365 //\r
366 AhciWriteReg (PciIo, EFI_AHCI_IS_OFFSET, AhciReadReg (PciIo, EFI_AHCI_IS_OFFSET));\r
367}\r
368\r
369/**\r
370 This function is used to dump the Status Registers and if there is ERR bit set\r
371 in the Status Register, the Error Register's value is also be dumped.\r
372\r
373 @param PciIo The PCI IO protocol instance.\r
374 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.\r
375 @param Port The number of port.\r
376 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.\r
377\r
378**/\r
379VOID\r
380EFIAPI\r
381AhciDumpPortStatus (\r
382 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
383 IN EFI_AHCI_REGISTERS *AhciRegisters,\r
384 IN UINT8 Port,\r
385 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock\r
386 )\r
387{\r
388 UINTN Offset;\r
389 UINT32 Data;\r
390 UINTN FisBaseAddr;\r
391 EFI_STATUS Status;\r
392\r
393 ASSERT (PciIo != NULL);\r
394\r
395 if (AtaStatusBlock != NULL) {\r
396 ZeroMem (AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));\r
397\r
398 FisBaseAddr = (UINTN)AhciRegisters->AhciRFis + Port * sizeof (EFI_AHCI_RECEIVED_FIS);\r
399 Offset = FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET;\r
400\r
401 Status = AhciCheckMemSet (Offset, EFI_AHCI_FIS_TYPE_MASK, EFI_AHCI_FIS_REGISTER_D2H, NULL);\r
402 if (!EFI_ERROR (Status)) {\r
403 //\r
404 // If D2H FIS is received, update StatusBlock with its content.\r
405 //\r
406 CopyMem (AtaStatusBlock, (UINT8 *)Offset, sizeof (EFI_ATA_STATUS_BLOCK));\r
407 } else {\r
408 //\r
409 // If D2H FIS is not received, only update Status & Error field through PxTFD\r
410 // as there is no other way to get the content of the Shadow Register Block.\r
411 //\r
412 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;\r
413 Data = AhciReadReg (PciIo, (UINT32)Offset);\r
414\r
415 AtaStatusBlock->AtaStatus = (UINT8)Data;\r
416 if ((AtaStatusBlock->AtaStatus & BIT0) != 0) {\r
417 AtaStatusBlock->AtaError = (UINT8)(Data >> 8);\r
418 }\r
419 }\r
420 }\r
421}\r
422\r
423\r
424/**\r
425 Enable the FIS running for giving port.\r
426\r
427 @param PciIo The PCI IO protocol instance.\r
428 @param Port The number of port.\r
429 @param Timeout The timeout value of enabling FIS, uses 100ns as a unit.\r
430\r
431 @retval EFI_DEVICE_ERROR The FIS enable setting fails.\r
432 @retval EFI_TIMEOUT The FIS enable setting is time out.\r
433 @retval EFI_SUCCESS The FIS enable successfully.\r
434\r
435**/\r
436EFI_STATUS\r
437EFIAPI\r
438AhciEnableFisReceive (\r
439 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
440 IN UINT8 Port,\r
441 IN UINT64 Timeout\r
442 )\r
443{\r
444 UINT32 Offset;\r
445\r
446 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;\r
447 AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_FRE);\r
448\r
449 return EFI_SUCCESS;\r
450}\r
451\r
452/**\r
453 Disable the FIS running for giving port.\r
454\r
455 @param PciIo The PCI IO protocol instance.\r
456 @param Port The number of port.\r
457 @param Timeout The timeout value of disabling FIS, uses 100ns as a unit.\r
458\r
459 @retval EFI_DEVICE_ERROR The FIS disable setting fails.\r
460 @retval EFI_TIMEOUT The FIS disable setting is time out.\r
461 @retval EFI_UNSUPPORTED The port is in running state.\r
462 @retval EFI_SUCCESS The FIS disable successfully.\r
463\r
464**/\r
465EFI_STATUS\r
466EFIAPI\r
467AhciDisableFisReceive (\r
468 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
469 IN UINT8 Port,\r
470 IN UINT64 Timeout\r
471 )\r
472{\r
473 UINT32 Offset;\r
474 UINT32 Data;\r
475\r
476 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;\r
477 Data = AhciReadReg (PciIo, Offset);\r
478\r
479 //\r
480 // Before disabling Fis receive, the DMA engine of the port should NOT be in running status.\r
481 //\r
482 if ((Data & (EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_CR)) != 0) {\r
483 return EFI_UNSUPPORTED;\r
484 }\r
485\r
486 //\r
487 // Check if the Fis receive DMA engine for the port is running.\r
488 //\r
489 if ((Data & EFI_AHCI_PORT_CMD_FR) != EFI_AHCI_PORT_CMD_FR) {\r
490 return EFI_SUCCESS;\r
491 }\r
492\r
493 AhciAndReg (PciIo, Offset, (UINT32)~(EFI_AHCI_PORT_CMD_FRE));\r
494\r
495 return AhciWaitMmioSet (\r
496 PciIo,\r
497 Offset,\r
498 EFI_AHCI_PORT_CMD_FR,\r
499 0,\r
500 Timeout\r
501 );\r
502}\r
503\r
504\r
505\r
506/**\r
507 Build the command list, command table and prepare the fis receiver.\r
508\r
509 @param PciIo The PCI IO protocol instance.\r
510 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.\r
511 @param Port The number of port.\r
512 @param PortMultiplier The timeout value of stop.\r
513 @param CommandFis The control fis will be used for the transfer.\r
514 @param CommandList The command list will be used for the transfer.\r
515 @param AtapiCommand The atapi command will be used for the transfer.\r
516 @param AtapiCommandLength The length of the atapi command.\r
517 @param CommandSlotNumber The command slot will be used for the transfer.\r
518 @param DataPhysicalAddr The pointer to the data buffer pci bus master address.\r
519 @param DataLength The data count to be transferred.\r
520\r
521**/\r
522VOID\r
523EFIAPI\r
524AhciBuildCommand (\r
525 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
526 IN EFI_AHCI_REGISTERS *AhciRegisters,\r
527 IN UINT8 Port,\r
528 IN UINT8 PortMultiplier,\r
529 IN EFI_AHCI_COMMAND_FIS *CommandFis,\r
530 IN EFI_AHCI_COMMAND_LIST *CommandList,\r
531 IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,\r
532 IN UINT8 AtapiCommandLength,\r
533 IN UINT8 CommandSlotNumber,\r
534 IN OUT VOID *DataPhysicalAddr,\r
535 IN UINT32 DataLength\r
536 )\r
537{\r
538 UINT64 BaseAddr;\r
539 UINT32 PrdtNumber;\r
540 UINT32 PrdtIndex;\r
541 UINTN RemainedData;\r
542 UINTN MemAddr;\r
543 DATA_64 Data64;\r
544 UINT32 Offset;\r
545\r
546 //\r
547 // Filling the PRDT\r
548 //\r
549 PrdtNumber = (UINT32)DivU64x32 (((UINT64)DataLength + EFI_AHCI_MAX_DATA_PER_PRDT - 1), EFI_AHCI_MAX_DATA_PER_PRDT);\r
550\r
551 //\r
552 // According to AHCI 1.3 spec, a PRDT entry can point to a maximum 4MB data block.\r
553 // It also limits that the maximum amount of the PRDT entry in the command table\r
554 // is 65535.\r
555 //\r
556 ASSERT (PrdtNumber <= 65535);\r
557\r
558 Data64.Uint64 = (UINTN) (AhciRegisters->AhciRFis) + sizeof (EFI_AHCI_RECEIVED_FIS) * Port;\r
559\r
560 BaseAddr = Data64.Uint64;\r
561\r
562 ZeroMem ((VOID *)((UINTN) BaseAddr), sizeof (EFI_AHCI_RECEIVED_FIS));\r
563\r
564 ZeroMem (AhciRegisters->AhciCommandTable, sizeof (EFI_AHCI_COMMAND_TABLE));\r
565\r
566 CommandFis->AhciCFisPmNum = PortMultiplier;\r
567\r
568 CopyMem (&AhciRegisters->AhciCommandTable->CommandFis, CommandFis, sizeof (EFI_AHCI_COMMAND_FIS));\r
569\r
570 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;\r
571 if (AtapiCommand != NULL) {\r
572 CopyMem (\r
573 &AhciRegisters->AhciCommandTable->AtapiCmd,\r
574 AtapiCommand,\r
575 AtapiCommandLength\r
576 );\r
577\r
578 CommandList->AhciCmdA = 1;\r
579 CommandList->AhciCmdP = 1;\r
580\r
581 AhciOrReg (PciIo, Offset, (EFI_AHCI_PORT_CMD_DLAE | EFI_AHCI_PORT_CMD_ATAPI));\r
582 } else {\r
583 AhciAndReg (PciIo, Offset, (UINT32)~(EFI_AHCI_PORT_CMD_DLAE | EFI_AHCI_PORT_CMD_ATAPI));\r
584 }\r
585\r
586 RemainedData = (UINTN) DataLength;\r
587 MemAddr = (UINTN) DataPhysicalAddr;\r
588 CommandList->AhciCmdPrdtl = PrdtNumber;\r
589\r
590 for (PrdtIndex = 0; PrdtIndex < PrdtNumber; PrdtIndex++) {\r
591 if (RemainedData < EFI_AHCI_MAX_DATA_PER_PRDT) {\r
592 AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDbc = (UINT32)RemainedData - 1;\r
593 } else {\r
594 AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDbc = EFI_AHCI_MAX_DATA_PER_PRDT - 1;\r
595 }\r
596\r
597 Data64.Uint64 = (UINT64)MemAddr;\r
598 AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDba = Data64.Uint32.Lower32;\r
599 AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDbau = Data64.Uint32.Upper32;\r
600 RemainedData -= EFI_AHCI_MAX_DATA_PER_PRDT;\r
601 MemAddr += EFI_AHCI_MAX_DATA_PER_PRDT;\r
602 }\r
603\r
604 //\r
605 // Set the last PRDT to Interrupt On Complete\r
606 //\r
607 if (PrdtNumber > 0) {\r
608 AhciRegisters->AhciCommandTable->PrdtTable[PrdtNumber - 1].AhciPrdtIoc = 1;\r
609 }\r
610\r
611 CopyMem (\r
612 (VOID *) ((UINTN) AhciRegisters->AhciCmdList + (UINTN) CommandSlotNumber * sizeof (EFI_AHCI_COMMAND_LIST)),\r
613 CommandList,\r
614 sizeof (EFI_AHCI_COMMAND_LIST)\r
615 );\r
616\r
617 Data64.Uint64 = (UINT64)(UINTN) AhciRegisters->AhciCommandTablePciAddr;\r
618 AhciRegisters->AhciCmdList[CommandSlotNumber].AhciCmdCtba = Data64.Uint32.Lower32;\r
619 AhciRegisters->AhciCmdList[CommandSlotNumber].AhciCmdCtbau = Data64.Uint32.Upper32;\r
620 AhciRegisters->AhciCmdList[CommandSlotNumber].AhciCmdPmp = PortMultiplier;\r
621\r
622}\r
623\r
624/**\r
625 Buid a command FIS.\r
626\r
627 @param CmdFis A pointer to the EFI_AHCI_COMMAND_FIS data structure.\r
628 @param AtaCommandBlock A pointer to the AhciBuildCommandFis data structure.\r
629\r
630**/\r
631VOID\r
632EFIAPI\r
633AhciBuildCommandFis (\r
634 IN OUT EFI_AHCI_COMMAND_FIS *CmdFis,\r
635 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock\r
636 )\r
637{\r
638 ZeroMem (CmdFis, sizeof (EFI_AHCI_COMMAND_FIS));\r
639\r
640 CmdFis->AhciCFisType = EFI_AHCI_FIS_REGISTER_H2D;\r
641 //\r
642 // Indicator it's a command\r
643 //\r
644 CmdFis->AhciCFisCmdInd = 0x1;\r
645 CmdFis->AhciCFisCmd = AtaCommandBlock->AtaCommand;\r
646\r
647 CmdFis->AhciCFisFeature = AtaCommandBlock->AtaFeatures;\r
648 CmdFis->AhciCFisFeatureExp = AtaCommandBlock->AtaFeaturesExp;\r
649\r
650 CmdFis->AhciCFisSecNum = AtaCommandBlock->AtaSectorNumber;\r
651 CmdFis->AhciCFisSecNumExp = AtaCommandBlock->AtaSectorNumberExp;\r
652\r
653 CmdFis->AhciCFisClyLow = AtaCommandBlock->AtaCylinderLow;\r
654 CmdFis->AhciCFisClyLowExp = AtaCommandBlock->AtaCylinderLowExp;\r
655\r
656 CmdFis->AhciCFisClyHigh = AtaCommandBlock->AtaCylinderHigh;\r
657 CmdFis->AhciCFisClyHighExp = AtaCommandBlock->AtaCylinderHighExp;\r
658\r
659 CmdFis->AhciCFisSecCount = AtaCommandBlock->AtaSectorCount;\r
660 CmdFis->AhciCFisSecCountExp = AtaCommandBlock->AtaSectorCountExp;\r
661\r
662 CmdFis->AhciCFisDevHead = (UINT8) (AtaCommandBlock->AtaDeviceHead | 0xE0);\r
663}\r
664\r
665/**\r
666 Start a PIO data transfer on specific port.\r
667\r
668 @param[in] PciIo The PCI IO protocol instance.\r
669 @param[in] AhciRegisters The pointer to the EFI_AHCI_REGISTERS.\r
670 @param[in] Port The number of port.\r
671 @param[in] PortMultiplier The timeout value of stop.\r
672 @param[in] AtapiCommand The atapi command will be used for the\r
673 transfer.\r
674 @param[in] AtapiCommandLength The length of the atapi command.\r
675 @param[in] Read The transfer direction.\r
676 @param[in] AtaCommandBlock The EFI_ATA_COMMAND_BLOCK data.\r
677 @param[in, out] AtaStatusBlock The EFI_ATA_STATUS_BLOCK data.\r
678 @param[in, out] MemoryAddr The pointer to the data buffer.\r
679 @param[in] DataCount The data count to be transferred.\r
680 @param[in] Timeout The timeout value of non data transfer, uses 100ns as a unit.\r
681 @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK\r
682 used by non-blocking mode.\r
683\r
684 @retval EFI_DEVICE_ERROR The PIO data transfer abort with error occurs.\r
685 @retval EFI_TIMEOUT The operation is time out.\r
686 @retval EFI_UNSUPPORTED The device is not ready for transfer.\r
687 @retval EFI_SUCCESS The PIO data transfer executes successfully.\r
688\r
689**/\r
690EFI_STATUS\r
691EFIAPI\r
692AhciPioTransfer (\r
693 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
694 IN EFI_AHCI_REGISTERS *AhciRegisters,\r
695 IN UINT8 Port,\r
696 IN UINT8 PortMultiplier,\r
697 IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,\r
698 IN UINT8 AtapiCommandLength,\r
699 IN BOOLEAN Read,\r
700 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,\r
701 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,\r
702 IN OUT VOID *MemoryAddr,\r
703 IN UINT32 DataCount,\r
704 IN UINT64 Timeout,\r
705 IN ATA_NONBLOCK_TASK *Task\r
706 )\r
707{\r
708 EFI_STATUS Status;\r
709 UINTN FisBaseAddr;\r
710 UINTN Offset;\r
711 EFI_PHYSICAL_ADDRESS PhyAddr;\r
712 VOID *Map;\r
713 UINTN MapLength;\r
714 EFI_PCI_IO_PROTOCOL_OPERATION Flag;\r
715 UINT64 Delay;\r
716 EFI_AHCI_COMMAND_FIS CFis;\r
717 EFI_AHCI_COMMAND_LIST CmdList;\r
718 UINT32 PortTfd;\r
719 UINT32 PrdCount;\r
720 BOOLEAN InfiniteWait;\r
721 BOOLEAN PioFisReceived;\r
722 BOOLEAN D2hFisReceived;\r
723\r
724 if (Timeout == 0) {\r
725 InfiniteWait = TRUE;\r
726 } else {\r
727 InfiniteWait = FALSE;\r
728 }\r
729\r
730 if (Read) {\r
731 Flag = EfiPciIoOperationBusMasterWrite;\r
732 } else {\r
733 Flag = EfiPciIoOperationBusMasterRead;\r
734 }\r
735\r
736 //\r
737 // construct command list and command table with pci bus address\r
738 //\r
739 MapLength = DataCount;\r
740 Status = PciIo->Map (\r
741 PciIo,\r
742 Flag,\r
743 MemoryAddr,\r
744 &MapLength,\r
745 &PhyAddr,\r
746 &Map\r
747 );\r
748\r
749 if (EFI_ERROR (Status) || (DataCount != MapLength)) {\r
750 return EFI_BAD_BUFFER_SIZE;\r
751 }\r
752\r
753 //\r
754 // Package read needed\r
755 //\r
756 AhciBuildCommandFis (&CFis, AtaCommandBlock);\r
757\r
758 ZeroMem (&CmdList, sizeof (EFI_AHCI_COMMAND_LIST));\r
759\r
760 CmdList.AhciCmdCfl = EFI_AHCI_FIS_REGISTER_H2D_LENGTH / 4;\r
761 CmdList.AhciCmdW = Read ? 0 : 1;\r
762\r
763 AhciBuildCommand (\r
764 PciIo,\r
765 AhciRegisters,\r
766 Port,\r
767 PortMultiplier,\r
768 &CFis,\r
769 &CmdList,\r
770 AtapiCommand,\r
771 AtapiCommandLength,\r
772 0,\r
773 (VOID *)(UINTN)PhyAddr,\r
774 DataCount\r
775 );\r
776\r
777 Status = AhciStartCommand (\r
778 PciIo,\r
779 Port,\r
780 0,\r
781 Timeout\r
782 );\r
783 if (EFI_ERROR (Status)) {\r
784 goto Exit;\r
785 }\r
786\r
787 //\r
788 // Check the status and wait the driver sending data\r
789 //\r
790 FisBaseAddr = (UINTN)AhciRegisters->AhciRFis + Port * sizeof (EFI_AHCI_RECEIVED_FIS);\r
791\r
792 if (Read && (AtapiCommand == 0)) {\r
793 //\r
794 // Wait device sends the PIO setup fis before data transfer\r
795 //\r
796 Status = EFI_TIMEOUT;\r
797 Delay = DivU64x32 (Timeout, 1000) + 1;\r
798 do {\r
799 PioFisReceived = FALSE;\r
800 D2hFisReceived = FALSE;\r
801 Offset = FisBaseAddr + EFI_AHCI_PIO_FIS_OFFSET;\r
802 Status = AhciCheckMemSet (Offset, EFI_AHCI_FIS_TYPE_MASK, EFI_AHCI_FIS_PIO_SETUP, NULL);\r
803 if (!EFI_ERROR (Status)) {\r
804 PioFisReceived = TRUE;\r
805 }\r
806 //\r
807 // According to SATA 2.6 spec section 11.7, D2h FIS means an error encountered.\r
808 // But Qemu and Marvel 9230 sata controller may just receive a D2h FIS from device\r
809 // after the transaction is finished successfully.\r
810 // To get better device compatibilities, we further check if the PxTFD's ERR bit is set.\r
811 // By this way, we can know if there is a real error happened.\r
812 //\r
813 Offset = FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET;\r
814 Status = AhciCheckMemSet (Offset, EFI_AHCI_FIS_TYPE_MASK, EFI_AHCI_FIS_REGISTER_D2H, NULL);\r
815 if (!EFI_ERROR (Status)) {\r
816 D2hFisReceived = TRUE;\r
817 }\r
818\r
819 if (PioFisReceived || D2hFisReceived) {\r
820 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;\r
821 PortTfd = AhciReadReg (PciIo, (UINT32) Offset);\r
822 //\r
823 // PxTFD will be updated if there is a D2H or SetupFIS received. \r
824 //\r
825 if ((PortTfd & EFI_AHCI_PORT_TFD_ERR) != 0) {\r
826 Status = EFI_DEVICE_ERROR;\r
827 break;\r
828 }\r
829\r
830 PrdCount = *(volatile UINT32 *) (&(AhciRegisters->AhciCmdList[0].AhciCmdPrdbc));\r
831 if (PrdCount == DataCount) {\r
832 Status = EFI_SUCCESS;\r
833 break;\r
834 }\r
835 }\r
836\r
837 //\r
838 // Stall for 100 microseconds.\r
839 //\r
840 MicroSecondDelay(100);\r
841\r
842 Delay--;\r
843 if (Delay == 0) {\r
844 Status = EFI_TIMEOUT;\r
845 }\r
846 } while (InfiniteWait || (Delay > 0));\r
847 } else {\r
848 //\r
849 // Wait for D2H Fis is received\r
850 //\r
851 Offset = FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET;\r
852 Status = AhciWaitMemSet (\r
853 Offset,\r
854 EFI_AHCI_FIS_TYPE_MASK,\r
855 EFI_AHCI_FIS_REGISTER_D2H,\r
856 Timeout\r
857 );\r
858\r
859 if (EFI_ERROR (Status)) {\r
860 goto Exit;\r
861 }\r
862\r
863 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;\r
864 PortTfd = AhciReadReg (PciIo, (UINT32) Offset);\r
865 if ((PortTfd & EFI_AHCI_PORT_TFD_ERR) != 0) {\r
866 Status = EFI_DEVICE_ERROR;\r
867 }\r
868 }\r
869\r
870Exit:\r
871 AhciStopCommand (\r
872 PciIo,\r
873 Port,\r
874 Timeout\r
875 );\r
876\r
877 AhciDisableFisReceive (\r
878 PciIo,\r
879 Port,\r
880 Timeout\r
881 );\r
882\r
883 PciIo->Unmap (\r
884 PciIo,\r
885 Map\r
886 );\r
887\r
888 AhciDumpPortStatus (PciIo, AhciRegisters, Port, AtaStatusBlock);\r
889\r
890 return Status;\r
891}\r
892\r
893/**\r
894 Start a DMA data transfer on specific port\r
895\r
896 @param[in] Instance The ATA_ATAPI_PASS_THRU_INSTANCE protocol instance.\r
897 @param[in] AhciRegisters The pointer to the EFI_AHCI_REGISTERS.\r
898 @param[in] Port The number of port.\r
899 @param[in] PortMultiplier The timeout value of stop.\r
900 @param[in] AtapiCommand The atapi command will be used for the\r
901 transfer.\r
902 @param[in] AtapiCommandLength The length of the atapi command.\r
903 @param[in] Read The transfer direction.\r
904 @param[in] AtaCommandBlock The EFI_ATA_COMMAND_BLOCK data.\r
905 @param[in, out] AtaStatusBlock The EFI_ATA_STATUS_BLOCK data.\r
906 @param[in, out] MemoryAddr The pointer to the data buffer.\r
907 @param[in] DataCount The data count to be transferred.\r
908 @param[in] Timeout The timeout value of non data transfer, uses 100ns as a unit.\r
909 @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK\r
910 used by non-blocking mode.\r
911\r
912 @retval EFI_DEVICE_ERROR The DMA data transfer abort with error occurs.\r
913 @retval EFI_TIMEOUT The operation is time out.\r
914 @retval EFI_UNSUPPORTED The device is not ready for transfer.\r
915 @retval EFI_SUCCESS The DMA data transfer executes successfully.\r
916\r
917**/\r
918EFI_STATUS\r
919EFIAPI\r
920AhciDmaTransfer (\r
921 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,\r
922 IN EFI_AHCI_REGISTERS *AhciRegisters,\r
923 IN UINT8 Port,\r
924 IN UINT8 PortMultiplier,\r
925 IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,\r
926 IN UINT8 AtapiCommandLength,\r
927 IN BOOLEAN Read,\r
928 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,\r
929 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,\r
930 IN OUT VOID *MemoryAddr,\r
931 IN UINT32 DataCount,\r
932 IN UINT64 Timeout,\r
933 IN ATA_NONBLOCK_TASK *Task\r
934 )\r
935{\r
936 EFI_STATUS Status;\r
937 UINTN Offset;\r
938 EFI_PHYSICAL_ADDRESS PhyAddr;\r
939 VOID *Map;\r
940 UINTN MapLength;\r
941 EFI_PCI_IO_PROTOCOL_OPERATION Flag;\r
942 EFI_AHCI_COMMAND_FIS CFis;\r
943 EFI_AHCI_COMMAND_LIST CmdList;\r
944 UINTN FisBaseAddr;\r
945 UINT32 PortTfd;\r
946\r
947 EFI_PCI_IO_PROTOCOL *PciIo;\r
948 EFI_TPL OldTpl;\r
949\r
950 Map = NULL;\r
951 PciIo = Instance->PciIo;\r
952\r
953 if (PciIo == NULL) {\r
954 return EFI_INVALID_PARAMETER;\r
955 }\r
956\r
957 //\r
958 // Before starting the Blocking BlockIO operation, push to finish all non-blocking\r
959 // BlockIO tasks.\r
960 // Delay 100us to simulate the blocking time out checking.\r
961 //\r
962 OldTpl = gBS->RaiseTPL (TPL_NOTIFY);\r
963 while ((Task == NULL) && (!IsListEmpty (&Instance->NonBlockingTaskList))) {\r
964 AsyncNonBlockingTransferRoutine (NULL, Instance);\r
965 //\r
966 // Stall for 100us.\r
967 //\r
968 MicroSecondDelay (100);\r
969 }\r
970 gBS->RestoreTPL (OldTpl);\r
971\r
972 if ((Task == NULL) || ((Task != NULL) && (!Task->IsStart))) {\r
973 //\r
974 // Mark the Task to indicate that it has been started.\r
975 //\r
976 if (Task != NULL) {\r
977 Task->IsStart = TRUE;\r
978 }\r
979 if (Read) {\r
980 Flag = EfiPciIoOperationBusMasterWrite;\r
981 } else {\r
982 Flag = EfiPciIoOperationBusMasterRead;\r
983 }\r
984\r
985 //\r
986 // Construct command list and command table with pci bus address.\r
987 //\r
988 MapLength = DataCount;\r
989 Status = PciIo->Map (\r
990 PciIo,\r
991 Flag,\r
992 MemoryAddr,\r
993 &MapLength,\r
994 &PhyAddr,\r
995 &Map\r
996 );\r
997\r
998 if (EFI_ERROR (Status) || (DataCount != MapLength)) {\r
999 return EFI_BAD_BUFFER_SIZE;\r
1000 }\r
1001\r
1002 if (Task != NULL) {\r
1003 Task->Map = Map;\r
1004 }\r
1005 //\r
1006 // Package read needed\r
1007 //\r
1008 AhciBuildCommandFis (&CFis, AtaCommandBlock);\r
1009\r
1010 ZeroMem (&CmdList, sizeof (EFI_AHCI_COMMAND_LIST));\r
1011\r
1012 CmdList.AhciCmdCfl = EFI_AHCI_FIS_REGISTER_H2D_LENGTH / 4;\r
1013 CmdList.AhciCmdW = Read ? 0 : 1;\r
1014\r
1015 AhciBuildCommand (\r
1016 PciIo,\r
1017 AhciRegisters,\r
1018 Port,\r
1019 PortMultiplier,\r
1020 &CFis,\r
1021 &CmdList,\r
1022 AtapiCommand,\r
1023 AtapiCommandLength,\r
1024 0,\r
1025 (VOID *)(UINTN)PhyAddr,\r
1026 DataCount\r
1027 );\r
1028\r
1029 Status = AhciStartCommand (\r
1030 PciIo,\r
1031 Port,\r
1032 0,\r
1033 Timeout\r
1034 );\r
1035 if (EFI_ERROR (Status)) {\r
1036 goto Exit;\r
1037 }\r
1038 }\r
1039\r
1040 //\r
1041 // Wait for command compelte\r
1042 //\r
1043 FisBaseAddr = (UINTN)AhciRegisters->AhciRFis + Port * sizeof (EFI_AHCI_RECEIVED_FIS);\r
1044 Offset = FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET;\r
1045 if (Task != NULL) {\r
1046 //\r
1047 // For Non-blocking\r
1048 //\r
1049 Status = AhciCheckMemSet (\r
1050 Offset,\r
1051 EFI_AHCI_FIS_TYPE_MASK,\r
1052 EFI_AHCI_FIS_REGISTER_D2H,\r
1053 Task\r
1054 );\r
1055 } else {\r
1056 Status = AhciWaitMemSet (\r
1057 Offset,\r
1058 EFI_AHCI_FIS_TYPE_MASK,\r
1059 EFI_AHCI_FIS_REGISTER_D2H,\r
1060 Timeout\r
1061 );\r
1062 }\r
1063\r
1064 if (EFI_ERROR (Status)) {\r
1065 goto Exit;\r
1066 }\r
1067\r
1068 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;\r
1069 PortTfd = AhciReadReg (PciIo, (UINT32) Offset);\r
1070 if ((PortTfd & EFI_AHCI_PORT_TFD_ERR) != 0) {\r
1071 Status = EFI_DEVICE_ERROR;\r
1072 }\r
1073\r
1074Exit:\r
1075 //\r
1076 // For Blocking mode, the command should be stopped, the Fis should be disabled\r
1077 // and the PciIo should be unmapped.\r
1078 // For non-blocking mode, only when a error is happened (if the return status is\r
1079 // EFI_NOT_READY that means the command doesn't finished, try again.), first do the\r
1080 // context cleanup, then set the packet's Asb status.\r
1081 //\r
1082 if (Task == NULL ||\r
1083 ((Task != NULL) && (Status != EFI_NOT_READY))\r
1084 ) {\r
1085 AhciStopCommand (\r
1086 PciIo,\r
1087 Port,\r
1088 Timeout\r
1089 );\r
1090\r
1091 AhciDisableFisReceive (\r
1092 PciIo,\r
1093 Port,\r
1094 Timeout\r
1095 );\r
1096\r
1097 PciIo->Unmap (\r
1098 PciIo,\r
1099 (Task != NULL) ? Task->Map : Map\r
1100 );\r
1101\r
1102 if (Task != NULL) {\r
1103 Task->Packet->Asb->AtaStatus = 0x01;\r
1104 }\r
1105 }\r
1106\r
1107 AhciDumpPortStatus (PciIo, AhciRegisters, Port, AtaStatusBlock);\r
1108 return Status;\r
1109}\r
1110\r
1111/**\r
1112 Start a non data transfer on specific port.\r
1113\r
1114 @param[in] PciIo The PCI IO protocol instance.\r
1115 @param[in] AhciRegisters The pointer to the EFI_AHCI_REGISTERS.\r
1116 @param[in] Port The number of port.\r
1117 @param[in] PortMultiplier The timeout value of stop.\r
1118 @param[in] AtapiCommand The atapi command will be used for the\r
1119 transfer.\r
1120 @param[in] AtapiCommandLength The length of the atapi command.\r
1121 @param[in] AtaCommandBlock The EFI_ATA_COMMAND_BLOCK data.\r
1122 @param[in, out] AtaStatusBlock The EFI_ATA_STATUS_BLOCK data.\r
1123 @param[in] Timeout The timeout value of non data transfer, uses 100ns as a unit.\r
1124 @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK\r
1125 used by non-blocking mode.\r
1126\r
1127 @retval EFI_DEVICE_ERROR The non data transfer abort with error occurs.\r
1128 @retval EFI_TIMEOUT The operation is time out.\r
1129 @retval EFI_UNSUPPORTED The device is not ready for transfer.\r
1130 @retval EFI_SUCCESS The non data transfer executes successfully.\r
1131\r
1132**/\r
1133EFI_STATUS\r
1134EFIAPI\r
1135AhciNonDataTransfer (\r
1136 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
1137 IN EFI_AHCI_REGISTERS *AhciRegisters,\r
1138 IN UINT8 Port,\r
1139 IN UINT8 PortMultiplier,\r
1140 IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,\r
1141 IN UINT8 AtapiCommandLength,\r
1142 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,\r
1143 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,\r
1144 IN UINT64 Timeout,\r
1145 IN ATA_NONBLOCK_TASK *Task\r
1146 )\r
1147{\r
1148 EFI_STATUS Status;\r
1149 UINTN FisBaseAddr;\r
1150 UINTN Offset;\r
1151 UINT32 PortTfd;\r
1152 EFI_AHCI_COMMAND_FIS CFis;\r
1153 EFI_AHCI_COMMAND_LIST CmdList;\r
1154\r
1155 //\r
1156 // Package read needed\r
1157 //\r
1158 AhciBuildCommandFis (&CFis, AtaCommandBlock);\r
1159\r
1160 ZeroMem (&CmdList, sizeof (EFI_AHCI_COMMAND_LIST));\r
1161\r
1162 CmdList.AhciCmdCfl = EFI_AHCI_FIS_REGISTER_H2D_LENGTH / 4;\r
1163\r
1164 AhciBuildCommand (\r
1165 PciIo,\r
1166 AhciRegisters,\r
1167 Port,\r
1168 PortMultiplier,\r
1169 &CFis,\r
1170 &CmdList,\r
1171 AtapiCommand,\r
1172 AtapiCommandLength,\r
1173 0,\r
1174 NULL,\r
1175 0\r
1176 );\r
1177\r
1178 Status = AhciStartCommand (\r
1179 PciIo,\r
1180 Port,\r
1181 0,\r
1182 Timeout\r
1183 );\r
1184 if (EFI_ERROR (Status)) {\r
1185 goto Exit;\r
1186 }\r
1187\r
1188 //\r
1189 // Wait device sends the Response Fis\r
1190 //\r
1191 FisBaseAddr = (UINTN)AhciRegisters->AhciRFis + Port * sizeof (EFI_AHCI_RECEIVED_FIS);\r
1192 Offset = FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET;\r
1193 Status = AhciWaitMemSet (\r
1194 Offset,\r
1195 EFI_AHCI_FIS_TYPE_MASK,\r
1196 EFI_AHCI_FIS_REGISTER_D2H,\r
1197 Timeout\r
1198 );\r
1199\r
1200 if (EFI_ERROR (Status)) {\r
1201 goto Exit;\r
1202 }\r
1203\r
1204 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;\r
1205 PortTfd = AhciReadReg (PciIo, (UINT32) Offset);\r
1206 if ((PortTfd & EFI_AHCI_PORT_TFD_ERR) != 0) {\r
1207 Status = EFI_DEVICE_ERROR;\r
1208 }\r
1209\r
1210Exit:\r
1211 AhciStopCommand (\r
1212 PciIo,\r
1213 Port,\r
1214 Timeout\r
1215 );\r
1216\r
1217 AhciDisableFisReceive (\r
1218 PciIo,\r
1219 Port,\r
1220 Timeout\r
1221 );\r
1222\r
1223 AhciDumpPortStatus (PciIo, AhciRegisters, Port, AtaStatusBlock);\r
1224\r
1225 return Status;\r
1226}\r
1227\r
1228/**\r
1229 Stop command running for giving port\r
1230\r
1231 @param PciIo The PCI IO protocol instance.\r
1232 @param Port The number of port.\r
1233 @param Timeout The timeout value of stop, uses 100ns as a unit.\r
1234\r
1235 @retval EFI_DEVICE_ERROR The command stop unsuccessfully.\r
1236 @retval EFI_TIMEOUT The operation is time out.\r
1237 @retval EFI_SUCCESS The command stop successfully.\r
1238\r
1239**/\r
1240EFI_STATUS\r
1241EFIAPI\r
1242AhciStopCommand (\r
1243 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
1244 IN UINT8 Port,\r
1245 IN UINT64 Timeout\r
1246 )\r
1247{\r
1248 UINT32 Offset;\r
1249 UINT32 Data;\r
1250\r
1251 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;\r
1252 Data = AhciReadReg (PciIo, Offset);\r
1253\r
1254 if ((Data & (EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_CR)) == 0) {\r
1255 return EFI_SUCCESS;\r
1256 }\r
1257\r
1258 if ((Data & EFI_AHCI_PORT_CMD_ST) != 0) {\r
1259 AhciAndReg (PciIo, Offset, (UINT32)~(EFI_AHCI_PORT_CMD_ST));\r
1260 }\r
1261\r
1262 return AhciWaitMmioSet (\r
1263 PciIo,\r
1264 Offset,\r
1265 EFI_AHCI_PORT_CMD_CR,\r
1266 0,\r
1267 Timeout\r
1268 );\r
1269}\r
1270\r
1271/**\r
1272 Start command for give slot on specific port.\r
1273\r
1274 @param PciIo The PCI IO protocol instance.\r
1275 @param Port The number of port.\r
1276 @param CommandSlot The number of Command Slot.\r
1277 @param Timeout The timeout value of start, uses 100ns as a unit.\r
1278\r
1279 @retval EFI_DEVICE_ERROR The command start unsuccessfully.\r
1280 @retval EFI_TIMEOUT The operation is time out.\r
1281 @retval EFI_SUCCESS The command start successfully.\r
1282\r
1283**/\r
1284EFI_STATUS\r
1285EFIAPI\r
1286AhciStartCommand (\r
1287 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
1288 IN UINT8 Port,\r
1289 IN UINT8 CommandSlot,\r
1290 IN UINT64 Timeout\r
1291 )\r
1292{\r
1293 UINT32 CmdSlotBit;\r
1294 EFI_STATUS Status;\r
1295 UINT32 PortStatus;\r
1296 UINT32 StartCmd;\r
1297 UINT32 PortTfd;\r
1298 UINT32 Offset;\r
1299 UINT32 Capability;\r
1300\r
1301 //\r
1302 // Collect AHCI controller information\r
1303 //\r
1304 Capability = AhciReadReg(PciIo, EFI_AHCI_CAPABILITY_OFFSET);\r
1305\r
1306 CmdSlotBit = (UINT32) (1 << CommandSlot);\r
1307\r
1308 AhciClearPortStatus (\r
1309 PciIo,\r
1310 Port\r
1311 );\r
1312\r
1313 Status = AhciEnableFisReceive (\r
1314 PciIo,\r
1315 Port,\r
1316 Timeout\r
1317 );\r
1318\r
1319 if (EFI_ERROR (Status)) {\r
1320 return Status;\r
1321 }\r
1322\r
1323 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;\r
1324 PortStatus = AhciReadReg (PciIo, Offset);\r
1325\r
1326 StartCmd = 0;\r
1327 if ((PortStatus & EFI_AHCI_PORT_CMD_ALPE) != 0) {\r
1328 StartCmd = AhciReadReg (PciIo, Offset);\r
1329 StartCmd &= ~EFI_AHCI_PORT_CMD_ICC_MASK;\r
1330 StartCmd |= EFI_AHCI_PORT_CMD_ACTIVE;\r
1331 }\r
1332\r
1333 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;\r
1334 PortTfd = AhciReadReg (PciIo, Offset);\r
1335\r
1336 if ((PortTfd & (EFI_AHCI_PORT_TFD_BSY | EFI_AHCI_PORT_TFD_DRQ)) != 0) {\r
1337 if ((Capability & BIT24) != 0) {\r
1338 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;\r
1339 AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_CLO);\r
1340\r
1341 AhciWaitMmioSet (\r
1342 PciIo,\r
1343 Offset,\r
1344 EFI_AHCI_PORT_CMD_CLO,\r
1345 0,\r
1346 Timeout\r
1347 );\r
1348 }\r
1349 }\r
1350\r
1351 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;\r
1352 AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_ST | StartCmd);\r
1353\r
1354 //\r
1355 // Setting the command\r
1356 //\r
1357 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CI;\r
1358 AhciAndReg (PciIo, Offset, 0);\r
1359 AhciOrReg (PciIo, Offset, CmdSlotBit);\r
1360\r
1361 return EFI_SUCCESS;\r
1362}\r
1363\r
1364/**\r
1365 Do AHCI port reset.\r
1366\r
1367 @param PciIo The PCI IO protocol instance.\r
1368 @param Port The number of port.\r
1369 @param Timeout The timeout value of reset, uses 100ns as a unit.\r
1370\r
1371 @retval EFI_DEVICE_ERROR The port reset unsuccessfully\r
1372 @retval EFI_TIMEOUT The reset operation is time out.\r
1373 @retval EFI_SUCCESS The port reset successfully.\r
1374\r
1375**/\r
1376EFI_STATUS\r
1377EFIAPI\r
1378AhciPortReset (\r
1379 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
1380 IN UINT8 Port,\r
1381 IN UINT64 Timeout\r
1382 )\r
1383{\r
1384 EFI_STATUS Status;\r
1385 UINT32 Offset;\r
1386\r
1387 AhciClearPortStatus (PciIo, Port);\r
1388\r
1389 AhciStopCommand (PciIo, Port, Timeout);\r
1390\r
1391 AhciDisableFisReceive (PciIo, Port, Timeout);\r
1392\r
1393 AhciEnableFisReceive (PciIo, Port, Timeout);\r
1394\r
1395 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SCTL;\r
1396\r
1397 AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_SCTL_DET_INIT);\r
1398\r
1399 //\r
1400 // wait 5 millisecond before de-assert DET\r
1401 //\r
1402 MicroSecondDelay (5000);\r
1403\r
1404 AhciAndReg (PciIo, Offset, (UINT32)EFI_AHCI_PORT_SCTL_MASK);\r
1405\r
1406 //\r
1407 // wait 5 millisecond before de-assert DET\r
1408 //\r
1409 MicroSecondDelay (5000);\r
1410\r
1411 //\r
1412 // Wait for communication to be re-established\r
1413 //\r
1414 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SSTS;\r
1415 Status = AhciWaitMmioSet (\r
1416 PciIo,\r
1417 Offset,\r
1418 EFI_AHCI_PORT_SSTS_DET_MASK,\r
1419 EFI_AHCI_PORT_SSTS_DET_PCE,\r
1420 Timeout\r
1421 );\r
1422\r
1423 if (EFI_ERROR (Status)) {\r
1424 DEBUG ((EFI_D_ERROR, "Port %d COMRESET failed: %r\n", Port, Status));\r
1425 return Status;\r
1426 }\r
1427\r
1428 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SERR;\r
1429 AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_ERR_CLEAR);\r
1430\r
1431 return EFI_SUCCESS;\r
1432}\r
1433\r
1434/**\r
1435 Do AHCI HBA reset.\r
1436\r
1437 @param PciIo The PCI IO protocol instance.\r
1438 @param Timeout The timeout value of reset, uses 100ns as a unit.\r
1439\r
1440 @retval EFI_DEVICE_ERROR AHCI controller is failed to complete hardware reset.\r
1441 @retval EFI_TIMEOUT The reset operation is time out.\r
1442 @retval EFI_SUCCESS AHCI controller is reset successfully.\r
1443\r
1444**/\r
1445EFI_STATUS\r
1446EFIAPI\r
1447AhciReset (\r
1448 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
1449 IN UINT64 Timeout\r
1450 )\r
1451{\r
1452 UINT64 Delay;\r
1453 UINT32 Value;\r
1454\r
1455 //\r
1456 // Make sure that GHC.AE bit is set before accessing any AHCI registers.\r
1457 //\r
1458 Value = AhciReadReg(PciIo, EFI_AHCI_GHC_OFFSET);\r
1459\r
1460 if ((Value & EFI_AHCI_GHC_ENABLE) == 0) {\r
1461 AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);\r
1462 }\r
1463\r
1464 AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_RESET);\r
1465\r
1466 Delay = DivU64x32(Timeout, 1000) + 1;\r
1467\r
1468 do {\r
1469 Value = AhciReadReg(PciIo, EFI_AHCI_GHC_OFFSET);\r
1470\r
1471 if ((Value & EFI_AHCI_GHC_RESET) == 0) {\r
1472 break;\r
1473 }\r
1474\r
1475 //\r
1476 // Stall for 100 microseconds.\r
1477 //\r
1478 MicroSecondDelay(100);\r
1479\r
1480 Delay--;\r
1481 } while (Delay > 0);\r
1482\r
1483 if (Delay == 0) {\r
1484 return EFI_TIMEOUT;\r
1485 }\r
1486\r
1487 return EFI_SUCCESS;\r
1488}\r
1489\r
1490/**\r
1491 Send SMART Return Status command to check if the execution of SMART cmd is successful or not.\r
1492\r
1493 @param PciIo The PCI IO protocol instance.\r
1494 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.\r
1495 @param Port The number of port.\r
1496 @param PortMultiplier The port multiplier port number.\r
1497 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.\r
1498\r
1499 @retval EFI_SUCCESS Successfully get the return status of S.M.A.R.T command execution.\r
1500 @retval Others Fail to get return status data.\r
1501\r
1502**/\r
1503EFI_STATUS\r
1504EFIAPI\r
1505AhciAtaSmartReturnStatusCheck (\r
1506 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
1507 IN EFI_AHCI_REGISTERS *AhciRegisters,\r
1508 IN UINT8 Port,\r
1509 IN UINT8 PortMultiplier,\r
1510 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock\r
1511 )\r
1512{\r
1513 EFI_STATUS Status;\r
1514 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;\r
1515 UINT8 LBAMid;\r
1516 UINT8 LBAHigh;\r
1517 UINTN FisBaseAddr;\r
1518 UINT32 Value;\r
1519\r
1520 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));\r
1521\r
1522 AtaCommandBlock.AtaCommand = ATA_CMD_SMART;\r
1523 AtaCommandBlock.AtaFeatures = ATA_SMART_RETURN_STATUS;\r
1524 AtaCommandBlock.AtaCylinderLow = ATA_CONSTANT_4F;\r
1525 AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;\r
1526\r
1527 //\r
1528 // Send S.M.A.R.T Read Return Status command to device\r
1529 //\r
1530 Status = AhciNonDataTransfer (\r
1531 PciIo,\r
1532 AhciRegisters,\r
1533 (UINT8)Port,\r
1534 (UINT8)PortMultiplier,\r
1535 NULL,\r
1536 0,\r
1537 &AtaCommandBlock,\r
1538 AtaStatusBlock,\r
1539 ATA_ATAPI_TIMEOUT,\r
1540 NULL\r
1541 );\r
1542\r
1543 if (EFI_ERROR (Status)) {\r
1544 REPORT_STATUS_CODE (\r
1545 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
1546 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_DISABLED)\r
1547 );\r
1548 return EFI_DEVICE_ERROR;\r
1549 }\r
1550\r
1551 REPORT_STATUS_CODE (\r
1552 EFI_PROGRESS_CODE,\r
1553 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_ENABLE)\r
1554 );\r
1555\r
1556 FisBaseAddr = (UINTN)AhciRegisters->AhciRFis + Port * sizeof (EFI_AHCI_RECEIVED_FIS);\r
1557\r
1558 Value = *(UINT32 *) (FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET);\r
1559\r
1560 if ((Value & EFI_AHCI_FIS_TYPE_MASK) == EFI_AHCI_FIS_REGISTER_D2H) {\r
1561 LBAMid = ((UINT8 *)(UINTN)(FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET))[5];\r
1562 LBAHigh = ((UINT8 *)(UINTN)(FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET))[6];\r
1563\r
1564 if ((LBAMid == 0x4f) && (LBAHigh == 0xc2)) {\r
1565 //\r
1566 // The threshold exceeded condition is not detected by the device\r
1567 //\r
1568 DEBUG ((EFI_D_INFO, "The S.M.A.R.T threshold exceeded condition is not detected\n"));\r
1569 REPORT_STATUS_CODE (\r
1570 EFI_PROGRESS_CODE,\r
1571 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_UNDERTHRESHOLD)\r
1572 );\r
1573 } else if ((LBAMid == 0xf4) && (LBAHigh == 0x2c)) {\r
1574 //\r
1575 // The threshold exceeded condition is detected by the device\r
1576 //\r
1577 DEBUG ((EFI_D_INFO, "The S.M.A.R.T threshold exceeded condition is detected\n"));\r
1578 REPORT_STATUS_CODE (\r
1579 EFI_PROGRESS_CODE,\r
1580 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_OVERTHRESHOLD)\r
1581 );\r
1582 }\r
1583 }\r
1584\r
1585 return EFI_SUCCESS;\r
1586}\r
1587\r
1588/**\r
1589 Enable SMART command of the disk if supported.\r
1590\r
1591 @param PciIo The PCI IO protocol instance.\r
1592 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.\r
1593 @param Port The number of port.\r
1594 @param PortMultiplier The port multiplier port number.\r
1595 @param IdentifyData A pointer to data buffer which is used to contain IDENTIFY data.\r
1596 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.\r
1597\r
1598**/\r
1599VOID\r
1600EFIAPI\r
1601AhciAtaSmartSupport (\r
1602 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
1603 IN EFI_AHCI_REGISTERS *AhciRegisters,\r
1604 IN UINT8 Port,\r
1605 IN UINT8 PortMultiplier,\r
1606 IN EFI_IDENTIFY_DATA *IdentifyData,\r
1607 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock\r
1608 )\r
1609{\r
1610 EFI_STATUS Status;\r
1611 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;\r
1612\r
1613 //\r
1614 // Detect if the device supports S.M.A.R.T.\r
1615 //\r
1616 if ((IdentifyData->AtaData.command_set_supported_82 & 0x0001) != 0x0001) {\r
1617 //\r
1618 // S.M.A.R.T is not supported by the device\r
1619 //\r
1620 DEBUG ((EFI_D_INFO, "S.M.A.R.T feature is not supported at port [%d] PortMultiplier [%d]!\n",\r
1621 Port, PortMultiplier));\r
1622 REPORT_STATUS_CODE (\r
1623 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
1624 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_NOTSUPPORTED)\r
1625 );\r
1626 } else {\r
1627 //\r
1628 // Check if the feature is enabled. If not, then enable S.M.A.R.T.\r
1629 //\r
1630 if ((IdentifyData->AtaData.command_set_feature_enb_85 & 0x0001) != 0x0001) {\r
1631\r
1632 REPORT_STATUS_CODE (\r
1633 EFI_PROGRESS_CODE,\r
1634 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_DISABLE)\r
1635 );\r
1636\r
1637 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));\r
1638\r
1639 AtaCommandBlock.AtaCommand = ATA_CMD_SMART;\r
1640 AtaCommandBlock.AtaFeatures = ATA_SMART_ENABLE_OPERATION;\r
1641 AtaCommandBlock.AtaCylinderLow = ATA_CONSTANT_4F;\r
1642 AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;\r
1643\r
1644 //\r
1645 // Send S.M.A.R.T Enable command to device\r
1646 //\r
1647 Status = AhciNonDataTransfer (\r
1648 PciIo,\r
1649 AhciRegisters,\r
1650 (UINT8)Port,\r
1651 (UINT8)PortMultiplier,\r
1652 NULL,\r
1653 0,\r
1654 &AtaCommandBlock,\r
1655 AtaStatusBlock,\r
1656 ATA_ATAPI_TIMEOUT,\r
1657 NULL\r
1658 );\r
1659\r
1660\r
1661 if (!EFI_ERROR (Status)) {\r
1662 //\r
1663 // Send S.M.A.R.T AutoSave command to device\r
1664 //\r
1665 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));\r
1666\r
1667 AtaCommandBlock.AtaCommand = ATA_CMD_SMART;\r
1668 AtaCommandBlock.AtaFeatures = 0xD2;\r
1669 AtaCommandBlock.AtaSectorCount = 0xF1;\r
1670 AtaCommandBlock.AtaCylinderLow = ATA_CONSTANT_4F;\r
1671 AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;\r
1672\r
1673 Status = AhciNonDataTransfer (\r
1674 PciIo,\r
1675 AhciRegisters,\r
1676 (UINT8)Port,\r
1677 (UINT8)PortMultiplier,\r
1678 NULL,\r
1679 0,\r
1680 &AtaCommandBlock,\r
1681 AtaStatusBlock,\r
1682 ATA_ATAPI_TIMEOUT,\r
1683 NULL\r
1684 );\r
1685\r
1686 if (!EFI_ERROR (Status)) {\r
1687 Status = AhciAtaSmartReturnStatusCheck (\r
1688 PciIo,\r
1689 AhciRegisters,\r
1690 (UINT8)Port,\r
1691 (UINT8)PortMultiplier,\r
1692 AtaStatusBlock\r
1693 );\r
1694 }\r
1695 }\r
1696 }\r
1697 DEBUG ((EFI_D_INFO, "Enabled S.M.A.R.T feature at port [%d] PortMultiplier [%d]!\n",\r
1698 Port, PortMultiplier));\r
1699 }\r
1700\r
1701 return ;\r
1702}\r
1703\r
1704/**\r
1705 Send Buffer cmd to specific device.\r
1706\r
1707 @param PciIo The PCI IO protocol instance.\r
1708 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.\r
1709 @param Port The number of port.\r
1710 @param PortMultiplier The port multiplier port number.\r
1711 @param Buffer The data buffer to store IDENTIFY PACKET data.\r
1712\r
1713 @retval EFI_DEVICE_ERROR The cmd abort with error occurs.\r
1714 @retval EFI_TIMEOUT The operation is time out.\r
1715 @retval EFI_UNSUPPORTED The device is not ready for executing.\r
1716 @retval EFI_SUCCESS The cmd executes successfully.\r
1717\r
1718**/\r
1719EFI_STATUS\r
1720EFIAPI\r
1721AhciIdentify (\r
1722 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
1723 IN EFI_AHCI_REGISTERS *AhciRegisters,\r
1724 IN UINT8 Port,\r
1725 IN UINT8 PortMultiplier,\r
1726 IN OUT EFI_IDENTIFY_DATA *Buffer\r
1727 )\r
1728{\r
1729 EFI_STATUS Status;\r
1730 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;\r
1731 EFI_ATA_STATUS_BLOCK AtaStatusBlock;\r
1732\r
1733 if (PciIo == NULL || AhciRegisters == NULL || Buffer == NULL) {\r
1734 return EFI_INVALID_PARAMETER;\r
1735 }\r
1736\r
1737 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));\r
1738 ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));\r
1739\r
1740 AtaCommandBlock.AtaCommand = ATA_CMD_IDENTIFY_DRIVE;\r
1741 AtaCommandBlock.AtaSectorCount = 1;\r
1742\r
1743 Status = AhciPioTransfer (\r
1744 PciIo,\r
1745 AhciRegisters,\r
1746 Port,\r
1747 PortMultiplier,\r
1748 NULL,\r
1749 0,\r
1750 TRUE,\r
1751 &AtaCommandBlock,\r
1752 &AtaStatusBlock,\r
1753 Buffer,\r
1754 sizeof (EFI_IDENTIFY_DATA),\r
1755 ATA_ATAPI_TIMEOUT,\r
1756 NULL\r
1757 );\r
1758\r
1759 return Status;\r
1760}\r
1761\r
1762/**\r
1763 Send Buffer cmd to specific device.\r
1764\r
1765 @param PciIo The PCI IO protocol instance.\r
1766 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.\r
1767 @param Port The number of port.\r
1768 @param PortMultiplier The port multiplier port number.\r
1769 @param Buffer The data buffer to store IDENTIFY PACKET data.\r
1770\r
1771 @retval EFI_DEVICE_ERROR The cmd abort with error occurs.\r
1772 @retval EFI_TIMEOUT The operation is time out.\r
1773 @retval EFI_UNSUPPORTED The device is not ready for executing.\r
1774 @retval EFI_SUCCESS The cmd executes successfully.\r
1775\r
1776**/\r
1777EFI_STATUS\r
1778EFIAPI\r
1779AhciIdentifyPacket (\r
1780 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
1781 IN EFI_AHCI_REGISTERS *AhciRegisters,\r
1782 IN UINT8 Port,\r
1783 IN UINT8 PortMultiplier,\r
1784 IN OUT EFI_IDENTIFY_DATA *Buffer\r
1785 )\r
1786{\r
1787 EFI_STATUS Status;\r
1788 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;\r
1789 EFI_ATA_STATUS_BLOCK AtaStatusBlock;\r
1790\r
1791 if (PciIo == NULL || AhciRegisters == NULL) {\r
1792 return EFI_INVALID_PARAMETER;\r
1793 }\r
1794\r
1795 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));\r
1796 ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));\r
1797\r
1798 AtaCommandBlock.AtaCommand = ATA_CMD_IDENTIFY_DEVICE;\r
1799 AtaCommandBlock.AtaSectorCount = 1;\r
1800\r
1801 Status = AhciPioTransfer (\r
1802 PciIo,\r
1803 AhciRegisters,\r
1804 Port,\r
1805 PortMultiplier,\r
1806 NULL,\r
1807 0,\r
1808 TRUE,\r
1809 &AtaCommandBlock,\r
1810 &AtaStatusBlock,\r
1811 Buffer,\r
1812 sizeof (EFI_IDENTIFY_DATA),\r
1813 ATA_ATAPI_TIMEOUT,\r
1814 NULL\r
1815 );\r
1816\r
1817 return Status;\r
1818}\r
1819\r
1820/**\r
1821 Send SET FEATURE cmd on specific device.\r
1822\r
1823 @param PciIo The PCI IO protocol instance.\r
1824 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.\r
1825 @param Port The number of port.\r
1826 @param PortMultiplier The port multiplier port number.\r
1827 @param Feature The data to send Feature register.\r
1828 @param FeatureSpecificData The specific data for SET FEATURE cmd.\r
1829\r
1830 @retval EFI_DEVICE_ERROR The cmd abort with error occurs.\r
1831 @retval EFI_TIMEOUT The operation is time out.\r
1832 @retval EFI_UNSUPPORTED The device is not ready for executing.\r
1833 @retval EFI_SUCCESS The cmd executes successfully.\r
1834\r
1835**/\r
1836EFI_STATUS\r
1837EFIAPI\r
1838AhciDeviceSetFeature (\r
1839 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
1840 IN EFI_AHCI_REGISTERS *AhciRegisters,\r
1841 IN UINT8 Port,\r
1842 IN UINT8 PortMultiplier,\r
1843 IN UINT16 Feature,\r
1844 IN UINT32 FeatureSpecificData\r
1845 )\r
1846{\r
1847 EFI_STATUS Status;\r
1848 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;\r
1849 EFI_ATA_STATUS_BLOCK AtaStatusBlock;\r
1850\r
1851 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));\r
1852 ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));\r
1853\r
1854 AtaCommandBlock.AtaCommand = ATA_CMD_SET_FEATURES;\r
1855 AtaCommandBlock.AtaFeatures = (UINT8) Feature;\r
1856 AtaCommandBlock.AtaFeaturesExp = (UINT8) (Feature >> 8);\r
1857 AtaCommandBlock.AtaSectorCount = (UINT8) FeatureSpecificData;\r
1858 AtaCommandBlock.AtaSectorNumber = (UINT8) (FeatureSpecificData >> 8);\r
1859 AtaCommandBlock.AtaCylinderLow = (UINT8) (FeatureSpecificData >> 16);\r
1860 AtaCommandBlock.AtaCylinderHigh = (UINT8) (FeatureSpecificData >> 24);\r
1861\r
1862 Status = AhciNonDataTransfer (\r
1863 PciIo,\r
1864 AhciRegisters,\r
1865 (UINT8)Port,\r
1866 (UINT8)PortMultiplier,\r
1867 NULL,\r
1868 0,\r
1869 &AtaCommandBlock,\r
1870 &AtaStatusBlock,\r
1871 ATA_ATAPI_TIMEOUT,\r
1872 NULL\r
1873 );\r
1874\r
1875 return Status;\r
1876}\r
1877\r
1878/**\r
1879 This function is used to send out ATAPI commands conforms to the Packet Command\r
1880 with PIO Protocol.\r
1881\r
1882 @param PciIo The PCI IO protocol instance.\r
1883 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.\r
1884 @param Port The number of port.\r
1885 @param PortMultiplier The number of port multiplier.\r
1886 @param Packet A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET structure.\r
1887\r
1888 @retval EFI_SUCCESS send out the ATAPI packet command successfully\r
1889 and device sends data successfully.\r
1890 @retval EFI_DEVICE_ERROR the device failed to send data.\r
1891\r
1892**/\r
1893EFI_STATUS\r
1894EFIAPI\r
1895AhciPacketCommandExecute (\r
1896 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
1897 IN EFI_AHCI_REGISTERS *AhciRegisters,\r
1898 IN UINT8 Port,\r
1899 IN UINT8 PortMultiplier,\r
1900 IN EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet\r
1901 )\r
1902{\r
1903 EFI_STATUS Status;\r
1904 VOID *Buffer;\r
1905 UINT32 Length;\r
1906 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;\r
1907 EFI_ATA_STATUS_BLOCK AtaStatusBlock;\r
1908 BOOLEAN Read;\r
1909\r
1910 if (Packet == NULL || Packet->Cdb == NULL) {\r
1911 return EFI_INVALID_PARAMETER;\r
1912 }\r
1913\r
1914 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));\r
1915 ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));\r
1916 AtaCommandBlock.AtaCommand = ATA_CMD_PACKET;\r
1917 //\r
1918 // No OVL; No DMA\r
1919 //\r
1920 AtaCommandBlock.AtaFeatures = 0x00;\r
1921 //\r
1922 // set the transfersize to ATAPI_MAX_BYTE_COUNT to let the device\r
1923 // determine how many data should be transferred.\r
1924 //\r
1925 AtaCommandBlock.AtaCylinderLow = (UINT8) (ATAPI_MAX_BYTE_COUNT & 0x00ff);\r
1926 AtaCommandBlock.AtaCylinderHigh = (UINT8) (ATAPI_MAX_BYTE_COUNT >> 8);\r
1927\r
1928 if (Packet->DataDirection == EFI_EXT_SCSI_DATA_DIRECTION_READ) {\r
1929 Buffer = Packet->InDataBuffer;\r
1930 Length = Packet->InTransferLength;\r
1931 Read = TRUE;\r
1932 } else {\r
1933 Buffer = Packet->OutDataBuffer;\r
1934 Length = Packet->OutTransferLength;\r
1935 Read = FALSE;\r
1936 }\r
1937\r
1938 if (Length == 0) {\r
1939 Status = AhciNonDataTransfer (\r
1940 PciIo,\r
1941 AhciRegisters,\r
1942 Port,\r
1943 PortMultiplier,\r
1944 Packet->Cdb,\r
1945 Packet->CdbLength,\r
1946 &AtaCommandBlock,\r
1947 &AtaStatusBlock,\r
1948 Packet->Timeout,\r
1949 NULL\r
1950 );\r
1951 } else {\r
1952 Status = AhciPioTransfer (\r
1953 PciIo,\r
1954 AhciRegisters,\r
1955 Port,\r
1956 PortMultiplier,\r
1957 Packet->Cdb,\r
1958 Packet->CdbLength,\r
1959 Read,\r
1960 &AtaCommandBlock,\r
1961 &AtaStatusBlock,\r
1962 Buffer,\r
1963 Length,\r
1964 Packet->Timeout,\r
1965 NULL\r
1966 );\r
1967 }\r
1968 return Status;\r
1969}\r
1970\r
1971/**\r
1972 Allocate transfer-related data struct which is used at AHCI mode.\r
1973\r
1974 @param PciIo The PCI IO protocol instance.\r
1975 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.\r
1976\r
1977**/\r
1978EFI_STATUS\r
1979EFIAPI\r
1980AhciCreateTransferDescriptor (\r
1981 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
1982 IN OUT EFI_AHCI_REGISTERS *AhciRegisters\r
1983 )\r
1984{\r
1985 EFI_STATUS Status;\r
1986 UINTN Bytes;\r
1987 VOID *Buffer;\r
1988\r
1989 UINT32 Capability;\r
1990 UINT32 PortImplementBitMap;\r
1991 UINT8 MaxPortNumber;\r
1992 UINT8 MaxCommandSlotNumber;\r
1993 BOOLEAN Support64Bit;\r
1994 UINT64 MaxReceiveFisSize;\r
1995 UINT64 MaxCommandListSize;\r
1996 UINT64 MaxCommandTableSize;\r
1997 EFI_PHYSICAL_ADDRESS AhciRFisPciAddr;\r
1998 EFI_PHYSICAL_ADDRESS AhciCmdListPciAddr;\r
1999 EFI_PHYSICAL_ADDRESS AhciCommandTablePciAddr;\r
2000\r
2001 Buffer = NULL;\r
2002 //\r
2003 // Collect AHCI controller information\r
2004 //\r
2005 Capability = AhciReadReg(PciIo, EFI_AHCI_CAPABILITY_OFFSET);\r
2006 //\r
2007 // Get the number of command slots per port supported by this HBA.\r
2008 //\r
2009 MaxCommandSlotNumber = (UINT8) (((Capability & 0x1F00) >> 8) + 1);\r
2010 Support64Bit = (BOOLEAN) (((Capability & BIT31) != 0) ? TRUE : FALSE);\r
2011 \r
2012 PortImplementBitMap = AhciReadReg(PciIo, EFI_AHCI_PI_OFFSET);\r
2013 //\r
2014 // Get the highest bit of implemented ports which decides how many bytes are allocated for recived FIS.\r
2015 //\r
2016 MaxPortNumber = (UINT8)(UINTN)(HighBitSet32(PortImplementBitMap) + 1);\r
2017 if (MaxPortNumber == 0) {\r
2018 return EFI_DEVICE_ERROR;\r
2019 }\r
2020\r
2021 MaxReceiveFisSize = MaxPortNumber * sizeof (EFI_AHCI_RECEIVED_FIS);\r
2022 Status = PciIo->AllocateBuffer (\r
2023 PciIo,\r
2024 AllocateAnyPages,\r
2025 EfiBootServicesData,\r
2026 EFI_SIZE_TO_PAGES ((UINTN) MaxReceiveFisSize),\r
2027 &Buffer,\r
2028 0\r
2029 );\r
2030\r
2031 if (EFI_ERROR (Status)) {\r
2032 return EFI_OUT_OF_RESOURCES;\r
2033 }\r
2034\r
2035 ZeroMem (Buffer, (UINTN)MaxReceiveFisSize);\r
2036\r
2037 AhciRegisters->AhciRFis = Buffer;\r
2038 AhciRegisters->MaxReceiveFisSize = MaxReceiveFisSize;\r
2039 Bytes = (UINTN)MaxReceiveFisSize;\r
2040\r
2041 Status = PciIo->Map (\r
2042 PciIo,\r
2043 EfiPciIoOperationBusMasterCommonBuffer,\r
2044 Buffer,\r
2045 &Bytes,\r
2046 &AhciRFisPciAddr,\r
2047 &AhciRegisters->MapRFis\r
2048 );\r
2049\r
2050 if (EFI_ERROR (Status) || (Bytes != MaxReceiveFisSize)) {\r
2051 //\r
2052 // Map error or unable to map the whole RFis buffer into a contiguous region.\r
2053 //\r
2054 Status = EFI_OUT_OF_RESOURCES;\r
2055 goto Error6;\r
2056 }\r
2057\r
2058 if ((!Support64Bit) && (AhciRFisPciAddr > 0x100000000ULL)) {\r
2059 //\r
2060 // The AHCI HBA doesn't support 64bit addressing, so should not get a >4G pci bus master address.\r
2061 //\r
2062 Status = EFI_DEVICE_ERROR;\r
2063 goto Error5;\r
2064 }\r
2065 AhciRegisters->AhciRFisPciAddr = (EFI_AHCI_RECEIVED_FIS *)(UINTN)AhciRFisPciAddr;\r
2066\r
2067 //\r
2068 // Allocate memory for command list\r
2069 // Note that the implemenation is a single task model which only use a command list for all ports.\r
2070 //\r
2071 Buffer = NULL;\r
2072 MaxCommandListSize = MaxCommandSlotNumber * sizeof (EFI_AHCI_COMMAND_LIST);\r
2073 Status = PciIo->AllocateBuffer (\r
2074 PciIo,\r
2075 AllocateAnyPages,\r
2076 EfiBootServicesData,\r
2077 EFI_SIZE_TO_PAGES ((UINTN) MaxCommandListSize),\r
2078 &Buffer,\r
2079 0\r
2080 );\r
2081\r
2082 if (EFI_ERROR (Status)) {\r
2083 //\r
2084 // Free mapped resource.\r
2085 //\r
2086 Status = EFI_OUT_OF_RESOURCES;\r
2087 goto Error5;\r
2088 }\r
2089\r
2090 ZeroMem (Buffer, (UINTN)MaxCommandListSize);\r
2091\r
2092 AhciRegisters->AhciCmdList = Buffer;\r
2093 AhciRegisters->MaxCommandListSize = MaxCommandListSize;\r
2094 Bytes = (UINTN)MaxCommandListSize;\r
2095\r
2096 Status = PciIo->Map (\r
2097 PciIo,\r
2098 EfiPciIoOperationBusMasterCommonBuffer,\r
2099 Buffer,\r
2100 &Bytes,\r
2101 &AhciCmdListPciAddr,\r
2102 &AhciRegisters->MapCmdList\r
2103 );\r
2104\r
2105 if (EFI_ERROR (Status) || (Bytes != MaxCommandListSize)) {\r
2106 //\r
2107 // Map error or unable to map the whole cmd list buffer into a contiguous region.\r
2108 //\r
2109 Status = EFI_OUT_OF_RESOURCES;\r
2110 goto Error4;\r
2111 }\r
2112\r
2113 if ((!Support64Bit) && (AhciCmdListPciAddr > 0x100000000ULL)) {\r
2114 //\r
2115 // The AHCI HBA doesn't support 64bit addressing, so should not get a >4G pci bus master address.\r
2116 //\r
2117 Status = EFI_DEVICE_ERROR;\r
2118 goto Error3;\r
2119 }\r
2120 AhciRegisters->AhciCmdListPciAddr = (EFI_AHCI_COMMAND_LIST *)(UINTN)AhciCmdListPciAddr;\r
2121\r
2122 //\r
2123 // Allocate memory for command table\r
2124 // According to AHCI 1.3 spec, a PRD table can contain maximum 65535 entries.\r
2125 //\r
2126 Buffer = NULL;\r
2127 MaxCommandTableSize = sizeof (EFI_AHCI_COMMAND_TABLE);\r
2128\r
2129 Status = PciIo->AllocateBuffer (\r
2130 PciIo,\r
2131 AllocateAnyPages,\r
2132 EfiBootServicesData,\r
2133 EFI_SIZE_TO_PAGES ((UINTN) MaxCommandTableSize),\r
2134 &Buffer,\r
2135 0\r
2136 );\r
2137\r
2138 if (EFI_ERROR (Status)) {\r
2139 //\r
2140 // Free mapped resource.\r
2141 //\r
2142 Status = EFI_OUT_OF_RESOURCES;\r
2143 goto Error3;\r
2144 }\r
2145\r
2146 ZeroMem (Buffer, (UINTN)MaxCommandTableSize);\r
2147\r
2148 AhciRegisters->AhciCommandTable = Buffer;\r
2149 AhciRegisters->MaxCommandTableSize = MaxCommandTableSize;\r
2150 Bytes = (UINTN)MaxCommandTableSize;\r
2151\r
2152 Status = PciIo->Map (\r
2153 PciIo,\r
2154 EfiPciIoOperationBusMasterCommonBuffer,\r
2155 Buffer,\r
2156 &Bytes,\r
2157 &AhciCommandTablePciAddr,\r
2158 &AhciRegisters->MapCommandTable\r
2159 );\r
2160\r
2161 if (EFI_ERROR (Status) || (Bytes != MaxCommandTableSize)) {\r
2162 //\r
2163 // Map error or unable to map the whole cmd list buffer into a contiguous region.\r
2164 //\r
2165 Status = EFI_OUT_OF_RESOURCES;\r
2166 goto Error2;\r
2167 }\r
2168\r
2169 if ((!Support64Bit) && (AhciCommandTablePciAddr > 0x100000000ULL)) {\r
2170 //\r
2171 // The AHCI HBA doesn't support 64bit addressing, so should not get a >4G pci bus master address.\r
2172 //\r
2173 Status = EFI_DEVICE_ERROR;\r
2174 goto Error1;\r
2175 }\r
2176 AhciRegisters->AhciCommandTablePciAddr = (EFI_AHCI_COMMAND_TABLE *)(UINTN)AhciCommandTablePciAddr;\r
2177\r
2178 return EFI_SUCCESS;\r
2179 //\r
2180 // Map error or unable to map the whole CmdList buffer into a contiguous region.\r
2181 //\r
2182Error1:\r
2183 PciIo->Unmap (\r
2184 PciIo,\r
2185 AhciRegisters->MapCommandTable\r
2186 );\r
2187Error2:\r
2188 PciIo->FreeBuffer (\r
2189 PciIo,\r
2190 EFI_SIZE_TO_PAGES ((UINTN) MaxCommandTableSize),\r
2191 AhciRegisters->AhciCommandTable\r
2192 );\r
2193Error3:\r
2194 PciIo->Unmap (\r
2195 PciIo,\r
2196 AhciRegisters->MapCmdList\r
2197 );\r
2198Error4:\r
2199 PciIo->FreeBuffer (\r
2200 PciIo,\r
2201 EFI_SIZE_TO_PAGES ((UINTN) MaxCommandListSize),\r
2202 AhciRegisters->AhciCmdList\r
2203 );\r
2204Error5:\r
2205 PciIo->Unmap (\r
2206 PciIo,\r
2207 AhciRegisters->MapRFis\r
2208 );\r
2209Error6:\r
2210 PciIo->FreeBuffer (\r
2211 PciIo,\r
2212 EFI_SIZE_TO_PAGES ((UINTN) MaxReceiveFisSize),\r
2213 AhciRegisters->AhciRFis\r
2214 );\r
2215\r
2216 return Status;\r
2217}\r
2218\r
2219/**\r
2220 Initialize ATA host controller at AHCI mode.\r
2221\r
2222 The function is designed to initialize ATA host controller.\r
2223\r
2224 @param[in] Instance A pointer to the ATA_ATAPI_PASS_THRU_INSTANCE instance.\r
2225\r
2226**/\r
2227EFI_STATUS\r
2228EFIAPI\r
2229AhciModeInitialization (\r
2230 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance\r
2231 )\r
2232{\r
2233 EFI_STATUS Status;\r
2234 EFI_PCI_IO_PROTOCOL *PciIo;\r
2235 EFI_IDE_CONTROLLER_INIT_PROTOCOL *IdeInit;\r
2236 UINT32 Capability;\r
2237 UINT8 MaxPortNumber;\r
2238 UINT32 PortImplementBitMap;\r
2239\r
2240 EFI_AHCI_REGISTERS *AhciRegisters;\r
2241\r
2242 UINT8 Port;\r
2243 DATA_64 Data64;\r
2244 UINT32 Offset;\r
2245 UINT32 Data;\r
2246 EFI_IDENTIFY_DATA Buffer;\r
2247 EFI_ATA_DEVICE_TYPE DeviceType;\r
2248 EFI_ATA_COLLECTIVE_MODE *SupportedModes;\r
2249 EFI_ATA_TRANSFER_MODE TransferMode;\r
2250 UINT32 PhyDetectDelay;\r
2251 UINT32 Value;\r
2252\r
2253 if (Instance == NULL) {\r
2254 return EFI_INVALID_PARAMETER;\r
2255 }\r
2256\r
2257 PciIo = Instance->PciIo;\r
2258 IdeInit = Instance->IdeControllerInit;\r
2259\r
2260 Status = AhciReset (PciIo, EFI_AHCI_BUS_RESET_TIMEOUT);\r
2261\r
2262 if (EFI_ERROR (Status)) {\r
2263 return EFI_DEVICE_ERROR;\r
2264 }\r
2265\r
2266 //\r
2267 // Collect AHCI controller information\r
2268 //\r
2269 Capability = AhciReadReg (PciIo, EFI_AHCI_CAPABILITY_OFFSET);\r
2270\r
2271 //\r
2272 // Make sure that GHC.AE bit is set before accessing any AHCI registers.\r
2273 //\r
2274 Value = AhciReadReg(PciIo, EFI_AHCI_GHC_OFFSET);\r
2275\r
2276 if ((Value & EFI_AHCI_GHC_ENABLE) == 0) {\r
2277 AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);\r
2278 }\r
2279\r
2280 //\r
2281 // Enable 64-bit DMA support in the PCI layer if this controller\r
2282 // supports it.\r
2283 //\r
2284 if ((Capability & EFI_AHCI_CAP_S64A) != 0) {\r
2285 Status = PciIo->Attributes (\r
2286 PciIo,\r
2287 EfiPciIoAttributeOperationEnable,\r
2288 EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE,\r
2289 NULL\r
2290 );\r
2291 if (EFI_ERROR (Status)) {\r
2292 DEBUG ((EFI_D_WARN,\r
2293 "AhciModeInitialization: failed to enable 64-bit DMA on 64-bit capable controller (%r)\n",\r
2294 Status));\r
2295 }\r
2296 }\r
2297\r
2298 //\r
2299 // Get the number of command slots per port supported by this HBA.\r
2300 //\r
2301 MaxPortNumber = (UINT8) ((Capability & 0x1F) + 1);\r
2302\r
2303 //\r
2304 // Get the bit map of those ports exposed by this HBA.\r
2305 // It indicates which ports that the HBA supports are available for software to use.\r
2306 //\r
2307 PortImplementBitMap = AhciReadReg(PciIo, EFI_AHCI_PI_OFFSET);\r
2308\r
2309 AhciRegisters = &Instance->AhciRegisters;\r
2310 Status = AhciCreateTransferDescriptor (PciIo, AhciRegisters);\r
2311\r
2312 if (EFI_ERROR (Status)) {\r
2313 return EFI_OUT_OF_RESOURCES;\r
2314 }\r
2315\r
2316 for (Port = 0; Port < EFI_AHCI_MAX_PORTS; Port ++) {\r
2317 if ((PortImplementBitMap & (BIT0 << Port)) != 0) {\r
2318 //\r
2319 // According to AHCI spec, MaxPortNumber should be equal or greater than the number of implemented ports.\r
2320 //\r
2321 if ((MaxPortNumber--) == 0) {\r
2322 //\r
2323 // Should never be here.\r
2324 //\r
2325 ASSERT (FALSE);\r
2326 return EFI_SUCCESS;\r
2327 }\r
2328\r
2329 IdeInit->NotifyPhase (IdeInit, EfiIdeBeforeChannelEnumeration, Port);\r
2330\r
2331 //\r
2332 // Initialize FIS Base Address Register and Command List Base Address Register for use.\r
2333 //\r
2334 Data64.Uint64 = (UINTN) (AhciRegisters->AhciRFisPciAddr) + sizeof (EFI_AHCI_RECEIVED_FIS) * Port;\r
2335 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_FB;\r
2336 AhciWriteReg (PciIo, Offset, Data64.Uint32.Lower32);\r
2337 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_FBU;\r
2338 AhciWriteReg (PciIo, Offset, Data64.Uint32.Upper32);\r
2339\r
2340 Data64.Uint64 = (UINTN) (AhciRegisters->AhciCmdListPciAddr);\r
2341 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CLB;\r
2342 AhciWriteReg (PciIo, Offset, Data64.Uint32.Lower32);\r
2343 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CLBU;\r
2344 AhciWriteReg (PciIo, Offset, Data64.Uint32.Upper32);\r
2345\r
2346 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;\r
2347 Data = AhciReadReg (PciIo, Offset);\r
2348 if ((Data & EFI_AHCI_PORT_CMD_CPD) != 0) {\r
2349 AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_POD);\r
2350 }\r
2351\r
2352 if ((Capability & EFI_AHCI_CAP_SSS) != 0) {\r
2353 AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_SUD);\r
2354 }\r
2355\r
2356 //\r
2357 // Disable aggressive power management.\r
2358 //\r
2359 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SCTL;\r
2360 AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_SCTL_IPM_INIT);\r
2361 //\r
2362 // Disable the reporting of the corresponding interrupt to system software.\r
2363 //\r
2364 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_IE;\r
2365 AhciAndReg (PciIo, Offset, 0);\r
2366\r
2367 //\r
2368 // Now inform the IDE Controller Init Module.\r
2369 //\r
2370 IdeInit->NotifyPhase (IdeInit, EfiIdeBusBeforeDevicePresenceDetection, Port);\r
2371\r
2372 //\r
2373 // Enable FIS Receive DMA engine for the first D2H FIS.\r
2374 //\r
2375 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;\r
2376 AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_FRE);\r
2377\r
2378 //\r
2379 // Wait no longer than 10 ms to wait the Phy to detect the presence of a device.\r
2380 // It's the requirment from SATA1.0a spec section 5.2.\r
2381 //\r
2382 PhyDetectDelay = EFI_AHCI_BUS_PHY_DETECT_TIMEOUT;\r
2383 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SSTS;\r
2384 do {\r
2385 Data = AhciReadReg (PciIo, Offset) & EFI_AHCI_PORT_SSTS_DET_MASK;\r
2386 if ((Data == EFI_AHCI_PORT_SSTS_DET_PCE) || (Data == EFI_AHCI_PORT_SSTS_DET)) {\r
2387 break;\r
2388 }\r
2389\r
2390 MicroSecondDelay (1000);\r
2391 PhyDetectDelay--;\r
2392 } while (PhyDetectDelay > 0);\r
2393\r
2394 if (PhyDetectDelay == 0) {\r
2395 //\r
2396 // No device detected at this port.\r
2397 // Clear PxCMD.SUD for those ports at which there are no device present.\r
2398 //\r
2399 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;\r
2400 AhciAndReg (PciIo, Offset, (UINT32) ~(EFI_AHCI_PORT_CMD_SUD));\r
2401 continue;\r
2402 }\r
2403\r
2404 //\r
2405 // According to SATA1.0a spec section 5.2, we need to wait for PxTFD.BSY and PxTFD.DRQ\r
2406 // and PxTFD.ERR to be zero. The maximum wait time is 16s which is defined at ATA spec.\r
2407 //\r
2408 PhyDetectDelay = 16 * 1000;\r
2409 do {\r
2410 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SERR;\r
2411 if (AhciReadReg(PciIo, Offset) != 0) {\r
2412 AhciWriteReg (PciIo, Offset, AhciReadReg(PciIo, Offset));\r
2413 }\r
2414 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;\r
2415\r
2416 Data = AhciReadReg (PciIo, Offset) & EFI_AHCI_PORT_TFD_MASK;\r
2417 if (Data == 0) {\r
2418 break;\r
2419 }\r
2420\r
2421 MicroSecondDelay (1000);\r
2422 PhyDetectDelay--;\r
2423 } while (PhyDetectDelay > 0);\r
2424\r
2425 if (PhyDetectDelay == 0) {\r
2426 DEBUG ((EFI_D_ERROR, "Port %d Device presence detected but phy not ready (TFD=0x%X)\n", Port, Data));\r
2427 continue;\r
2428 }\r
2429\r
2430 //\r
2431 // When the first D2H register FIS is received, the content of PxSIG register is updated.\r
2432 //\r
2433 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SIG;\r
2434 Status = AhciWaitMmioSet (\r
2435 PciIo,\r
2436 Offset,\r
2437 0x0000FFFF,\r
2438 0x00000101,\r
2439 EFI_TIMER_PERIOD_SECONDS(16)\r
2440 );\r
2441 if (EFI_ERROR (Status)) {\r
2442 continue;\r
2443 }\r
2444\r
2445 Data = AhciReadReg (PciIo, Offset);\r
2446 if ((Data & EFI_AHCI_ATAPI_SIG_MASK) == EFI_AHCI_ATAPI_DEVICE_SIG) {\r
2447 Status = AhciIdentifyPacket (PciIo, AhciRegisters, Port, 0, &Buffer);\r
2448\r
2449 if (EFI_ERROR (Status)) {\r
2450 continue;\r
2451 }\r
2452\r
2453 DeviceType = EfiIdeCdrom;\r
2454 } else if ((Data & EFI_AHCI_ATAPI_SIG_MASK) == EFI_AHCI_ATA_DEVICE_SIG) {\r
2455 Status = AhciIdentify (PciIo, AhciRegisters, Port, 0, &Buffer);\r
2456\r
2457 if (EFI_ERROR (Status)) {\r
2458 REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_EC_NOT_DETECTED));\r
2459 continue;\r
2460 }\r
2461\r
2462 DeviceType = EfiIdeHarddisk;\r
2463 } else {\r
2464 continue;\r
2465 }\r
2466 DEBUG ((EFI_D_INFO, "port [%d] port mulitplier [%d] has a [%a]\n",\r
2467 Port, 0, DeviceType == EfiIdeCdrom ? "cdrom" : "harddisk"));\r
2468\r
2469 //\r
2470 // If the device is a hard disk, then try to enable S.M.A.R.T feature\r
2471 //\r
2472 if ((DeviceType == EfiIdeHarddisk) && PcdGetBool (PcdAtaSmartEnable)) {\r
2473 AhciAtaSmartSupport (\r
2474 PciIo,\r
2475 AhciRegisters,\r
2476 Port,\r
2477 0,\r
2478 &Buffer,\r
2479 NULL\r
2480 );\r
2481 }\r
2482\r
2483 //\r
2484 // Submit identify data to IDE controller init driver\r
2485 //\r
2486 IdeInit->SubmitData (IdeInit, Port, 0, &Buffer);\r
2487\r
2488 //\r
2489 // Now start to config ide device parameter and transfer mode.\r
2490 //\r
2491 Status = IdeInit->CalculateMode (\r
2492 IdeInit,\r
2493 Port,\r
2494 0,\r
2495 &SupportedModes\r
2496 );\r
2497 if (EFI_ERROR (Status)) {\r
2498 DEBUG ((EFI_D_ERROR, "Calculate Mode Fail, Status = %r\n", Status));\r
2499 continue;\r
2500 }\r
2501\r
2502 //\r
2503 // Set best supported PIO mode on this IDE device\r
2504 //\r
2505 if (SupportedModes->PioMode.Mode <= EfiAtaPioMode2) {\r
2506 TransferMode.ModeCategory = EFI_ATA_MODE_DEFAULT_PIO;\r
2507 } else {\r
2508 TransferMode.ModeCategory = EFI_ATA_MODE_FLOW_PIO;\r
2509 }\r
2510\r
2511 TransferMode.ModeNumber = (UINT8) (SupportedModes->PioMode.Mode);\r
2512\r
2513 //\r
2514 // Set supported DMA mode on this IDE device. Note that UDMA & MDMA cann't\r
2515 // be set together. Only one DMA mode can be set to a device. If setting\r
2516 // DMA mode operation fails, we can continue moving on because we only use\r
2517 // PIO mode at boot time. DMA modes are used by certain kind of OS booting\r
2518 //\r
2519 if (SupportedModes->UdmaMode.Valid) {\r
2520 TransferMode.ModeCategory = EFI_ATA_MODE_UDMA;\r
2521 TransferMode.ModeNumber = (UINT8) (SupportedModes->UdmaMode.Mode);\r
2522 } else if (SupportedModes->MultiWordDmaMode.Valid) {\r
2523 TransferMode.ModeCategory = EFI_ATA_MODE_MDMA;\r
2524 TransferMode.ModeNumber = (UINT8) SupportedModes->MultiWordDmaMode.Mode;\r
2525 }\r
2526\r
2527 Status = AhciDeviceSetFeature (PciIo, AhciRegisters, Port, 0, 0x03, (UINT32)(*(UINT8 *)&TransferMode));\r
2528 if (EFI_ERROR (Status)) {\r
2529 DEBUG ((EFI_D_ERROR, "Set transfer Mode Fail, Status = %r\n", Status));\r
2530 continue;\r
2531 }\r
2532\r
2533 //\r
2534 // Found a ATA or ATAPI device, add it into the device list.\r
2535 //\r
2536 CreateNewDeviceInfo (Instance, Port, 0xFFFF, DeviceType, &Buffer);\r
2537 if (DeviceType == EfiIdeHarddisk) {\r
2538 REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_PC_ENABLE));\r
2539 }\r
2540 }\r
2541 }\r
2542\r
2543 return EFI_SUCCESS;\r
2544}\r
2545\r
EFI Development Kit II mirror for PVE