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1/** @file\r
2\r
3 XHCI transfer scheduling routines.\r
4\r
5Copyright (c) 2011 - 2013, Intel Corporation. All rights reserved.<BR>\r
6This program and the accompanying materials\r
7are licensed and made available under the terms and conditions of the BSD License\r
8which accompanies this distribution. The full text of the license may be found at\r
9http://opensource.org/licenses/bsd-license.php\r
10\r
11THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15\r
16#include "Xhci.h"\r
17\r
18/**\r
19 Create a command transfer TRB to support XHCI command interfaces.\r
20\r
21 @param Xhc The XHCI Instance.\r
22 @param CmdTrb The cmd TRB to be executed.\r
23\r
24 @return Created URB or NULL.\r
25\r
26**/\r
27URB*\r
28XhcCreateCmdTrb (\r
29 IN USB_XHCI_INSTANCE *Xhc,\r
30 IN TRB_TEMPLATE *CmdTrb\r
31 )\r
32{\r
33 URB *Urb;\r
34\r
35 Urb = AllocateZeroPool (sizeof (URB));\r
36 if (Urb == NULL) {\r
37 return NULL;\r
38 }\r
39\r
40 Urb->Signature = XHC_URB_SIG;\r
41\r
42 Urb->Ring = &Xhc->CmdRing;\r
43 XhcSyncTrsRing (Xhc, Urb->Ring);\r
44 Urb->TrbNum = 1;\r
45 Urb->TrbStart = Urb->Ring->RingEnqueue;\r
46 CopyMem (Urb->TrbStart, CmdTrb, sizeof (TRB_TEMPLATE));\r
47 Urb->TrbStart->CycleBit = Urb->Ring->RingPCS & BIT0;\r
48 Urb->TrbEnd = Urb->TrbStart;\r
49\r
50 return Urb;\r
51}\r
52\r
53/**\r
54 Execute a XHCI cmd TRB pointed by CmdTrb.\r
55\r
56 @param Xhc The XHCI Instance.\r
57 @param CmdTrb The cmd TRB to be executed.\r
58 @param Timeout Indicates the maximum time, in millisecond, which the\r
59 transfer is allowed to complete.\r
60 @param EvtTrb The event TRB corresponding to the cmd TRB.\r
61\r
62 @retval EFI_SUCCESS The transfer was completed successfully.\r
63 @retval EFI_INVALID_PARAMETER Some parameters are invalid.\r
64 @retval EFI_TIMEOUT The transfer failed due to timeout.\r
65 @retval EFI_DEVICE_ERROR The transfer failed due to host controller error.\r
66\r
67**/\r
68EFI_STATUS\r
69EFIAPI\r
70XhcCmdTransfer (\r
71 IN USB_XHCI_INSTANCE *Xhc,\r
72 IN TRB_TEMPLATE *CmdTrb,\r
73 IN UINTN Timeout,\r
74 OUT TRB_TEMPLATE **EvtTrb\r
75 )\r
76{\r
77 EFI_STATUS Status;\r
78 URB *Urb;\r
79\r
80 //\r
81 // Validate the parameters\r
82 //\r
83 if ((Xhc == NULL) || (CmdTrb == NULL)) {\r
84 return EFI_INVALID_PARAMETER;\r
85 }\r
86\r
87 Status = EFI_DEVICE_ERROR;\r
88\r
89 if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {\r
90 DEBUG ((EFI_D_ERROR, "XhcCmdTransfer: HC is halted\n"));\r
91 goto ON_EXIT;\r
92 }\r
93\r
94 //\r
95 // Create a new URB, then poll the execution status.\r
96 //\r
97 Urb = XhcCreateCmdTrb (Xhc, CmdTrb);\r
98\r
99 if (Urb == NULL) {\r
100 DEBUG ((EFI_D_ERROR, "XhcCmdTransfer: failed to create URB\n"));\r
101 Status = EFI_OUT_OF_RESOURCES;\r
102 goto ON_EXIT;\r
103 }\r
104\r
105 Status = XhcExecTransfer (Xhc, TRUE, Urb, Timeout);\r
106 *EvtTrb = Urb->EvtTrb;\r
107\r
108 if (Urb->Result == EFI_USB_NOERROR) {\r
109 Status = EFI_SUCCESS;\r
110 }\r
111\r
112 FreePool (Urb);\r
113\r
114ON_EXIT:\r
115 return Status;\r
116}\r
117\r
118/**\r
119 Create a new URB for a new transaction.\r
120\r
121 @param Xhc The XHCI Instance\r
122 @param BusAddr The logical device address assigned by UsbBus driver\r
123 @param EpAddr Endpoint addrress\r
124 @param DevSpeed The device speed\r
125 @param MaxPacket The max packet length of the endpoint\r
126 @param Type The transaction type\r
127 @param Request The standard USB request for control transfer\r
128 @param Data The user data to transfer\r
129 @param DataLen The length of data buffer\r
130 @param Callback The function to call when data is transferred\r
131 @param Context The context to the callback\r
132\r
133 @return Created URB or NULL\r
134\r
135**/\r
136URB*\r
137XhcCreateUrb (\r
138 IN USB_XHCI_INSTANCE *Xhc,\r
139 IN UINT8 BusAddr,\r
140 IN UINT8 EpAddr,\r
141 IN UINT8 DevSpeed,\r
142 IN UINTN MaxPacket,\r
143 IN UINTN Type,\r
144 IN EFI_USB_DEVICE_REQUEST *Request,\r
145 IN VOID *Data,\r
146 IN UINTN DataLen,\r
147 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,\r
148 IN VOID *Context\r
149 )\r
150{\r
151 USB_ENDPOINT *Ep;\r
152 EFI_STATUS Status;\r
153 URB *Urb;\r
154\r
155 Urb = AllocateZeroPool (sizeof (URB));\r
156 if (Urb == NULL) {\r
157 return NULL;\r
158 }\r
159\r
160 Urb->Signature = XHC_URB_SIG;\r
161 InitializeListHead (&Urb->UrbList);\r
162\r
163 Ep = &Urb->Ep;\r
164 Ep->BusAddr = BusAddr;\r
165 Ep->EpAddr = (UINT8)(EpAddr & 0x0F);\r
166 Ep->Direction = ((EpAddr & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut;\r
167 Ep->DevSpeed = DevSpeed;\r
168 Ep->MaxPacket = MaxPacket;\r
169 Ep->Type = Type;\r
170\r
171 Urb->Request = Request;\r
172 Urb->Data = Data;\r
173 Urb->DataLen = DataLen;\r
174 Urb->Callback = Callback;\r
175 Urb->Context = Context;\r
176\r
177 Status = XhcCreateTransferTrb (Xhc, Urb);\r
178 ASSERT_EFI_ERROR (Status);\r
179\r
180 return Urb;\r
181}\r
182\r
183/**\r
184 Create a transfer TRB.\r
185\r
186 @param Xhc The XHCI Instance\r
187 @param Urb The urb used to construct the transfer TRB.\r
188\r
189 @return Created TRB or NULL\r
190\r
191**/\r
192EFI_STATUS\r
193XhcCreateTransferTrb (\r
194 IN USB_XHCI_INSTANCE *Xhc,\r
195 IN URB *Urb\r
196 )\r
197{\r
198 VOID *OutputContext;\r
199 TRANSFER_RING *EPRing;\r
200 UINT8 EPType;\r
201 UINT8 SlotId;\r
202 UINT8 Dci;\r
203 TRB *TrbStart;\r
204 UINTN TotalLen;\r
205 UINTN Len;\r
206 UINTN TrbNum;\r
207\r
208 SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);\r
209 if (SlotId == 0) {\r
210 return EFI_DEVICE_ERROR;\r
211 }\r
212\r
213 Urb->Finished = FALSE;\r
214 Urb->StartDone = FALSE;\r
215 Urb->EndDone = FALSE;\r
216 Urb->Completed = 0;\r
217 Urb->Result = EFI_USB_NOERROR;\r
218\r
219 Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));\r
220 ASSERT (Dci < 32);\r
221 EPRing = (TRANSFER_RING *)(UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1];\r
222 Urb->Ring = EPRing;\r
223 OutputContext = (VOID *)(UINTN)Xhc->DCBAA[SlotId];\r
224 if (Xhc->HcCParams.Data.Csz == 0) {\r
225 EPType = (UINT8) ((DEVICE_CONTEXT *)OutputContext)->EP[Dci-1].EPType;\r
226 } else {\r
227 EPType = (UINT8) ((DEVICE_CONTEXT_64 *)OutputContext)->EP[Dci-1].EPType;\r
228 }\r
229\r
230 //\r
231 // Construct the TRB\r
232 //\r
233 XhcSyncTrsRing (Xhc, EPRing);\r
234 Urb->TrbStart = EPRing->RingEnqueue;\r
235 switch (EPType) {\r
236 case ED_CONTROL_BIDIR:\r
237 //\r
238 // For control transfer, create SETUP_STAGE_TRB first.\r
239 //\r
240 TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
241 TrbStart->TrbCtrSetup.bmRequestType = Urb->Request->RequestType;\r
242 TrbStart->TrbCtrSetup.bRequest = Urb->Request->Request;\r
243 TrbStart->TrbCtrSetup.wValue = Urb->Request->Value;\r
244 TrbStart->TrbCtrSetup.wIndex = Urb->Request->Index;\r
245 TrbStart->TrbCtrSetup.wLength = Urb->Request->Length;\r
246 TrbStart->TrbCtrSetup.Lenth = 8;\r
247 TrbStart->TrbCtrSetup.IntTarget = 0;\r
248 TrbStart->TrbCtrSetup.IOC = 1;\r
249 TrbStart->TrbCtrSetup.IDT = 1;\r
250 TrbStart->TrbCtrSetup.Type = TRB_TYPE_SETUP_STAGE;\r
251 if (Urb->Ep.Direction == EfiUsbDataIn) {\r
252 TrbStart->TrbCtrSetup.TRT = 3;\r
253 } else if (Urb->Ep.Direction == EfiUsbDataOut) {\r
254 TrbStart->TrbCtrSetup.TRT = 2;\r
255 } else {\r
256 TrbStart->TrbCtrSetup.TRT = 0;\r
257 }\r
258 //\r
259 // Update the cycle bit\r
260 //\r
261 TrbStart->TrbCtrSetup.CycleBit = EPRing->RingPCS & BIT0;\r
262 Urb->TrbNum++;\r
263\r
264 //\r
265 // For control transfer, create DATA_STAGE_TRB.\r
266 //\r
267 if (Urb->DataLen > 0) {\r
268 XhcSyncTrsRing (Xhc, EPRing);\r
269 TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
270 TrbStart->TrbCtrData.TRBPtrLo = XHC_LOW_32BIT(Urb->Data);\r
271 TrbStart->TrbCtrData.TRBPtrHi = XHC_HIGH_32BIT(Urb->Data);\r
272 TrbStart->TrbCtrData.Lenth = (UINT32) Urb->DataLen;\r
273 TrbStart->TrbCtrData.TDSize = 0;\r
274 TrbStart->TrbCtrData.IntTarget = 0;\r
275 TrbStart->TrbCtrData.ISP = 1;\r
276 TrbStart->TrbCtrData.IOC = 1;\r
277 TrbStart->TrbCtrData.IDT = 0;\r
278 TrbStart->TrbCtrData.CH = 0;\r
279 TrbStart->TrbCtrData.Type = TRB_TYPE_DATA_STAGE;\r
280 if (Urb->Ep.Direction == EfiUsbDataIn) {\r
281 TrbStart->TrbCtrData.DIR = 1;\r
282 } else if (Urb->Ep.Direction == EfiUsbDataOut) {\r
283 TrbStart->TrbCtrData.DIR = 0;\r
284 } else {\r
285 TrbStart->TrbCtrData.DIR = 0;\r
286 }\r
287 //\r
288 // Update the cycle bit\r
289 //\r
290 TrbStart->TrbCtrData.CycleBit = EPRing->RingPCS & BIT0;\r
291 Urb->TrbNum++;\r
292 }\r
293 //\r
294 // For control transfer, create STATUS_STAGE_TRB.\r
295 // Get the pointer to next TRB for status stage use\r
296 //\r
297 XhcSyncTrsRing (Xhc, EPRing);\r
298 TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
299 TrbStart->TrbCtrStatus.IntTarget = 0;\r
300 TrbStart->TrbCtrStatus.IOC = 1;\r
301 TrbStart->TrbCtrStatus.CH = 0;\r
302 TrbStart->TrbCtrStatus.Type = TRB_TYPE_STATUS_STAGE;\r
303 if (Urb->Ep.Direction == EfiUsbDataIn) {\r
304 TrbStart->TrbCtrStatus.DIR = 0;\r
305 } else if (Urb->Ep.Direction == EfiUsbDataOut) {\r
306 TrbStart->TrbCtrStatus.DIR = 1;\r
307 } else {\r
308 TrbStart->TrbCtrStatus.DIR = 0;\r
309 }\r
310 //\r
311 // Update the cycle bit\r
312 //\r
313 TrbStart->TrbCtrStatus.CycleBit = EPRing->RingPCS & BIT0;\r
314 //\r
315 // Update the enqueue pointer\r
316 //\r
317 XhcSyncTrsRing (Xhc, EPRing);\r
318 Urb->TrbNum++;\r
319 Urb->TrbEnd = (TRB_TEMPLATE *)(UINTN)TrbStart;\r
320\r
321 break;\r
322\r
323 case ED_BULK_OUT:\r
324 case ED_BULK_IN:\r
325 TotalLen = 0;\r
326 Len = 0;\r
327 TrbNum = 0;\r
328 TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
329 while (TotalLen < Urb->DataLen) {\r
330 if ((TotalLen + 0x10000) >= Urb->DataLen) {\r
331 Len = Urb->DataLen - TotalLen;\r
332 } else {\r
333 Len = 0x10000;\r
334 }\r
335 TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
336 TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->Data + TotalLen);\r
337 TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->Data + TotalLen);\r
338 TrbStart->TrbNormal.Lenth = (UINT32) Len;\r
339 TrbStart->TrbNormal.TDSize = 0;\r
340 TrbStart->TrbNormal.IntTarget = 0;\r
341 TrbStart->TrbNormal.ISP = 1;\r
342 TrbStart->TrbNormal.IOC = 1;\r
343 TrbStart->TrbNormal.Type = TRB_TYPE_NORMAL;\r
344 //\r
345 // Update the cycle bit\r
346 //\r
347 TrbStart->TrbNormal.CycleBit = EPRing->RingPCS & BIT0;\r
348\r
349 XhcSyncTrsRing (Xhc, EPRing);\r
350 TrbNum++;\r
351 TotalLen += Len;\r
352 }\r
353\r
354 Urb->TrbNum = TrbNum;\r
355 Urb->TrbEnd = (TRB_TEMPLATE *)(UINTN)TrbStart;\r
356 break;\r
357\r
358 case ED_INTERRUPT_OUT:\r
359 case ED_INTERRUPT_IN:\r
360 TotalLen = 0;\r
361 Len = 0;\r
362 TrbNum = 0;\r
363 TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
364 while (TotalLen < Urb->DataLen) {\r
365 if ((TotalLen + 0x10000) >= Urb->DataLen) {\r
366 Len = Urb->DataLen - TotalLen;\r
367 } else {\r
368 Len = 0x10000;\r
369 }\r
370 TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
371 TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->Data + TotalLen);\r
372 TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->Data + TotalLen);\r
373 TrbStart->TrbNormal.Lenth = (UINT32) Len;\r
374 TrbStart->TrbNormal.TDSize = 0;\r
375 TrbStart->TrbNormal.IntTarget = 0;\r
376 TrbStart->TrbNormal.ISP = 1;\r
377 TrbStart->TrbNormal.IOC = 1;\r
378 TrbStart->TrbNormal.Type = TRB_TYPE_NORMAL;\r
379 //\r
380 // Update the cycle bit\r
381 //\r
382 TrbStart->TrbNormal.CycleBit = EPRing->RingPCS & BIT0;\r
383\r
384 XhcSyncTrsRing (Xhc, EPRing);\r
385 TrbNum++;\r
386 TotalLen += Len;\r
387 }\r
388\r
389 Urb->TrbNum = TrbNum;\r
390 Urb->TrbEnd = (TRB_TEMPLATE *)(UINTN)TrbStart;\r
391 break;\r
392\r
393 default:\r
394 DEBUG ((EFI_D_INFO, "Not supported EPType 0x%x!\n",EPType));\r
395 ASSERT (FALSE);\r
396 break;\r
397 }\r
398\r
399 return EFI_SUCCESS;\r
400}\r
401\r
402\r
403/**\r
404 Initialize the XHCI host controller for schedule.\r
405\r
406 @param Xhc The XHCI Instance to be initialized.\r
407\r
408**/\r
409VOID\r
410XhcInitSched (\r
411 IN USB_XHCI_INSTANCE *Xhc\r
412 )\r
413{\r
414 VOID *Dcbaa;\r
415 UINT64 CmdRing;\r
416 UINTN Entries;\r
417 UINT32 MaxScratchpadBufs;\r
418 UINT64 *ScratchBuf;\r
419 UINT64 *ScratchEntryBuf;\r
420 UINT32 Index;\r
421\r
422 //\r
423 // Program the Max Device Slots Enabled (MaxSlotsEn) field in the CONFIG register (5.4.7)\r
424 // to enable the device slots that system software is going to use.\r
425 //\r
426 Xhc->MaxSlotsEn = Xhc->HcSParams1.Data.MaxSlots;\r
427 ASSERT (Xhc->MaxSlotsEn >= 1 && Xhc->MaxSlotsEn <= 255);\r
428 XhcWriteOpReg (Xhc, XHC_CONFIG_OFFSET, Xhc->MaxSlotsEn);\r
429\r
430 //\r
431 // The Device Context Base Address Array entry associated with each allocated Device Slot\r
432 // shall contain a 64-bit pointer to the base of the associated Device Context.\r
433 // The Device Context Base Address Array shall contain MaxSlotsEn + 1 entries.\r
434 // Software shall set Device Context Base Address Array entries for unallocated Device Slots to '0'.\r
435 //\r
436 Entries = (Xhc->MaxSlotsEn + 1) * sizeof(UINT64);\r
437 Dcbaa = AllocatePages (EFI_SIZE_TO_PAGES (Entries));\r
438 ASSERT (Dcbaa != NULL);\r
439 ZeroMem (Dcbaa, Entries);\r
440\r
441 //\r
442 // A Scratchpad Buffer is a PAGESIZE block of system memory located on a PAGESIZE boundary.\r
443 // System software shall allocate the Scratchpad Buffer(s) before placing the xHC in to Run\r
444 // mode (Run/Stop(R/S) ='1').\r
445 //\r
446 MaxScratchpadBufs = ((Xhc->HcSParams2.Data.ScratchBufHi) << 5) | (Xhc->HcSParams2.Data.ScratchBufLo);\r
447 Xhc->MaxScratchpadBufs = MaxScratchpadBufs;\r
448 ASSERT (MaxScratchpadBufs <= 1023);\r
449 if (MaxScratchpadBufs != 0) {\r
450 ScratchBuf = AllocateAlignedPages (EFI_SIZE_TO_PAGES (MaxScratchpadBufs * sizeof (UINT64)), Xhc->PageSize);\r
451 ASSERT (ScratchBuf != NULL);\r
452 ZeroMem (ScratchBuf, MaxScratchpadBufs * sizeof (UINT64));\r
453 Xhc->ScratchBuf = ScratchBuf;\r
454\r
455 for (Index = 0; Index < MaxScratchpadBufs; Index++) {\r
456 ScratchEntryBuf = AllocateAlignedPages (EFI_SIZE_TO_PAGES (Xhc->PageSize), Xhc->PageSize);\r
457 ASSERT (ScratchEntryBuf != NULL);\r
458 ZeroMem (ScratchEntryBuf, Xhc->PageSize);\r
459 *ScratchBuf++ = (UINT64)(UINTN)ScratchEntryBuf;\r
460 }\r
461\r
462 //\r
463 // The Scratchpad Buffer Array contains pointers to the Scratchpad Buffers. Entry 0 of the\r
464 // Device Context Base Address Array points to the Scratchpad Buffer Array.\r
465 //\r
466 *(UINT64 *)Dcbaa = (UINT64)(UINTN)Xhc->ScratchBuf;\r
467 }\r
468\r
469 //\r
470 // Program the Device Context Base Address Array Pointer (DCBAAP) register (5.4.6) with\r
471 // a 64-bit address pointing to where the Device Context Base Address Array is located.\r
472 //\r
473 Xhc->DCBAA = (UINT64 *)(UINTN)Dcbaa;\r
474 //\r
475 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,\r
476 // So divide it to two 32-bytes width register access.\r
477 //\r
478 XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT(Xhc->DCBAA));\r
479 XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET + 4, XHC_HIGH_32BIT (Xhc->DCBAA));\r
480 DEBUG ((EFI_D_INFO, "XhcInitSched:DCBAA=0x%x\n", (UINT64)(UINTN)Xhc->DCBAA));\r
481\r
482 //\r
483 // Define the Command Ring Dequeue Pointer by programming the Command Ring Control Register\r
484 // (5.4.5) with a 64-bit address pointing to the starting address of the first TRB of the Command Ring.\r
485 // Note: The Command Ring is 64 byte aligned, so the low order 6 bits of the Command Ring Pointer shall\r
486 // always be '0'.\r
487 //\r
488 CreateTransferRing (Xhc, CMD_RING_TRB_NUMBER, &Xhc->CmdRing);\r
489 //\r
490 // The xHC uses the Enqueue Pointer to determine when a Transfer Ring is empty. As it fetches TRBs from a\r
491 // Transfer Ring it checks for a Cycle bit transition. If a transition detected, the ring is empty.\r
492 // So we set RCS as inverted PCS init value to let Command Ring empty\r
493 //\r
494 CmdRing = (UINT64)(UINTN)Xhc->CmdRing.RingSeg0;\r
495 ASSERT ((CmdRing & 0x3F) == 0);\r
496 CmdRing |= XHC_CRCR_RCS;\r
497 //\r
498 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,\r
499 // So divide it to two 32-bytes width register access.\r
500 //\r
501 XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET, XHC_LOW_32BIT(CmdRing));\r
502 XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET + 4, XHC_HIGH_32BIT (CmdRing));\r
503\r
504 DEBUG ((EFI_D_INFO, "XhcInitSched:XHC_CRCR=0x%x\n", Xhc->CmdRing.RingSeg0));\r
505\r
506 //\r
507 // Disable the 'interrupter enable' bit in USB_CMD\r
508 // and clear IE & IP bit in all Interrupter X Management Registers.\r
509 //\r
510 XhcClearOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_INTE);\r
511 for (Index = 0; Index < (UINT16)(Xhc->HcSParams1.Data.MaxIntrs); Index++) {\r
512 XhcClearRuntimeRegBit (Xhc, XHC_IMAN_OFFSET + (Index * 32), XHC_IMAN_IE);\r
513 XhcSetRuntimeRegBit (Xhc, XHC_IMAN_OFFSET + (Index * 32), XHC_IMAN_IP);\r
514 }\r
515\r
516 //\r
517 // Allocate EventRing for Cmd, Ctrl, Bulk, Interrupt, AsynInterrupt transfer\r
518 //\r
519 CreateEventRing (Xhc, &Xhc->EventRing);\r
520 DEBUG ((EFI_D_INFO, "XhcInitSched:XHC_EVENTRING=0x%x\n", Xhc->EventRing.EventRingSeg0));\r
521}\r
522\r
523/**\r
524 System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted\r
525 condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint\r
526 Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is\r
527 reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the\r
528 Stopped to the Running state.\r
529\r
530 @param Xhc The XHCI Instance.\r
531 @param Urb The urb which makes the endpoint halted.\r
532\r
533 @retval EFI_SUCCESS The recovery is successful.\r
534 @retval Others Failed to recovery halted endpoint.\r
535\r
536**/\r
537EFI_STATUS\r
538EFIAPI\r
539XhcRecoverHaltedEndpoint (\r
540 IN USB_XHCI_INSTANCE *Xhc,\r
541 IN URB *Urb\r
542 )\r
543{\r
544 EFI_STATUS Status;\r
545 EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
546 CMD_TRB_RESET_ENDPOINT CmdTrbResetED;\r
547 CMD_SET_TR_DEQ_POINTER CmdSetTRDeq;\r
548 UINT8 Dci;\r
549 UINT8 SlotId;\r
550\r
551 Status = EFI_SUCCESS;\r
552 SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);\r
553 if (SlotId == 0) {\r
554 return EFI_DEVICE_ERROR;\r
555 }\r
556 Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));\r
557 ASSERT (Dci < 32);\r
558 \r
559 DEBUG ((EFI_D_INFO, "Recovery Halted Slot = %x,Dci = %x\n", SlotId, Dci));\r
560\r
561 //\r
562 // 1) Send Reset endpoint command to transit from halt to stop state\r
563 //\r
564 ZeroMem (&CmdTrbResetED, sizeof (CmdTrbResetED));\r
565 CmdTrbResetED.CycleBit = 1;\r
566 CmdTrbResetED.Type = TRB_TYPE_RESET_ENDPOINT;\r
567 CmdTrbResetED.EDID = Dci;\r
568 CmdTrbResetED.SlotId = SlotId;\r
569 Status = XhcCmdTransfer (\r
570 Xhc,\r
571 (TRB_TEMPLATE *) (UINTN) &CmdTrbResetED,\r
572 XHC_GENERIC_TIMEOUT,\r
573 (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
574 );\r
575 ASSERT (!EFI_ERROR(Status));\r
576\r
577 //\r
578 // 2)Set dequeue pointer\r
579 //\r
580 ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq));\r
581 CmdSetTRDeq.PtrLo = XHC_LOW_32BIT (Urb->Ring->RingEnqueue) | Urb->Ring->RingPCS;\r
582 CmdSetTRDeq.PtrHi = XHC_HIGH_32BIT (Urb->Ring->RingEnqueue);\r
583 CmdSetTRDeq.CycleBit = 1;\r
584 CmdSetTRDeq.Type = TRB_TYPE_SET_TR_DEQUE;\r
585 CmdSetTRDeq.Endpoint = Dci;\r
586 CmdSetTRDeq.SlotId = SlotId;\r
587 Status = XhcCmdTransfer (\r
588 Xhc,\r
589 (TRB_TEMPLATE *) (UINTN) &CmdSetTRDeq,\r
590 XHC_GENERIC_TIMEOUT,\r
591 (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
592 );\r
593 ASSERT (!EFI_ERROR(Status));\r
594\r
595 //\r
596 // 3)Ring the doorbell to transit from stop to active\r
597 //\r
598 XhcRingDoorBell (Xhc, SlotId, Dci);\r
599\r
600 return Status;\r
601}\r
602\r
603/**\r
604 Create XHCI event ring.\r
605\r
606 @param Xhc The XHCI Instance.\r
607 @param EventRing The created event ring.\r
608\r
609**/\r
610VOID\r
611CreateEventRing (\r
612 IN USB_XHCI_INSTANCE *Xhc,\r
613 OUT EVENT_RING *EventRing\r
614 )\r
615{\r
616 VOID *Buf;\r
617 EVENT_RING_SEG_TABLE_ENTRY *ERSTBase;\r
618\r
619 ASSERT (EventRing != NULL);\r
620\r
621 Buf = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER));\r
622 ASSERT (Buf != NULL);\r
623 ASSERT (((UINTN) Buf & 0x3F) == 0);\r
624 ZeroMem (Buf, sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER);\r
625\r
626 EventRing->EventRingSeg0 = Buf;\r
627 EventRing->TrbNumber = EVENT_RING_TRB_NUMBER;\r
628 EventRing->EventRingDequeue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;\r
629 EventRing->EventRingEnqueue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;\r
630 //\r
631 // Software maintains an Event Ring Consumer Cycle State (CCS) bit, initializing it to '1'\r
632 // and toggling it every time the Event Ring Dequeue Pointer wraps back to the beginning of the Event Ring.\r
633 //\r
634 EventRing->EventRingCCS = 1;\r
635\r
636 Buf = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER));\r
637 ASSERT (Buf != NULL);\r
638 ASSERT (((UINTN) Buf & 0x3F) == 0);\r
639 ZeroMem (Buf, sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER);\r
640\r
641 ERSTBase = (EVENT_RING_SEG_TABLE_ENTRY *) Buf;\r
642 EventRing->ERSTBase = ERSTBase;\r
643 ERSTBase->PtrLo = XHC_LOW_32BIT (EventRing->EventRingSeg0);\r
644 ERSTBase->PtrHi = XHC_HIGH_32BIT (EventRing->EventRingSeg0);\r
645 ERSTBase->RingTrbSize = EVENT_RING_TRB_NUMBER;\r
646\r
647 //\r
648 // Program the Interrupter Event Ring Segment Table Size (ERSTSZ) register (5.5.2.3.1)\r
649 //\r
650 XhcWriteRuntimeReg (\r
651 Xhc,\r
652 XHC_ERSTSZ_OFFSET,\r
653 ERST_NUMBER\r
654 );\r
655 //\r
656 // Program the Interrupter Event Ring Dequeue Pointer (ERDP) register (5.5.2.3.3)\r
657 //\r
658 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,\r
659 // So divide it to two 32-bytes width register access.\r
660 //\r
661 XhcWriteRuntimeReg (\r
662 Xhc,\r
663 XHC_ERDP_OFFSET,\r
664 XHC_LOW_32BIT((UINT64)(UINTN)EventRing->EventRingDequeue)\r
665 );\r
666 XhcWriteRuntimeReg (\r
667 Xhc,\r
668 XHC_ERDP_OFFSET + 4,\r
669 XHC_HIGH_32BIT((UINT64)(UINTN)EventRing->EventRingDequeue)\r
670 );\r
671 //\r
672 // Program the Interrupter Event Ring Segment Table Base Address (ERSTBA) register(5.5.2.3.2)\r
673 //\r
674 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,\r
675 // So divide it to two 32-bytes width register access.\r
676 //\r
677 XhcWriteRuntimeReg (\r
678 Xhc,\r
679 XHC_ERSTBA_OFFSET,\r
680 XHC_LOW_32BIT((UINT64)(UINTN)ERSTBase)\r
681 );\r
682 XhcWriteRuntimeReg (\r
683 Xhc,\r
684 XHC_ERSTBA_OFFSET + 4,\r
685 XHC_HIGH_32BIT((UINT64)(UINTN)ERSTBase)\r
686 );\r
687 //\r
688 // Need set IMAN IE bit to enble the ring interrupt\r
689 //\r
690 XhcSetRuntimeRegBit (Xhc, XHC_IMAN_OFFSET, XHC_IMAN_IE);\r
691}\r
692\r
693/**\r
694 Create XHCI transfer ring.\r
695\r
696 @param Xhc The XHCI Instance.\r
697 @param TrbNum The number of TRB in the ring.\r
698 @param TransferRing The created transfer ring.\r
699\r
700**/\r
701VOID\r
702CreateTransferRing (\r
703 IN USB_XHCI_INSTANCE *Xhc,\r
704 IN UINTN TrbNum,\r
705 OUT TRANSFER_RING *TransferRing\r
706 )\r
707{\r
708 VOID *Buf;\r
709 LINK_TRB *EndTrb;\r
710\r
711 Buf = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * TrbNum));\r
712 ASSERT (Buf != NULL);\r
713 ASSERT (((UINTN) Buf & 0x3F) == 0);\r
714 ZeroMem (Buf, sizeof (TRB_TEMPLATE) * TrbNum);\r
715\r
716 TransferRing->RingSeg0 = Buf;\r
717 TransferRing->TrbNumber = TrbNum;\r
718 TransferRing->RingEnqueue = (TRB_TEMPLATE *) TransferRing->RingSeg0;\r
719 TransferRing->RingDequeue = (TRB_TEMPLATE *) TransferRing->RingSeg0;\r
720 TransferRing->RingPCS = 1;\r
721 //\r
722 // 4.9.2 Transfer Ring Management\r
723 // To form a ring (or circular queue) a Link TRB may be inserted at the end of a ring to\r
724 // point to the first TRB in the ring.\r
725 //\r
726 EndTrb = (LINK_TRB *) ((UINTN)Buf + sizeof (TRB_TEMPLATE) * (TrbNum - 1));\r
727 EndTrb->Type = TRB_TYPE_LINK;\r
728 EndTrb->PtrLo = XHC_LOW_32BIT (Buf);\r
729 EndTrb->PtrHi = XHC_HIGH_32BIT (Buf);\r
730 //\r
731 // Toggle Cycle (TC). When set to '1', the xHC shall toggle its interpretation of the Cycle bit.\r
732 //\r
733 EndTrb->TC = 1;\r
734 //\r
735 // Set Cycle bit as other TRB PCS init value\r
736 //\r
737 EndTrb->CycleBit = 0;\r
738}\r
739\r
740/**\r
741 Free XHCI event ring.\r
742\r
743 @param Xhc The XHCI Instance.\r
744 @param EventRing The event ring to be freed.\r
745\r
746**/\r
747EFI_STATUS\r
748EFIAPI\r
749XhcFreeEventRing (\r
750 IN USB_XHCI_INSTANCE *Xhc,\r
751 IN EVENT_RING *EventRing\r
752)\r
753{\r
754 UINT8 Index;\r
755 EVENT_RING_SEG_TABLE_ENTRY *TablePtr;\r
756 VOID *RingBuf;\r
757 EVENT_RING_SEG_TABLE_ENTRY *EventRingPtr;\r
758\r
759 if(EventRing->EventRingSeg0 == NULL) {\r
760 return EFI_SUCCESS;\r
761 }\r
762\r
763 //\r
764 // Get the Event Ring Segment Table base address\r
765 //\r
766 TablePtr = (EVENT_RING_SEG_TABLE_ENTRY *)(EventRing->ERSTBase);\r
767\r
768 //\r
769 // Get all the TRBs Ring and release\r
770 //\r
771 for (Index = 0; Index < ERST_NUMBER; Index++) {\r
772 EventRingPtr = TablePtr + Index;\r
773 RingBuf = (VOID *)(UINTN)(EventRingPtr->PtrLo | LShiftU64 ((UINT64)EventRingPtr->PtrHi, 32));\r
774\r
775 if(RingBuf != NULL) {\r
776 FreePages (RingBuf, EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER));\r
777 ZeroMem (EventRingPtr, sizeof (EVENT_RING_SEG_TABLE_ENTRY));\r
778 }\r
779 }\r
780\r
781 FreePages (TablePtr, EFI_SIZE_TO_PAGES (sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER));\r
782 return EFI_SUCCESS;\r
783}\r
784\r
785/**\r
786 Free the resouce allocated at initializing schedule.\r
787\r
788 @param Xhc The XHCI Instance.\r
789\r
790**/\r
791VOID\r
792XhcFreeSched (\r
793 IN USB_XHCI_INSTANCE *Xhc\r
794 )\r
795{\r
796 UINT32 Index;\r
797 UINT64 *ScratchBuf;\r
798\r
799 if (Xhc->ScratchBuf != NULL) {\r
800 ScratchBuf = Xhc->ScratchBuf;\r
801 for (Index = 0; Index < Xhc->MaxScratchpadBufs; Index++) {\r
802 FreeAlignedPages ((VOID*)(UINTN)*ScratchBuf++, EFI_SIZE_TO_PAGES (Xhc->PageSize));\r
803 }\r
804 FreeAlignedPages (Xhc->ScratchBuf, EFI_SIZE_TO_PAGES (Xhc->MaxScratchpadBufs * sizeof (UINT64)));\r
805 }\r
806\r
807 if (Xhc->DCBAA != NULL) {\r
808 FreePages (Xhc->DCBAA, EFI_SIZE_TO_PAGES((Xhc->MaxSlotsEn + 1) * sizeof(UINT64)));\r
809 Xhc->DCBAA = NULL;\r
810 }\r
811\r
812 if (Xhc->CmdRing.RingSeg0 != NULL){\r
813 FreePages (Xhc->CmdRing.RingSeg0, EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER));\r
814 Xhc->CmdRing.RingSeg0 = NULL;\r
815 }\r
816\r
817 XhcFreeEventRing (Xhc,&Xhc->EventRing);\r
818}\r
819\r
820/**\r
821 Check if the Trb is a transaction of the URBs in XHCI's asynchronous transfer list.\r
822\r
823 @param Xhc The XHCI Instance.\r
824 @param Trb The TRB to be checked.\r
825 @param Urb The pointer to the matched Urb.\r
826\r
827 @retval TRUE The Trb is matched with a transaction of the URBs in the async list.\r
828 @retval FALSE The Trb is not matched with any URBs in the async list.\r
829\r
830**/\r
831BOOLEAN\r
832IsAsyncIntTrb (\r
833 IN USB_XHCI_INSTANCE *Xhc,\r
834 IN TRB_TEMPLATE *Trb,\r
835 OUT URB **Urb\r
836 )\r
837{\r
838 LIST_ENTRY *Entry;\r
839 LIST_ENTRY *Next;\r
840 TRB_TEMPLATE *CheckedTrb;\r
841 URB *CheckedUrb;\r
842 UINTN Index;\r
843\r
844 EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {\r
845 CheckedUrb = EFI_LIST_CONTAINER (Entry, URB, UrbList);\r
846 CheckedTrb = CheckedUrb->TrbStart;\r
847 for (Index = 0; Index < CheckedUrb->TrbNum; Index++) {\r
848 if (Trb == CheckedTrb) {\r
849 *Urb = CheckedUrb;\r
850 return TRUE;\r
851 }\r
852 CheckedTrb++;\r
853 if ((UINTN)CheckedTrb >= ((UINTN) CheckedUrb->Ring->RingSeg0 + sizeof (TRB_TEMPLATE) * CheckedUrb->Ring->TrbNumber)) {\r
854 CheckedTrb = (TRB_TEMPLATE*) CheckedUrb->Ring->RingSeg0;\r
855 }\r
856 }\r
857 }\r
858\r
859 return FALSE;\r
860}\r
861\r
862/**\r
863 Check if the Trb is a transaction of the URB.\r
864\r
865 @param Trb The TRB to be checked\r
866 @param Urb The transfer ring to be checked.\r
867\r
868 @retval TRUE It is a transaction of the URB.\r
869 @retval FALSE It is not any transaction of the URB.\r
870\r
871**/\r
872BOOLEAN\r
873IsTransferRingTrb (\r
874 IN TRB_TEMPLATE *Trb,\r
875 IN URB *Urb\r
876 )\r
877{\r
878 TRB_TEMPLATE *CheckedTrb;\r
879 UINTN Index;\r
880\r
881 CheckedTrb = Urb->Ring->RingSeg0;\r
882\r
883 ASSERT (Urb->Ring->TrbNumber == CMD_RING_TRB_NUMBER || Urb->Ring->TrbNumber == TR_RING_TRB_NUMBER);\r
884\r
885 for (Index = 0; Index < Urb->Ring->TrbNumber; Index++) {\r
886 if (Trb == CheckedTrb) {\r
887 return TRUE;\r
888 }\r
889 CheckedTrb++;\r
890 }\r
891\r
892 return FALSE;\r
893}\r
894\r
895/**\r
896 Check the URB's execution result and update the URB's\r
897 result accordingly.\r
898\r
899 @param Xhc The XHCI Instance.\r
900 @param Urb The URB to check result.\r
901\r
902 @return Whether the result of URB transfer is finialized.\r
903\r
904**/\r
905EFI_STATUS\r
906XhcCheckUrbResult (\r
907 IN USB_XHCI_INSTANCE *Xhc,\r
908 IN URB *Urb\r
909 )\r
910{\r
911 EVT_TRB_TRANSFER *EvtTrb;\r
912 TRB_TEMPLATE *TRBPtr;\r
913 UINTN Index;\r
914 UINT8 TRBType;\r
915 EFI_STATUS Status;\r
916 URB *AsyncUrb;\r
917 URB *CheckedUrb;\r
918 UINT64 XhcDequeue;\r
919 UINT32 High;\r
920 UINT32 Low;\r
921\r
922 ASSERT ((Xhc != NULL) && (Urb != NULL));\r
923\r
924 Status = EFI_SUCCESS;\r
925 AsyncUrb = NULL;\r
926\r
927 if (Urb->Finished) {\r
928 goto EXIT;\r
929 }\r
930\r
931 EvtTrb = NULL;\r
932\r
933 if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {\r
934 Urb->Result |= EFI_USB_ERR_SYSTEM;\r
935 Status = EFI_DEVICE_ERROR;\r
936 goto EXIT;\r
937 }\r
938\r
939 //\r
940 // Traverse the event ring to find out all new events from the previous check.\r
941 //\r
942 XhcSyncEventRing (Xhc, &Xhc->EventRing);\r
943 for (Index = 0; Index < Xhc->EventRing.TrbNumber; Index++) {\r
944 Status = XhcCheckNewEvent (Xhc, &Xhc->EventRing, ((TRB_TEMPLATE **)&EvtTrb));\r
945 if (Status == EFI_NOT_READY) {\r
946 //\r
947 // All new events are handled, return directly.\r
948 //\r
949 goto EXIT;\r
950 }\r
951\r
952 //\r
953 // Only handle COMMAND_COMPLETETION_EVENT and TRANSFER_EVENT.\r
954 //\r
955 if ((EvtTrb->Type != TRB_TYPE_COMMAND_COMPLT_EVENT) && (EvtTrb->Type != TRB_TYPE_TRANS_EVENT)) {\r
956 continue;\r
957 }\r
958\r
959 TRBPtr = (TRB_TEMPLATE *)(UINTN)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64) EvtTrb->TRBPtrHi, 32));\r
960\r
961 //\r
962 // Update the status of Urb according to the finished event regardless of whether\r
963 // the urb is current checked one or in the XHCI's async transfer list.\r
964 // This way is used to avoid that those completed async transfer events don't get\r
965 // handled in time and are flushed by newer coming events.\r
966 //\r
967 if (IsTransferRingTrb (TRBPtr, Urb)) {\r
968 CheckedUrb = Urb;\r
969 } else if (IsAsyncIntTrb (Xhc, TRBPtr, &AsyncUrb)) { \r
970 CheckedUrb = AsyncUrb;\r
971 } else {\r
972 continue;\r
973 }\r
974 \r
975 switch (EvtTrb->Completecode) {\r
976 case TRB_COMPLETION_STALL_ERROR:\r
977 CheckedUrb->Result |= EFI_USB_ERR_STALL;\r
978 CheckedUrb->Finished = TRUE;\r
979 DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: STALL_ERROR! Completecode = %x\n",EvtTrb->Completecode));\r
980 break;\r
981\r
982 case TRB_COMPLETION_BABBLE_ERROR:\r
983 CheckedUrb->Result |= EFI_USB_ERR_BABBLE;\r
984 CheckedUrb->Finished = TRUE;\r
985 DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: BABBLE_ERROR! Completecode = %x\n",EvtTrb->Completecode));\r
986 break;\r
987\r
988 case TRB_COMPLETION_DATA_BUFFER_ERROR:\r
989 CheckedUrb->Result |= EFI_USB_ERR_BUFFER;\r
990 CheckedUrb->Finished = TRUE;\r
991 DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: ERR_BUFFER! Completecode = %x\n",EvtTrb->Completecode));\r
992 break;\r
993\r
994 case TRB_COMPLETION_USB_TRANSACTION_ERROR:\r
995 CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;\r
996 CheckedUrb->Finished = TRUE;\r
997 DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: TRANSACTION_ERROR! Completecode = %x\n",EvtTrb->Completecode));\r
998 break;\r
999\r
1000 case TRB_COMPLETION_SHORT_PACKET:\r
1001 case TRB_COMPLETION_SUCCESS:\r
1002 if (EvtTrb->Completecode == TRB_COMPLETION_SHORT_PACKET) {\r
1003 DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: short packet happens!\n"));\r
1004 }\r
1005\r
1006 TRBType = (UINT8) (TRBPtr->Type);\r
1007 if ((TRBType == TRB_TYPE_DATA_STAGE) ||\r
1008 (TRBType == TRB_TYPE_NORMAL) ||\r
1009 (TRBType == TRB_TYPE_ISOCH)) {\r
1010 CheckedUrb->Completed += (CheckedUrb->DataLen - EvtTrb->Lenth);\r
1011 }\r
1012\r
1013 break;\r
1014\r
1015 default:\r
1016 DEBUG ((EFI_D_ERROR, "Transfer Default Error Occur! Completecode = 0x%x!\n",EvtTrb->Completecode));\r
1017 CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;\r
1018 CheckedUrb->Finished = TRUE;\r
1019 break;\r
1020 }\r
1021\r
1022 //\r
1023 // Only check first and end Trb event address\r
1024 //\r
1025 if (TRBPtr == CheckedUrb->TrbStart) {\r
1026 CheckedUrb->StartDone = TRUE;\r
1027 }\r
1028\r
1029 if (TRBPtr == CheckedUrb->TrbEnd) {\r
1030 CheckedUrb->EndDone = TRUE;\r
1031 }\r
1032\r
1033 if (CheckedUrb->StartDone && CheckedUrb->EndDone) {\r
1034 CheckedUrb->Finished = TRUE;\r
1035 CheckedUrb->EvtTrb = (TRB_TEMPLATE *)EvtTrb;\r
1036 }\r
1037 }\r
1038\r
1039EXIT:\r
1040\r
1041 //\r
1042 // Advance event ring to last available entry\r
1043 //\r
1044 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,\r
1045 // So divide it to two 32-bytes width register access.\r
1046 //\r
1047 Low = XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET);\r
1048 High = XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4);\r
1049 XhcDequeue = (UINT64)(LShiftU64((UINT64)High, 32) | Low);\r
1050\r
1051 if ((XhcDequeue & (~0x0F)) != ((UINT64)(UINTN)Xhc->EventRing.EventRingDequeue & (~0x0F))) {\r
1052 //\r
1053 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,\r
1054 // So divide it to two 32-bytes width register access.\r
1055 //\r
1056 XhcWriteRuntimeReg (Xhc, XHC_ERDP_OFFSET, XHC_LOW_32BIT (Xhc->EventRing.EventRingDequeue) | BIT3);\r
1057 XhcWriteRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4, XHC_HIGH_32BIT (Xhc->EventRing.EventRingDequeue));\r
1058 }\r
1059\r
1060 return Status;\r
1061}\r
1062\r
1063\r
1064/**\r
1065 Execute the transfer by polling the URB. This is a synchronous operation.\r
1066\r
1067 @param Xhc The XHCI Instance.\r
1068 @param CmdTransfer The executed URB is for cmd transfer or not.\r
1069 @param Urb The URB to execute.\r
1070 @param Timeout The time to wait before abort, in millisecond.\r
1071\r
1072 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.\r
1073 @return EFI_TIMEOUT The transfer failed due to time out.\r
1074 @return EFI_SUCCESS The transfer finished OK.\r
1075\r
1076**/\r
1077EFI_STATUS\r
1078XhcExecTransfer (\r
1079 IN USB_XHCI_INSTANCE *Xhc,\r
1080 IN BOOLEAN CmdTransfer,\r
1081 IN URB *Urb,\r
1082 IN UINTN Timeout\r
1083 )\r
1084{\r
1085 EFI_STATUS Status;\r
1086 UINTN Index;\r
1087 UINTN Loop;\r
1088 UINT8 SlotId;\r
1089 UINT8 Dci;\r
1090\r
1091 if (CmdTransfer) {\r
1092 SlotId = 0;\r
1093 Dci = 0;\r
1094 } else {\r
1095 SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);\r
1096 if (SlotId == 0) {\r
1097 return EFI_DEVICE_ERROR;\r
1098 }\r
1099 Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));\r
1100 ASSERT (Dci < 32);\r
1101 }\r
1102\r
1103 Status = EFI_SUCCESS;\r
1104 Loop = Timeout * XHC_1_MILLISECOND;\r
1105 if (Timeout == 0) {\r
1106 Loop = 0xFFFFFFFF;\r
1107 }\r
1108\r
1109 XhcRingDoorBell (Xhc, SlotId, Dci);\r
1110\r
1111 for (Index = 0; Index < Loop; Index++) {\r
1112 Status = XhcCheckUrbResult (Xhc, Urb);\r
1113 if (Urb->Finished) {\r
1114 break;\r
1115 }\r
1116 gBS->Stall (XHC_1_MICROSECOND);\r
1117 }\r
1118\r
1119 if (Index == Loop) {\r
1120 Urb->Result = EFI_USB_ERR_TIMEOUT;\r
1121 }\r
1122\r
1123 return Status;\r
1124}\r
1125\r
1126/**\r
1127 Delete a single asynchronous interrupt transfer for\r
1128 the device and endpoint.\r
1129\r
1130 @param Xhc The XHCI Instance.\r
1131 @param BusAddr The logical device address assigned by UsbBus driver.\r
1132 @param EpNum The endpoint of the target.\r
1133\r
1134 @retval EFI_SUCCESS An asynchronous transfer is removed.\r
1135 @retval EFI_NOT_FOUND No transfer for the device is found.\r
1136\r
1137**/\r
1138EFI_STATUS\r
1139XhciDelAsyncIntTransfer (\r
1140 IN USB_XHCI_INSTANCE *Xhc,\r
1141 IN UINT8 BusAddr,\r
1142 IN UINT8 EpNum\r
1143 )\r
1144{\r
1145 LIST_ENTRY *Entry;\r
1146 LIST_ENTRY *Next;\r
1147 URB *Urb;\r
1148 EFI_USB_DATA_DIRECTION Direction;\r
1149\r
1150 Direction = ((EpNum & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut;\r
1151 EpNum &= 0x0F;\r
1152\r
1153 Urb = NULL;\r
1154\r
1155 EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {\r
1156 Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);\r
1157 if ((Urb->Ep.BusAddr == BusAddr) &&\r
1158 (Urb->Ep.EpAddr == EpNum) &&\r
1159 (Urb->Ep.Direction == Direction)) {\r
1160 RemoveEntryList (&Urb->UrbList);\r
1161 FreePool (Urb->Data);\r
1162 FreePool (Urb);\r
1163 return EFI_SUCCESS;\r
1164 }\r
1165 }\r
1166\r
1167 return EFI_NOT_FOUND;\r
1168}\r
1169\r
1170/**\r
1171 Remove all the asynchronous interrutp transfers.\r
1172\r
1173 @param Xhc The XHCI Instance.\r
1174\r
1175**/\r
1176VOID\r
1177XhciDelAllAsyncIntTransfers (\r
1178 IN USB_XHCI_INSTANCE *Xhc\r
1179 )\r
1180{\r
1181 LIST_ENTRY *Entry;\r
1182 LIST_ENTRY *Next;\r
1183 URB *Urb;\r
1184\r
1185 EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {\r
1186 Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);\r
1187 RemoveEntryList (&Urb->UrbList);\r
1188 FreePool (Urb->Data);\r
1189 FreePool (Urb);\r
1190 }\r
1191}\r
1192\r
1193/**\r
1194 Update the queue head for next round of asynchronous transfer\r
1195\r
1196 @param Xhc The XHCI Instance.\r
1197 @param Urb The URB to update\r
1198\r
1199**/\r
1200VOID\r
1201XhcUpdateAsyncRequest (\r
1202 IN USB_XHCI_INSTANCE *Xhc,\r
1203 IN URB *Urb\r
1204 )\r
1205{\r
1206 EFI_STATUS Status;\r
1207\r
1208 if (Urb->Result == EFI_USB_NOERROR) {\r
1209 Status = XhcCreateTransferTrb (Xhc, Urb);\r
1210 if (EFI_ERROR (Status)) {\r
1211 return;\r
1212 }\r
1213 Status = RingIntTransferDoorBell (Xhc, Urb);\r
1214 if (EFI_ERROR (Status)) {\r
1215 return;\r
1216 }\r
1217 }\r
1218}\r
1219\r
1220\r
1221/**\r
1222 Interrupt transfer periodic check handler.\r
1223\r
1224 @param Event Interrupt event.\r
1225 @param Context Pointer to USB_XHCI_INSTANCE.\r
1226\r
1227**/\r
1228VOID\r
1229EFIAPI\r
1230XhcMonitorAsyncRequests (\r
1231 IN EFI_EVENT Event,\r
1232 IN VOID *Context\r
1233 )\r
1234{\r
1235 USB_XHCI_INSTANCE *Xhc;\r
1236 LIST_ENTRY *Entry;\r
1237 LIST_ENTRY *Next;\r
1238 UINT8 *ProcBuf;\r
1239 URB *Urb;\r
1240 UINT8 SlotId;\r
1241 EFI_TPL OldTpl;\r
1242\r
1243 OldTpl = gBS->RaiseTPL (XHC_TPL);\r
1244\r
1245 Xhc = (USB_XHCI_INSTANCE*) Context;\r
1246\r
1247 EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {\r
1248 Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);\r
1249\r
1250 //\r
1251 // Make sure that the device is available before every check.\r
1252 //\r
1253 SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);\r
1254 if (SlotId == 0) {\r
1255 continue;\r
1256 }\r
1257\r
1258 //\r
1259 // Check the result of URB execution. If it is still\r
1260 // active, check the next one.\r
1261 //\r
1262 XhcCheckUrbResult (Xhc, Urb);\r
1263\r
1264 if (!Urb->Finished) {\r
1265 continue;\r
1266 }\r
1267\r
1268 //\r
1269 // Allocate a buffer then copy the transferred data for user.\r
1270 // If failed to allocate the buffer, update the URB for next\r
1271 // round of transfer. Ignore the data of this round.\r
1272 //\r
1273 ProcBuf = NULL;\r
1274 if (Urb->Result == EFI_USB_NOERROR) {\r
1275 ASSERT (Urb->Completed <= Urb->DataLen);\r
1276\r
1277 ProcBuf = AllocateZeroPool (Urb->Completed);\r
1278\r
1279 if (ProcBuf == NULL) {\r
1280 XhcUpdateAsyncRequest (Xhc, Urb);\r
1281 continue;\r
1282 }\r
1283\r
1284 CopyMem (ProcBuf, Urb->Data, Urb->Completed);\r
1285 }\r
1286\r
1287 //\r
1288 // Leave error recovery to its related device driver. A\r
1289 // common case of the error recovery is to re-submit the\r
1290 // interrupt transfer which is linked to the head of the\r
1291 // list. This function scans from head to tail. So the\r
1292 // re-submitted interrupt transfer's callback function\r
1293 // will not be called again in this round. Don't touch this\r
1294 // URB after the callback, it may have been removed by the\r
1295 // callback.\r
1296 //\r
1297 if (Urb->Callback != NULL) {\r
1298 //\r
1299 // Restore the old TPL, USB bus maybe connect device in\r
1300 // his callback. Some drivers may has a lower TPL restriction.\r
1301 //\r
1302 gBS->RestoreTPL (OldTpl);\r
1303 (Urb->Callback) (ProcBuf, Urb->Completed, Urb->Context, Urb->Result);\r
1304 OldTpl = gBS->RaiseTPL (XHC_TPL);\r
1305 }\r
1306\r
1307 if (ProcBuf != NULL) {\r
1308 gBS->FreePool (ProcBuf);\r
1309 }\r
1310\r
1311 XhcUpdateAsyncRequest (Xhc, Urb);\r
1312 }\r
1313 gBS->RestoreTPL (OldTpl);\r
1314}\r
1315\r
1316/**\r
1317 Monitor the port status change. Enable/Disable device slot if there is a device attached/detached.\r
1318\r
1319 @param Xhc The XHCI Instance.\r
1320 @param ParentRouteChart The route string pointed to the parent device if it exists.\r
1321 @param Port The port to be polled.\r
1322 @param PortState The port state.\r
1323\r
1324 @retval EFI_SUCCESS Successfully enable/disable device slot according to port state.\r
1325 @retval Others Should not appear.\r
1326\r
1327**/\r
1328EFI_STATUS\r
1329EFIAPI\r
1330XhcPollPortStatusChange (\r
1331 IN USB_XHCI_INSTANCE *Xhc,\r
1332 IN USB_DEV_ROUTE ParentRouteChart,\r
1333 IN UINT8 Port,\r
1334 IN EFI_USB_PORT_STATUS *PortState\r
1335 )\r
1336{\r
1337 EFI_STATUS Status;\r
1338 UINT8 Speed;\r
1339 UINT8 SlotId;\r
1340 USB_DEV_ROUTE RouteChart;\r
1341\r
1342 Status = EFI_SUCCESS;\r
1343\r
1344 if (ParentRouteChart.Dword == 0) {\r
1345 RouteChart.Route.RouteString = 0;\r
1346 RouteChart.Route.RootPortNum = Port + 1;\r
1347 RouteChart.Route.TierNum = 1;\r
1348 } else {\r
1349 if(Port < 14) {\r
1350 RouteChart.Route.RouteString = ParentRouteChart.Route.RouteString | (Port << (4 * (ParentRouteChart.Route.TierNum - 1)));\r
1351 } else {\r
1352 RouteChart.Route.RouteString = ParentRouteChart.Route.RouteString | (15 << (4 * (ParentRouteChart.Route.TierNum - 1)));\r
1353 }\r
1354 RouteChart.Route.RootPortNum = ParentRouteChart.Route.RootPortNum;\r
1355 RouteChart.Route.TierNum = ParentRouteChart.Route.TierNum + 1;\r
1356 }\r
1357\r
1358 if (((PortState->PortStatus & USB_PORT_STAT_ENABLE) != 0) &&\r
1359 ((PortState->PortStatus & USB_PORT_STAT_CONNECTION) != 0)) {\r
1360 //\r
1361 // Has a device attached, Identify device speed after port is enabled.\r
1362 //\r
1363 Speed = EFI_USB_SPEED_FULL;\r
1364 if ((PortState->PortStatus & USB_PORT_STAT_LOW_SPEED) != 0) {\r
1365 Speed = EFI_USB_SPEED_LOW;\r
1366 } else if ((PortState->PortStatus & USB_PORT_STAT_HIGH_SPEED) != 0) {\r
1367 Speed = EFI_USB_SPEED_HIGH;\r
1368 } else if ((PortState->PortStatus & USB_PORT_STAT_SUPER_SPEED) != 0) {\r
1369 Speed = EFI_USB_SPEED_SUPER;\r
1370 }\r
1371 //\r
1372 // Execute Enable_Slot cmd for attached device, initialize device context and assign device address.\r
1373 //\r
1374 SlotId = XhcRouteStringToSlotId (Xhc, RouteChart);\r
1375 if (SlotId == 0) {\r
1376 if (Xhc->HcCParams.Data.Csz == 0) {\r
1377 Status = XhcInitializeDeviceSlot (Xhc, ParentRouteChart, Port, RouteChart, Speed);\r
1378 } else {\r
1379 Status = XhcInitializeDeviceSlot64 (Xhc, ParentRouteChart, Port, RouteChart, Speed);\r
1380 }\r
1381 ASSERT_EFI_ERROR (Status);\r
1382 }\r
1383 } else if ((PortState->PortStatus & USB_PORT_STAT_CONNECTION) == 0) {\r
1384 //\r
1385 // Device is detached. Disable the allocated device slot and release resource.\r
1386 //\r
1387 SlotId = XhcRouteStringToSlotId (Xhc, RouteChart);\r
1388 if (SlotId != 0) {\r
1389 if (Xhc->HcCParams.Data.Csz == 0) {\r
1390 Status = XhcDisableSlotCmd (Xhc, SlotId);\r
1391 } else {\r
1392 Status = XhcDisableSlotCmd64 (Xhc, SlotId);\r
1393 }\r
1394 ASSERT_EFI_ERROR (Status);\r
1395 }\r
1396 }\r
1397 return Status;\r
1398}\r
1399\r
1400\r
1401/**\r
1402 Calculate the device context index by endpoint address and direction.\r
1403\r
1404 @param EpAddr The target endpoint number.\r
1405 @param Direction The direction of the target endpoint.\r
1406\r
1407 @return The device context index of endpoint.\r
1408\r
1409**/\r
1410UINT8\r
1411XhcEndpointToDci (\r
1412 IN UINT8 EpAddr,\r
1413 IN UINT8 Direction\r
1414 )\r
1415{\r
1416 UINT8 Index;\r
1417\r
1418 if (EpAddr == 0) {\r
1419 return 1;\r
1420 } else {\r
1421 Index = (UINT8) (2 * EpAddr);\r
1422 if (Direction == EfiUsbDataIn) {\r
1423 Index += 1;\r
1424 }\r
1425 return Index;\r
1426 }\r
1427}\r
1428\r
1429/**\r
1430 Find out the actual device address according to the requested device address from UsbBus.\r
1431\r
1432 @param Xhc The XHCI Instance.\r
1433 @param BusDevAddr The requested device address by UsbBus upper driver.\r
1434\r
1435 @return The actual device address assigned to the device.\r
1436\r
1437**/\r
1438UINT8\r
1439EFIAPI\r
1440XhcBusDevAddrToSlotId (\r
1441 IN USB_XHCI_INSTANCE *Xhc,\r
1442 IN UINT8 BusDevAddr\r
1443 )\r
1444{\r
1445 UINT8 Index;\r
1446\r
1447 for (Index = 0; Index < 255; Index++) {\r
1448 if (Xhc->UsbDevContext[Index + 1].Enabled &&\r
1449 (Xhc->UsbDevContext[Index + 1].SlotId != 0) &&\r
1450 (Xhc->UsbDevContext[Index + 1].BusDevAddr == BusDevAddr)) {\r
1451 break;\r
1452 }\r
1453 }\r
1454\r
1455 if (Index == 255) {\r
1456 return 0;\r
1457 }\r
1458\r
1459 return Xhc->UsbDevContext[Index + 1].SlotId;\r
1460}\r
1461\r
1462/**\r
1463 Find out the slot id according to the device's route string.\r
1464\r
1465 @param Xhc The XHCI Instance.\r
1466 @param RouteString The route string described the device location.\r
1467\r
1468 @return The slot id used by the device.\r
1469\r
1470**/\r
1471UINT8\r
1472EFIAPI\r
1473XhcRouteStringToSlotId (\r
1474 IN USB_XHCI_INSTANCE *Xhc,\r
1475 IN USB_DEV_ROUTE RouteString\r
1476 )\r
1477{\r
1478 UINT8 Index;\r
1479\r
1480 for (Index = 0; Index < 255; Index++) {\r
1481 if (Xhc->UsbDevContext[Index + 1].Enabled &&\r
1482 (Xhc->UsbDevContext[Index + 1].SlotId != 0) &&\r
1483 (Xhc->UsbDevContext[Index + 1].RouteString.Dword == RouteString.Dword)) {\r
1484 break;\r
1485 }\r
1486 }\r
1487\r
1488 if (Index == 255) {\r
1489 return 0;\r
1490 }\r
1491\r
1492 return Xhc->UsbDevContext[Index + 1].SlotId;\r
1493}\r
1494\r
1495/**\r
1496 Synchronize the specified event ring to update the enqueue and dequeue pointer.\r
1497\r
1498 @param Xhc The XHCI Instance.\r
1499 @param EvtRing The event ring to sync.\r
1500\r
1501 @retval EFI_SUCCESS The event ring is synchronized successfully.\r
1502\r
1503**/\r
1504EFI_STATUS\r
1505EFIAPI\r
1506XhcSyncEventRing (\r
1507 IN USB_XHCI_INSTANCE *Xhc,\r
1508 IN EVENT_RING *EvtRing\r
1509 )\r
1510{\r
1511 UINTN Index;\r
1512 TRB_TEMPLATE *EvtTrb1;\r
1513\r
1514 ASSERT (EvtRing != NULL);\r
1515\r
1516 //\r
1517 // Calculate the EventRingEnqueue and EventRingCCS.\r
1518 // Note: only support single Segment\r
1519 //\r
1520 EvtTrb1 = EvtRing->EventRingDequeue;\r
1521\r
1522 for (Index = 0; Index < EvtRing->TrbNumber; Index++) {\r
1523 if (EvtTrb1->CycleBit != EvtRing->EventRingCCS) {\r
1524 break;\r
1525 }\r
1526\r
1527 EvtTrb1++;\r
1528\r
1529 if ((UINTN)EvtTrb1 >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {\r
1530 EvtTrb1 = EvtRing->EventRingSeg0;\r
1531 EvtRing->EventRingCCS = (EvtRing->EventRingCCS) ? 0 : 1;\r
1532 }\r
1533 }\r
1534\r
1535 if (Index < EvtRing->TrbNumber) {\r
1536 EvtRing->EventRingEnqueue = EvtTrb1;\r
1537 } else {\r
1538 ASSERT (FALSE);\r
1539 }\r
1540\r
1541 return EFI_SUCCESS;\r
1542}\r
1543\r
1544/**\r
1545 Synchronize the specified transfer ring to update the enqueue and dequeue pointer.\r
1546\r
1547 @param Xhc The XHCI Instance.\r
1548 @param TrsRing The transfer ring to sync.\r
1549\r
1550 @retval EFI_SUCCESS The transfer ring is synchronized successfully.\r
1551\r
1552**/\r
1553EFI_STATUS\r
1554EFIAPI\r
1555XhcSyncTrsRing (\r
1556 IN USB_XHCI_INSTANCE *Xhc,\r
1557 IN TRANSFER_RING *TrsRing\r
1558 )\r
1559{\r
1560 UINTN Index;\r
1561 TRB_TEMPLATE *TrsTrb;\r
1562\r
1563 ASSERT (TrsRing != NULL);\r
1564 //\r
1565 // Calculate the latest RingEnqueue and RingPCS\r
1566 //\r
1567 TrsTrb = TrsRing->RingEnqueue;\r
1568 ASSERT (TrsTrb != NULL);\r
1569\r
1570 for (Index = 0; Index < TrsRing->TrbNumber; Index++) {\r
1571 if (TrsTrb->CycleBit != (TrsRing->RingPCS & BIT0)) {\r
1572 break;\r
1573 }\r
1574 TrsTrb++;\r
1575 if ((UINT8) TrsTrb->Type == TRB_TYPE_LINK) {\r
1576 ASSERT (((LINK_TRB*)TrsTrb)->TC != 0);\r
1577 //\r
1578 // set cycle bit in Link TRB as normal\r
1579 //\r
1580 ((LINK_TRB*)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0;\r
1581 //\r
1582 // Toggle PCS maintained by software\r
1583 //\r
1584 TrsRing->RingPCS = (TrsRing->RingPCS & BIT0) ? 0 : 1;\r
1585 TrsTrb = (TRB_TEMPLATE *)(UINTN)((TrsTrb->Parameter1 | LShiftU64 ((UINT64)TrsTrb->Parameter2, 32)) & ~0x0F);\r
1586 }\r
1587 }\r
1588\r
1589 ASSERT (Index != TrsRing->TrbNumber);\r
1590\r
1591 if (TrsTrb != TrsRing->RingEnqueue) {\r
1592 TrsRing->RingEnqueue = TrsTrb;\r
1593 }\r
1594\r
1595 //\r
1596 // Clear the Trb context for enqueue, but reserve the PCS bit\r
1597 //\r
1598 TrsTrb->Parameter1 = 0;\r
1599 TrsTrb->Parameter2 = 0;\r
1600 TrsTrb->Status = 0;\r
1601 TrsTrb->RsvdZ1 = 0;\r
1602 TrsTrb->Type = 0;\r
1603 TrsTrb->Control = 0;\r
1604\r
1605 return EFI_SUCCESS;\r
1606}\r
1607\r
1608/**\r
1609 Check if there is a new generated event.\r
1610\r
1611 @param Xhc The XHCI Instance.\r
1612 @param EvtRing The event ring to check.\r
1613 @param NewEvtTrb The new event TRB found.\r
1614\r
1615 @retval EFI_SUCCESS Found a new event TRB at the event ring.\r
1616 @retval EFI_NOT_READY The event ring has no new event.\r
1617\r
1618**/\r
1619EFI_STATUS\r
1620EFIAPI\r
1621XhcCheckNewEvent (\r
1622 IN USB_XHCI_INSTANCE *Xhc,\r
1623 IN EVENT_RING *EvtRing,\r
1624 OUT TRB_TEMPLATE **NewEvtTrb\r
1625 )\r
1626{\r
1627 ASSERT (EvtRing != NULL);\r
1628\r
1629 *NewEvtTrb = EvtRing->EventRingDequeue;\r
1630\r
1631 if (EvtRing->EventRingDequeue == EvtRing->EventRingEnqueue) {\r
1632 return EFI_NOT_READY;\r
1633 }\r
1634\r
1635 EvtRing->EventRingDequeue++;\r
1636 //\r
1637 // If the dequeue pointer is beyond the ring, then roll-back it to the begining of the ring.\r
1638 //\r
1639 if ((UINTN)EvtRing->EventRingDequeue >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {\r
1640 EvtRing->EventRingDequeue = EvtRing->EventRingSeg0;\r
1641 }\r
1642\r
1643 return EFI_SUCCESS;\r
1644}\r
1645\r
1646/**\r
1647 Ring the door bell to notify XHCI there is a transaction to be executed.\r
1648\r
1649 @param Xhc The XHCI Instance.\r
1650 @param SlotId The slot id of the target device.\r
1651 @param Dci The device context index of the target slot or endpoint.\r
1652\r
1653 @retval EFI_SUCCESS Successfully ring the door bell.\r
1654\r
1655**/\r
1656EFI_STATUS\r
1657EFIAPI\r
1658XhcRingDoorBell (\r
1659 IN USB_XHCI_INSTANCE *Xhc,\r
1660 IN UINT8 SlotId,\r
1661 IN UINT8 Dci\r
1662 )\r
1663{\r
1664 if (SlotId == 0) {\r
1665 XhcWriteDoorBellReg (Xhc, 0, 0);\r
1666 } else {\r
1667 XhcWriteDoorBellReg (Xhc, SlotId * sizeof (UINT32), Dci);\r
1668 }\r
1669\r
1670 return EFI_SUCCESS;\r
1671}\r
1672\r
1673/**\r
1674 Ring the door bell to notify XHCI there is a transaction to be executed through URB.\r
1675\r
1676 @param Xhc The XHCI Instance.\r
1677 @param Urb The URB to be rung.\r
1678\r
1679 @retval EFI_SUCCESS Successfully ring the door bell.\r
1680\r
1681**/\r
1682EFI_STATUS\r
1683RingIntTransferDoorBell (\r
1684 IN USB_XHCI_INSTANCE *Xhc,\r
1685 IN URB *Urb\r
1686 )\r
1687{\r
1688 UINT8 SlotId;\r
1689 UINT8 Dci;\r
1690\r
1691 SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);\r
1692 Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));\r
1693 XhcRingDoorBell (Xhc, SlotId, Dci);\r
1694 return EFI_SUCCESS;\r
1695}\r
1696\r
1697/**\r
1698 Assign and initialize the device slot for a new device.\r
1699\r
1700 @param Xhc The XHCI Instance.\r
1701 @param ParentRouteChart The route string pointed to the parent device.\r
1702 @param ParentPort The port at which the device is located.\r
1703 @param RouteChart The route string pointed to the device.\r
1704 @param DeviceSpeed The device speed.\r
1705\r
1706 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.\r
1707\r
1708**/\r
1709EFI_STATUS\r
1710EFIAPI\r
1711XhcInitializeDeviceSlot (\r
1712 IN USB_XHCI_INSTANCE *Xhc,\r
1713 IN USB_DEV_ROUTE ParentRouteChart,\r
1714 IN UINT16 ParentPort,\r
1715 IN USB_DEV_ROUTE RouteChart,\r
1716 IN UINT8 DeviceSpeed\r
1717 )\r
1718{\r
1719 EFI_STATUS Status;\r
1720 EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
1721 INPUT_CONTEXT *InputContext;\r
1722 DEVICE_CONTEXT *OutputContext;\r
1723 TRANSFER_RING *EndpointTransferRing;\r
1724 CMD_TRB_ADDRESS_DEVICE CmdTrbAddr;\r
1725 UINT8 DeviceAddress;\r
1726 CMD_TRB_ENABLE_SLOT CmdTrb;\r
1727 UINT8 SlotId;\r
1728 UINT8 ParentSlotId;\r
1729 DEVICE_CONTEXT *ParentDeviceContext;\r
1730\r
1731 ZeroMem (&CmdTrb, sizeof (CMD_TRB_ENABLE_SLOT));\r
1732 CmdTrb.CycleBit = 1;\r
1733 CmdTrb.Type = TRB_TYPE_EN_SLOT;\r
1734\r
1735 Status = XhcCmdTransfer (\r
1736 Xhc,\r
1737 (TRB_TEMPLATE *) (UINTN) &CmdTrb,\r
1738 XHC_GENERIC_TIMEOUT,\r
1739 (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
1740 );\r
1741 ASSERT_EFI_ERROR (Status);\r
1742 ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);\r
1743 DEBUG ((EFI_D_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));\r
1744 SlotId = (UINT8)EvtTrb->SlotId;\r
1745 ASSERT (SlotId != 0);\r
1746\r
1747 ZeroMem (&Xhc->UsbDevContext[SlotId], sizeof (USB_DEV_CONTEXT));\r
1748 Xhc->UsbDevContext[SlotId].Enabled = TRUE;\r
1749 Xhc->UsbDevContext[SlotId].SlotId = SlotId;\r
1750 Xhc->UsbDevContext[SlotId].RouteString.Dword = RouteChart.Dword;\r
1751 Xhc->UsbDevContext[SlotId].ParentRouteString.Dword = ParentRouteChart.Dword;\r
1752\r
1753 //\r
1754 // 4.3.3 Device Slot Initialization\r
1755 // 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.\r
1756 //\r
1757 InputContext = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (INPUT_CONTEXT)));\r
1758 ASSERT (InputContext != NULL);\r
1759 ASSERT (((UINTN) InputContext & 0x3F) == 0);\r
1760 ZeroMem (InputContext, sizeof (INPUT_CONTEXT));\r
1761\r
1762 Xhc->UsbDevContext[SlotId].InputContext = (VOID *) InputContext;\r
1763\r
1764 //\r
1765 // 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1\r
1766 // flags to '1'. These flags indicate that the Slot Context and the Endpoint 0 Context of the Input\r
1767 // Context are affected by the command.\r
1768 //\r
1769 InputContext->InputControlContext.Dword2 |= (BIT0 | BIT1);\r
1770\r
1771 //\r
1772 // 3) Initialize the Input Slot Context data structure\r
1773 //\r
1774 InputContext->Slot.RouteString = RouteChart.Route.RouteString;\r
1775 InputContext->Slot.Speed = DeviceSpeed + 1;\r
1776 InputContext->Slot.ContextEntries = 1;\r
1777 InputContext->Slot.RootHubPortNum = RouteChart.Route.RootPortNum;\r
1778\r
1779 if (RouteChart.Route.RouteString) {\r
1780 //\r
1781 // The device is behind of hub device.\r
1782 //\r
1783 ParentSlotId = XhcRouteStringToSlotId(Xhc, ParentRouteChart);\r
1784 ASSERT (ParentSlotId != 0);\r
1785 //\r
1786 //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context\r
1787 //\r
1788 ParentDeviceContext = (DEVICE_CONTEXT *)Xhc->UsbDevContext[ParentSlotId].OutputContext;\r
1789 if ((ParentDeviceContext->Slot.TTPortNum == 0) &&\r
1790 (ParentDeviceContext->Slot.TTHubSlotId == 0)) {\r
1791 if ((ParentDeviceContext->Slot.Speed == (EFI_USB_SPEED_HIGH + 1)) && (DeviceSpeed < EFI_USB_SPEED_HIGH)) {\r
1792 //\r
1793 // Full/Low device attached to High speed hub port that isolates the high speed signaling\r
1794 // environment from Full/Low speed signaling environment for a device\r
1795 //\r
1796 InputContext->Slot.TTPortNum = ParentPort;\r
1797 InputContext->Slot.TTHubSlotId = ParentSlotId;\r
1798 }\r
1799 } else {\r
1800 //\r
1801 // Inherit the TT parameters from parent device.\r
1802 //\r
1803 InputContext->Slot.TTPortNum = ParentDeviceContext->Slot.TTPortNum;\r
1804 InputContext->Slot.TTHubSlotId = ParentDeviceContext->Slot.TTHubSlotId;\r
1805 //\r
1806 // If the device is a High speed device then down the speed to be the same as its parent Hub\r
1807 //\r
1808 if (DeviceSpeed == EFI_USB_SPEED_HIGH) {\r
1809 InputContext->Slot.Speed = ParentDeviceContext->Slot.Speed;\r
1810 }\r
1811 }\r
1812 }\r
1813\r
1814 //\r
1815 // 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.\r
1816 //\r
1817 EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));\r
1818 Xhc->UsbDevContext[SlotId].EndpointTransferRing[0] = EndpointTransferRing;\r
1819 CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);\r
1820 //\r
1821 // 5) Initialize the Input default control Endpoint 0 Context (6.2.3).\r
1822 //\r
1823 InputContext->EP[0].EPType = ED_CONTROL_BIDIR;\r
1824\r
1825 if (DeviceSpeed == EFI_USB_SPEED_SUPER) {\r
1826 InputContext->EP[0].MaxPacketSize = 512;\r
1827 } else if (DeviceSpeed == EFI_USB_SPEED_HIGH) {\r
1828 InputContext->EP[0].MaxPacketSize = 64;\r
1829 } else {\r
1830 InputContext->EP[0].MaxPacketSize = 8;\r
1831 }\r
1832 //\r
1833 // Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints\r
1834 // 1KB, and Bulk and Isoch endpoints 3KB.\r
1835 //\r
1836 InputContext->EP[0].AverageTRBLength = 8;\r
1837 InputContext->EP[0].MaxBurstSize = 0;\r
1838 InputContext->EP[0].Interval = 0;\r
1839 InputContext->EP[0].MaxPStreams = 0;\r
1840 InputContext->EP[0].Mult = 0;\r
1841 InputContext->EP[0].CErr = 3;\r
1842\r
1843 //\r
1844 // Init the DCS(dequeue cycle state) as the transfer ring's CCS\r
1845 //\r
1846 InputContext->EP[0].PtrLo = XHC_LOW_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0) | BIT0;\r
1847 InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0);\r
1848\r
1849 //\r
1850 // 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.\r
1851 //\r
1852 OutputContext = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (DEVICE_CONTEXT)));\r
1853 ASSERT (OutputContext != NULL);\r
1854 ASSERT (((UINTN) OutputContext & 0x3F) == 0);\r
1855 ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT));\r
1856\r
1857 Xhc->UsbDevContext[SlotId].OutputContext = OutputContext;\r
1858 //\r
1859 // 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with\r
1860 // a pointer to the Output Device Context data structure (6.2.1).\r
1861 //\r
1862 Xhc->DCBAA[SlotId] = (UINT64) (UINTN) OutputContext;\r
1863\r
1864 //\r
1865 // 8) Issue an Address Device Command for the Device Slot, where the command points to the Input\r
1866 // Context data structure described above.\r
1867 //\r
1868 ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));\r
1869 CmdTrbAddr.PtrLo = XHC_LOW_32BIT (Xhc->UsbDevContext[SlotId].InputContext);\r
1870 CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (Xhc->UsbDevContext[SlotId].InputContext);\r
1871 CmdTrbAddr.CycleBit = 1;\r
1872 CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV;\r
1873 CmdTrbAddr.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r
1874 Status = XhcCmdTransfer (\r
1875 Xhc,\r
1876 (TRB_TEMPLATE *) (UINTN) &CmdTrbAddr,\r
1877 XHC_GENERIC_TIMEOUT,\r
1878 (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
1879 );\r
1880 ASSERT (!EFI_ERROR(Status));\r
1881\r
1882 DeviceAddress = (UINT8) ((DEVICE_CONTEXT *) OutputContext)->Slot.DeviceAddress;\r
1883 DEBUG ((EFI_D_INFO, " Address %d assigned successfully\n", DeviceAddress));\r
1884\r
1885 Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;\r
1886\r
1887 return Status;\r
1888}\r
1889\r
1890/**\r
1891 Assign and initialize the device slot for a new device.\r
1892\r
1893 @param Xhc The XHCI Instance.\r
1894 @param ParentRouteChart The route string pointed to the parent device.\r
1895 @param ParentPort The port at which the device is located.\r
1896 @param RouteChart The route string pointed to the device.\r
1897 @param DeviceSpeed The device speed.\r
1898\r
1899 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.\r
1900\r
1901**/\r
1902EFI_STATUS\r
1903EFIAPI\r
1904XhcInitializeDeviceSlot64 (\r
1905 IN USB_XHCI_INSTANCE *Xhc,\r
1906 IN USB_DEV_ROUTE ParentRouteChart,\r
1907 IN UINT16 ParentPort,\r
1908 IN USB_DEV_ROUTE RouteChart,\r
1909 IN UINT8 DeviceSpeed\r
1910 )\r
1911{\r
1912 EFI_STATUS Status;\r
1913 EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
1914 INPUT_CONTEXT_64 *InputContext;\r
1915 DEVICE_CONTEXT_64 *OutputContext;\r
1916 TRANSFER_RING *EndpointTransferRing;\r
1917 CMD_TRB_ADDRESS_DEVICE CmdTrbAddr;\r
1918 UINT8 DeviceAddress;\r
1919 CMD_TRB_ENABLE_SLOT CmdTrb;\r
1920 UINT8 SlotId;\r
1921 UINT8 ParentSlotId;\r
1922 DEVICE_CONTEXT_64 *ParentDeviceContext;\r
1923\r
1924 ZeroMem (&CmdTrb, sizeof (CMD_TRB_ENABLE_SLOT));\r
1925 CmdTrb.CycleBit = 1;\r
1926 CmdTrb.Type = TRB_TYPE_EN_SLOT;\r
1927\r
1928 Status = XhcCmdTransfer (\r
1929 Xhc,\r
1930 (TRB_TEMPLATE *) (UINTN) &CmdTrb,\r
1931 XHC_GENERIC_TIMEOUT,\r
1932 (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
1933 );\r
1934 ASSERT_EFI_ERROR (Status);\r
1935 ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);\r
1936 DEBUG ((EFI_D_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));\r
1937 SlotId = (UINT8)EvtTrb->SlotId;\r
1938 ASSERT (SlotId != 0);\r
1939\r
1940 ZeroMem (&Xhc->UsbDevContext[SlotId], sizeof (USB_DEV_CONTEXT));\r
1941 Xhc->UsbDevContext[SlotId].Enabled = TRUE;\r
1942 Xhc->UsbDevContext[SlotId].SlotId = SlotId;\r
1943 Xhc->UsbDevContext[SlotId].RouteString.Dword = RouteChart.Dword;\r
1944 Xhc->UsbDevContext[SlotId].ParentRouteString.Dword = ParentRouteChart.Dword;\r
1945\r
1946 //\r
1947 // 4.3.3 Device Slot Initialization\r
1948 // 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.\r
1949 //\r
1950 InputContext = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (INPUT_CONTEXT_64)));\r
1951 ASSERT (InputContext != NULL);\r
1952 ASSERT (((UINTN) InputContext & 0x3F) == 0);\r
1953 ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));\r
1954\r
1955 Xhc->UsbDevContext[SlotId].InputContext = (VOID *) InputContext;\r
1956\r
1957 //\r
1958 // 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1\r
1959 // flags to '1'. These flags indicate that the Slot Context and the Endpoint 0 Context of the Input\r
1960 // Context are affected by the command.\r
1961 //\r
1962 InputContext->InputControlContext.Dword2 |= (BIT0 | BIT1);\r
1963\r
1964 //\r
1965 // 3) Initialize the Input Slot Context data structure\r
1966 //\r
1967 InputContext->Slot.RouteString = RouteChart.Route.RouteString;\r
1968 InputContext->Slot.Speed = DeviceSpeed + 1;\r
1969 InputContext->Slot.ContextEntries = 1;\r
1970 InputContext->Slot.RootHubPortNum = RouteChart.Route.RootPortNum;\r
1971\r
1972 if (RouteChart.Route.RouteString) {\r
1973 //\r
1974 // The device is behind of hub device.\r
1975 //\r
1976 ParentSlotId = XhcRouteStringToSlotId(Xhc, ParentRouteChart);\r
1977 ASSERT (ParentSlotId != 0);\r
1978 //\r
1979 //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context\r
1980 //\r
1981 ParentDeviceContext = (DEVICE_CONTEXT_64 *)Xhc->UsbDevContext[ParentSlotId].OutputContext;\r
1982 if ((ParentDeviceContext->Slot.TTPortNum == 0) &&\r
1983 (ParentDeviceContext->Slot.TTHubSlotId == 0)) {\r
1984 if ((ParentDeviceContext->Slot.Speed == (EFI_USB_SPEED_HIGH + 1)) && (DeviceSpeed < EFI_USB_SPEED_HIGH)) {\r
1985 //\r
1986 // Full/Low device attached to High speed hub port that isolates the high speed signaling\r
1987 // environment from Full/Low speed signaling environment for a device\r
1988 //\r
1989 InputContext->Slot.TTPortNum = ParentPort;\r
1990 InputContext->Slot.TTHubSlotId = ParentSlotId;\r
1991 }\r
1992 } else {\r
1993 //\r
1994 // Inherit the TT parameters from parent device.\r
1995 //\r
1996 InputContext->Slot.TTPortNum = ParentDeviceContext->Slot.TTPortNum;\r
1997 InputContext->Slot.TTHubSlotId = ParentDeviceContext->Slot.TTHubSlotId;\r
1998 //\r
1999 // If the device is a High speed device then down the speed to be the same as its parent Hub\r
2000 //\r
2001 if (DeviceSpeed == EFI_USB_SPEED_HIGH) {\r
2002 InputContext->Slot.Speed = ParentDeviceContext->Slot.Speed;\r
2003 }\r
2004 }\r
2005 }\r
2006\r
2007 //\r
2008 // 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.\r
2009 //\r
2010 EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));\r
2011 Xhc->UsbDevContext[SlotId].EndpointTransferRing[0] = EndpointTransferRing;\r
2012 CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);\r
2013 //\r
2014 // 5) Initialize the Input default control Endpoint 0 Context (6.2.3).\r
2015 //\r
2016 InputContext->EP[0].EPType = ED_CONTROL_BIDIR;\r
2017\r
2018 if (DeviceSpeed == EFI_USB_SPEED_SUPER) {\r
2019 InputContext->EP[0].MaxPacketSize = 512;\r
2020 } else if (DeviceSpeed == EFI_USB_SPEED_HIGH) {\r
2021 InputContext->EP[0].MaxPacketSize = 64;\r
2022 } else {\r
2023 InputContext->EP[0].MaxPacketSize = 8;\r
2024 }\r
2025 //\r
2026 // Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints\r
2027 // 1KB, and Bulk and Isoch endpoints 3KB.\r
2028 //\r
2029 InputContext->EP[0].AverageTRBLength = 8;\r
2030 InputContext->EP[0].MaxBurstSize = 0;\r
2031 InputContext->EP[0].Interval = 0;\r
2032 InputContext->EP[0].MaxPStreams = 0;\r
2033 InputContext->EP[0].Mult = 0;\r
2034 InputContext->EP[0].CErr = 3;\r
2035\r
2036 //\r
2037 // Init the DCS(dequeue cycle state) as the transfer ring's CCS\r
2038 //\r
2039 InputContext->EP[0].PtrLo = XHC_LOW_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0) | BIT0;\r
2040 InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0);\r
2041\r
2042 //\r
2043 // 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.\r
2044 //\r
2045 OutputContext = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (DEVICE_CONTEXT_64)));\r
2046 ASSERT (OutputContext != NULL);\r
2047 ASSERT (((UINTN) OutputContext & 0x3F) == 0);\r
2048 ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT_64));\r
2049\r
2050 Xhc->UsbDevContext[SlotId].OutputContext = OutputContext;\r
2051 //\r
2052 // 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with\r
2053 // a pointer to the Output Device Context data structure (6.2.1).\r
2054 //\r
2055 Xhc->DCBAA[SlotId] = (UINT64) (UINTN) OutputContext;\r
2056\r
2057 //\r
2058 // 8) Issue an Address Device Command for the Device Slot, where the command points to the Input\r
2059 // Context data structure described above.\r
2060 //\r
2061 ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));\r
2062 CmdTrbAddr.PtrLo = XHC_LOW_32BIT (Xhc->UsbDevContext[SlotId].InputContext);\r
2063 CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (Xhc->UsbDevContext[SlotId].InputContext);\r
2064 CmdTrbAddr.CycleBit = 1;\r
2065 CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV;\r
2066 CmdTrbAddr.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r
2067 Status = XhcCmdTransfer (\r
2068 Xhc,\r
2069 (TRB_TEMPLATE *) (UINTN) &CmdTrbAddr,\r
2070 XHC_GENERIC_TIMEOUT,\r
2071 (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
2072 );\r
2073 ASSERT (!EFI_ERROR(Status));\r
2074\r
2075 DeviceAddress = (UINT8) ((DEVICE_CONTEXT_64 *) OutputContext)->Slot.DeviceAddress;\r
2076 DEBUG ((EFI_D_INFO, " Address %d assigned successfully\n", DeviceAddress));\r
2077\r
2078 Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;\r
2079\r
2080 return Status;\r
2081}\r
2082\r
2083\r
2084/**\r
2085 Disable the specified device slot.\r
2086\r
2087 @param Xhc The XHCI Instance.\r
2088 @param SlotId The slot id to be disabled.\r
2089\r
2090 @retval EFI_SUCCESS Successfully disable the device slot.\r
2091\r
2092**/\r
2093EFI_STATUS\r
2094EFIAPI\r
2095XhcDisableSlotCmd (\r
2096 IN USB_XHCI_INSTANCE *Xhc,\r
2097 IN UINT8 SlotId\r
2098 )\r
2099{\r
2100 EFI_STATUS Status;\r
2101 TRB_TEMPLATE *EvtTrb;\r
2102 CMD_TRB_DISABLE_SLOT CmdTrbDisSlot;\r
2103 UINT8 Index;\r
2104 VOID *RingSeg;\r
2105\r
2106 //\r
2107 // Disable the device slots occupied by these devices on its downstream ports.\r
2108 // Entry 0 is reserved.\r
2109 //\r
2110 for (Index = 0; Index < 255; Index++) {\r
2111 if (!Xhc->UsbDevContext[Index + 1].Enabled ||\r
2112 (Xhc->UsbDevContext[Index + 1].SlotId == 0) ||\r
2113 (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword)) {\r
2114 continue;\r
2115 }\r
2116\r
2117 Status = XhcDisableSlotCmd (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);\r
2118\r
2119 if (EFI_ERROR (Status)) {\r
2120 DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));\r
2121 Xhc->UsbDevContext[Index + 1].SlotId = 0;\r
2122 }\r
2123 }\r
2124\r
2125 //\r
2126 // Construct the disable slot command\r
2127 //\r
2128 DEBUG ((EFI_D_INFO, "Disable device slot %d!\n", SlotId));\r
2129\r
2130 ZeroMem (&CmdTrbDisSlot, sizeof (CmdTrbDisSlot));\r
2131 CmdTrbDisSlot.CycleBit = 1;\r
2132 CmdTrbDisSlot.Type = TRB_TYPE_DIS_SLOT;\r
2133 CmdTrbDisSlot.SlotId = SlotId;\r
2134 Status = XhcCmdTransfer (\r
2135 Xhc,\r
2136 (TRB_TEMPLATE *) (UINTN) &CmdTrbDisSlot,\r
2137 XHC_GENERIC_TIMEOUT,\r
2138 (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
2139 );\r
2140 ASSERT_EFI_ERROR(Status);\r
2141 //\r
2142 // Free the slot's device context entry\r
2143 //\r
2144 Xhc->DCBAA[SlotId] = 0;\r
2145\r
2146 //\r
2147 // Free the slot related data structure\r
2148 //\r
2149 for (Index = 0; Index < 31; Index++) {\r
2150 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] != NULL) {\r
2151 RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;\r
2152 if (RingSeg != NULL) {\r
2153 FreePages (RingSeg, EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER));\r
2154 }\r
2155 FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);\r
2156 }\r
2157 }\r
2158\r
2159 for (Index = 0; Index < Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations; Index++) {\r
2160 if (Xhc->UsbDevContext[SlotId].ConfDesc[Index] != NULL) {\r
2161 FreePool (Xhc->UsbDevContext[SlotId].ConfDesc[Index]);\r
2162 }\r
2163 }\r
2164\r
2165 if (Xhc->UsbDevContext[SlotId].InputContext != NULL) {\r
2166 FreePages (Xhc->UsbDevContext[SlotId].InputContext, EFI_SIZE_TO_PAGES (sizeof (INPUT_CONTEXT)));\r
2167 }\r
2168\r
2169 if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {\r
2170 FreePages (Xhc->UsbDevContext[SlotId].OutputContext, EFI_SIZE_TO_PAGES (sizeof (DEVICE_CONTEXT)));\r
2171 }\r
2172 //\r
2173 // Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established\r
2174 // asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to\r
2175 // remove urb from XHCI's asynchronous transfer list.\r
2176 //\r
2177 Xhc->UsbDevContext[SlotId].Enabled = FALSE;\r
2178 Xhc->UsbDevContext[SlotId].SlotId = 0;\r
2179\r
2180 return Status;\r
2181}\r
2182\r
2183/**\r
2184 Disable the specified device slot.\r
2185\r
2186 @param Xhc The XHCI Instance.\r
2187 @param SlotId The slot id to be disabled.\r
2188\r
2189 @retval EFI_SUCCESS Successfully disable the device slot.\r
2190\r
2191**/\r
2192EFI_STATUS\r
2193EFIAPI\r
2194XhcDisableSlotCmd64 (\r
2195 IN USB_XHCI_INSTANCE *Xhc,\r
2196 IN UINT8 SlotId\r
2197 )\r
2198{\r
2199 EFI_STATUS Status;\r
2200 TRB_TEMPLATE *EvtTrb;\r
2201 CMD_TRB_DISABLE_SLOT CmdTrbDisSlot;\r
2202 UINT8 Index;\r
2203 VOID *RingSeg;\r
2204\r
2205 //\r
2206 // Disable the device slots occupied by these devices on its downstream ports.\r
2207 // Entry 0 is reserved.\r
2208 //\r
2209 for (Index = 0; Index < 255; Index++) {\r
2210 if (!Xhc->UsbDevContext[Index + 1].Enabled ||\r
2211 (Xhc->UsbDevContext[Index + 1].SlotId == 0) ||\r
2212 (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword)) {\r
2213 continue;\r
2214 }\r
2215\r
2216 Status = XhcDisableSlotCmd64 (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);\r
2217\r
2218 if (EFI_ERROR (Status)) {\r
2219 DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));\r
2220 Xhc->UsbDevContext[Index + 1].SlotId = 0;\r
2221 }\r
2222 }\r
2223\r
2224 //\r
2225 // Construct the disable slot command\r
2226 //\r
2227 DEBUG ((EFI_D_INFO, "Disable device slot %d!\n", SlotId));\r
2228\r
2229 ZeroMem (&CmdTrbDisSlot, sizeof (CmdTrbDisSlot));\r
2230 CmdTrbDisSlot.CycleBit = 1;\r
2231 CmdTrbDisSlot.Type = TRB_TYPE_DIS_SLOT;\r
2232 CmdTrbDisSlot.SlotId = SlotId;\r
2233 Status = XhcCmdTransfer (\r
2234 Xhc,\r
2235 (TRB_TEMPLATE *) (UINTN) &CmdTrbDisSlot,\r
2236 XHC_GENERIC_TIMEOUT,\r
2237 (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
2238 );\r
2239 ASSERT_EFI_ERROR(Status);\r
2240 //\r
2241 // Free the slot's device context entry\r
2242 //\r
2243 Xhc->DCBAA[SlotId] = 0;\r
2244\r
2245 //\r
2246 // Free the slot related data structure\r
2247 //\r
2248 for (Index = 0; Index < 31; Index++) {\r
2249 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] != NULL) {\r
2250 RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;\r
2251 if (RingSeg != NULL) {\r
2252 FreePages (RingSeg, EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER));\r
2253 }\r
2254 FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);\r
2255 }\r
2256 }\r
2257\r
2258 for (Index = 0; Index < Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations; Index++) {\r
2259 if (Xhc->UsbDevContext[SlotId].ConfDesc[Index] != NULL) {\r
2260 FreePool (Xhc->UsbDevContext[SlotId].ConfDesc[Index]);\r
2261 }\r
2262 }\r
2263\r
2264 if (Xhc->UsbDevContext[SlotId].InputContext != NULL) {\r
2265 FreePages (Xhc->UsbDevContext[SlotId].InputContext, EFI_SIZE_TO_PAGES (sizeof (INPUT_CONTEXT_64)));\r
2266 }\r
2267\r
2268 if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {\r
2269 FreePages (Xhc->UsbDevContext[SlotId].OutputContext, EFI_SIZE_TO_PAGES (sizeof (DEVICE_CONTEXT_64)));\r
2270 }\r
2271 //\r
2272 // Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established\r
2273 // asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to\r
2274 // remove urb from XHCI's asynchronous transfer list.\r
2275 //\r
2276 Xhc->UsbDevContext[SlotId].Enabled = FALSE;\r
2277 Xhc->UsbDevContext[SlotId].SlotId = 0;\r
2278\r
2279 return Status;\r
2280}\r
2281\r
2282\r
2283/**\r
2284 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r
2285\r
2286 @param Xhc The XHCI Instance.\r
2287 @param SlotId The slot id to be configured.\r
2288 @param DeviceSpeed The device's speed.\r
2289 @param ConfigDesc The pointer to the usb device configuration descriptor.\r
2290\r
2291 @retval EFI_SUCCESS Successfully configure all the device endpoints.\r
2292\r
2293**/\r
2294EFI_STATUS\r
2295EFIAPI\r
2296XhcSetConfigCmd (\r
2297 IN USB_XHCI_INSTANCE *Xhc,\r
2298 IN UINT8 SlotId,\r
2299 IN UINT8 DeviceSpeed,\r
2300 IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r
2301 )\r
2302{\r
2303 EFI_STATUS Status;\r
2304\r
2305 USB_INTERFACE_DESCRIPTOR *IfDesc;\r
2306 USB_ENDPOINT_DESCRIPTOR *EpDesc;\r
2307 UINT8 Index;\r
2308 UINTN NumEp;\r
2309 UINTN EpIndex;\r
2310 UINT8 EpAddr;\r
2311 UINT8 Direction;\r
2312 UINT8 Dci;\r
2313 UINT8 MaxDci;\r
2314 UINT32 PhyAddr;\r
2315 UINT8 Interval;\r
2316\r
2317 TRANSFER_RING *EndpointTransferRing;\r
2318 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;\r
2319 INPUT_CONTEXT *InputContext;\r
2320 DEVICE_CONTEXT *OutputContext;\r
2321 EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
2322 //\r
2323 // 4.6.6 Configure Endpoint\r
2324 //\r
2325 InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r
2326 OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;\r
2327 ZeroMem (InputContext, sizeof (INPUT_CONTEXT));\r
2328 CopyMem (&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT));\r
2329\r
2330 ASSERT (ConfigDesc != NULL);\r
2331\r
2332 MaxDci = 0;\r
2333\r
2334 IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);\r
2335 for (Index = 0; Index < ConfigDesc->NumInterfaces; Index++) {\r
2336 while (IfDesc->DescriptorType != USB_DESC_TYPE_INTERFACE) {\r
2337 IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);\r
2338 }\r
2339\r
2340 NumEp = IfDesc->NumEndpoints;\r
2341\r
2342 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDesc + 1);\r
2343 for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {\r
2344 while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {\r
2345 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
2346 }\r
2347\r
2348 EpAddr = (UINT8)(EpDesc->EndpointAddress & 0x0F);\r
2349 Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);\r
2350\r
2351 Dci = XhcEndpointToDci (EpAddr, Direction);\r
2352 ASSERT (Dci < 32);\r
2353 if (Dci > MaxDci) {\r
2354 MaxDci = Dci;\r
2355 }\r
2356\r
2357 InputContext->InputControlContext.Dword2 |= (BIT0 << Dci);\r
2358 InputContext->EP[Dci-1].MaxPacketSize = EpDesc->MaxPacketSize;\r
2359\r
2360 if (DeviceSpeed == EFI_USB_SPEED_SUPER) {\r
2361 //\r
2362 // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.\r
2363 //\r
2364 InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r
2365 } else {\r
2366 InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r
2367 }\r
2368\r
2369 switch (EpDesc->Attributes & USB_ENDPOINT_TYPE_MASK) {\r
2370 case USB_ENDPOINT_BULK:\r
2371 if (Direction == EfiUsbDataIn) {\r
2372 InputContext->EP[Dci-1].CErr = 3;\r
2373 InputContext->EP[Dci-1].EPType = ED_BULK_IN;\r
2374 } else {\r
2375 InputContext->EP[Dci-1].CErr = 3;\r
2376 InputContext->EP[Dci-1].EPType = ED_BULK_OUT;\r
2377 }\r
2378\r
2379 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r
2380 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {\r
2381 EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));\r
2382 Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;\r
2383 CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);\r
2384 }\r
2385\r
2386 break;\r
2387 case USB_ENDPOINT_ISO:\r
2388 if (Direction == EfiUsbDataIn) {\r
2389 InputContext->EP[Dci-1].CErr = 0;\r
2390 InputContext->EP[Dci-1].EPType = ED_ISOCH_IN;\r
2391 } else {\r
2392 InputContext->EP[Dci-1].CErr = 0;\r
2393 InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;\r
2394 }\r
2395 break;\r
2396 case USB_ENDPOINT_INTERRUPT:\r
2397 if (Direction == EfiUsbDataIn) {\r
2398 InputContext->EP[Dci-1].CErr = 3;\r
2399 InputContext->EP[Dci-1].EPType = ED_INTERRUPT_IN;\r
2400 } else {\r
2401 InputContext->EP[Dci-1].CErr = 3;\r
2402 InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;\r
2403 }\r
2404 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r
2405 InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;\r
2406 //\r
2407 // Get the bInterval from descriptor and init the the interval field of endpoint context\r
2408 //\r
2409 if ((DeviceSpeed == EFI_USB_SPEED_FULL) || (DeviceSpeed == EFI_USB_SPEED_LOW)) {\r
2410 Interval = EpDesc->Interval;\r
2411 //\r
2412 // Hard code the interval to MAX first, need calculate through the bInterval field of Endpoint descriptor.\r
2413 //\r
2414 InputContext->EP[Dci-1].Interval = 6;\r
2415 } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {\r
2416 Interval = EpDesc->Interval;\r
2417 ASSERT (Interval >= 1 && Interval <= 16);\r
2418 //\r
2419 // Refer to XHCI 1.0 spec section 6.2.3.6, table 61\r
2420 //\r
2421 InputContext->EP[Dci-1].Interval = Interval - 1;\r
2422 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r
2423 InputContext->EP[Dci-1].MaxESITPayload = 0x0002;\r
2424 InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r
2425 InputContext->EP[Dci-1].CErr = 3;\r
2426 }\r
2427\r
2428 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {\r
2429 EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));\r
2430 Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;\r
2431 CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);\r
2432 }\r
2433 break;\r
2434\r
2435 case USB_ENDPOINT_CONTROL:\r
2436 default:\r
2437 ASSERT (0);\r
2438 break;\r
2439 }\r
2440\r
2441 PhyAddr = XHC_LOW_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0);\r
2442 PhyAddr &= ~(0x0F);\r
2443 PhyAddr |= ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;\r
2444 InputContext->EP[Dci-1].PtrLo = PhyAddr;\r
2445 InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0);\r
2446\r
2447 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
2448 }\r
2449 IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);\r
2450 }\r
2451\r
2452 InputContext->InputControlContext.Dword2 |= BIT0;\r
2453 InputContext->Slot.ContextEntries = MaxDci;\r
2454 //\r
2455 // configure endpoint\r
2456 //\r
2457 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));\r
2458 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (InputContext);\r
2459 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (InputContext);\r
2460 CmdTrbCfgEP.CycleBit = 1;\r
2461 CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;\r
2462 CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r
2463 DEBUG ((EFI_D_INFO, "Configure Endpoint\n"));\r
2464 Status = XhcCmdTransfer (\r
2465 Xhc,\r
2466 (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,\r
2467 XHC_GENERIC_TIMEOUT,\r
2468 (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
2469 );\r
2470 ASSERT_EFI_ERROR(Status);\r
2471\r
2472 return Status;\r
2473}\r
2474\r
2475/**\r
2476 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r
2477\r
2478 @param Xhc The XHCI Instance.\r
2479 @param SlotId The slot id to be configured.\r
2480 @param DeviceSpeed The device's speed.\r
2481 @param ConfigDesc The pointer to the usb device configuration descriptor.\r
2482\r
2483 @retval EFI_SUCCESS Successfully configure all the device endpoints.\r
2484\r
2485**/\r
2486EFI_STATUS\r
2487EFIAPI\r
2488XhcSetConfigCmd64 (\r
2489 IN USB_XHCI_INSTANCE *Xhc,\r
2490 IN UINT8 SlotId,\r
2491 IN UINT8 DeviceSpeed,\r
2492 IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r
2493 )\r
2494{\r
2495 EFI_STATUS Status;\r
2496\r
2497 USB_INTERFACE_DESCRIPTOR *IfDesc;\r
2498 USB_ENDPOINT_DESCRIPTOR *EpDesc;\r
2499 UINT8 Index;\r
2500 UINTN NumEp;\r
2501 UINTN EpIndex;\r
2502 UINT8 EpAddr;\r
2503 UINT8 Direction;\r
2504 UINT8 Dci;\r
2505 UINT8 MaxDci;\r
2506 UINT32 PhyAddr;\r
2507 UINT8 Interval;\r
2508\r
2509 TRANSFER_RING *EndpointTransferRing;\r
2510 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;\r
2511 INPUT_CONTEXT_64 *InputContext;\r
2512 DEVICE_CONTEXT_64 *OutputContext;\r
2513 EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
2514 //\r
2515 // 4.6.6 Configure Endpoint\r
2516 //\r
2517 InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r
2518 OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;\r
2519 ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));\r
2520 CopyMem (&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT_64));\r
2521\r
2522 ASSERT (ConfigDesc != NULL);\r
2523\r
2524 MaxDci = 0;\r
2525\r
2526 IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);\r
2527 for (Index = 0; Index < ConfigDesc->NumInterfaces; Index++) {\r
2528 while (IfDesc->DescriptorType != USB_DESC_TYPE_INTERFACE) {\r
2529 IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);\r
2530 }\r
2531\r
2532 NumEp = IfDesc->NumEndpoints;\r
2533\r
2534 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDesc + 1);\r
2535 for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {\r
2536 while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {\r
2537 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
2538 }\r
2539\r
2540 EpAddr = (UINT8)(EpDesc->EndpointAddress & 0x0F);\r
2541 Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);\r
2542\r
2543 Dci = XhcEndpointToDci (EpAddr, Direction);\r
2544 ASSERT (Dci < 32);\r
2545 if (Dci > MaxDci) {\r
2546 MaxDci = Dci;\r
2547 }\r
2548\r
2549 InputContext->InputControlContext.Dword2 |= (BIT0 << Dci);\r
2550 InputContext->EP[Dci-1].MaxPacketSize = EpDesc->MaxPacketSize;\r
2551\r
2552 if (DeviceSpeed == EFI_USB_SPEED_SUPER) {\r
2553 //\r
2554 // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.\r
2555 //\r
2556 InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r
2557 } else {\r
2558 InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r
2559 }\r
2560\r
2561 switch (EpDesc->Attributes & USB_ENDPOINT_TYPE_MASK) {\r
2562 case USB_ENDPOINT_BULK:\r
2563 if (Direction == EfiUsbDataIn) {\r
2564 InputContext->EP[Dci-1].CErr = 3;\r
2565 InputContext->EP[Dci-1].EPType = ED_BULK_IN;\r
2566 } else {\r
2567 InputContext->EP[Dci-1].CErr = 3;\r
2568 InputContext->EP[Dci-1].EPType = ED_BULK_OUT;\r
2569 }\r
2570\r
2571 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r
2572 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {\r
2573 EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));\r
2574 Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;\r
2575 CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);\r
2576 }\r
2577\r
2578 break;\r
2579 case USB_ENDPOINT_ISO:\r
2580 if (Direction == EfiUsbDataIn) {\r
2581 InputContext->EP[Dci-1].CErr = 0;\r
2582 InputContext->EP[Dci-1].EPType = ED_ISOCH_IN;\r
2583 } else {\r
2584 InputContext->EP[Dci-1].CErr = 0;\r
2585 InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;\r
2586 }\r
2587 break;\r
2588 case USB_ENDPOINT_INTERRUPT:\r
2589 if (Direction == EfiUsbDataIn) {\r
2590 InputContext->EP[Dci-1].CErr = 3;\r
2591 InputContext->EP[Dci-1].EPType = ED_INTERRUPT_IN;\r
2592 } else {\r
2593 InputContext->EP[Dci-1].CErr = 3;\r
2594 InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;\r
2595 }\r
2596 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r
2597 InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;\r
2598 //\r
2599 // Get the bInterval from descriptor and init the the interval field of endpoint context\r
2600 //\r
2601 if ((DeviceSpeed == EFI_USB_SPEED_FULL) || (DeviceSpeed == EFI_USB_SPEED_LOW)) {\r
2602 Interval = EpDesc->Interval;\r
2603 //\r
2604 // Hard code the interval to MAX first, need calculate through the bInterval field of Endpoint descriptor.\r
2605 //\r
2606 InputContext->EP[Dci-1].Interval = 6;\r
2607 } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {\r
2608 Interval = EpDesc->Interval;\r
2609 ASSERT (Interval >= 1 && Interval <= 16);\r
2610 //\r
2611 // Refer to XHCI 1.0 spec section 6.2.3.6, table 61\r
2612 //\r
2613 InputContext->EP[Dci-1].Interval = Interval - 1;\r
2614 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r
2615 InputContext->EP[Dci-1].MaxESITPayload = 0x0002;\r
2616 InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r
2617 InputContext->EP[Dci-1].CErr = 3;\r
2618 }\r
2619\r
2620 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {\r
2621 EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));\r
2622 Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;\r
2623 CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);\r
2624 }\r
2625 break;\r
2626\r
2627 case USB_ENDPOINT_CONTROL:\r
2628 default:\r
2629 ASSERT (0);\r
2630 break;\r
2631 }\r
2632\r
2633 PhyAddr = XHC_LOW_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0);\r
2634 PhyAddr &= ~(0x0F);\r
2635 PhyAddr |= ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;\r
2636 InputContext->EP[Dci-1].PtrLo = PhyAddr;\r
2637 InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0);\r
2638\r
2639 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
2640 }\r
2641 IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);\r
2642 }\r
2643\r
2644 InputContext->InputControlContext.Dword2 |= BIT0;\r
2645 InputContext->Slot.ContextEntries = MaxDci;\r
2646 //\r
2647 // configure endpoint\r
2648 //\r
2649 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));\r
2650 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (InputContext);\r
2651 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (InputContext);\r
2652 CmdTrbCfgEP.CycleBit = 1;\r
2653 CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;\r
2654 CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r
2655 DEBUG ((EFI_D_INFO, "Configure Endpoint\n"));\r
2656 Status = XhcCmdTransfer (\r
2657 Xhc,\r
2658 (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,\r
2659 XHC_GENERIC_TIMEOUT,\r
2660 (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
2661 );\r
2662 ASSERT_EFI_ERROR(Status);\r
2663\r
2664 return Status;\r
2665}\r
2666\r
2667\r
2668/**\r
2669 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.\r
2670\r
2671 @param Xhc The XHCI Instance.\r
2672 @param SlotId The slot id to be evaluated.\r
2673 @param MaxPacketSize The max packet size supported by the device control transfer.\r
2674\r
2675 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.\r
2676\r
2677**/\r
2678EFI_STATUS\r
2679EFIAPI\r
2680XhcEvaluateContext (\r
2681 IN USB_XHCI_INSTANCE *Xhc,\r
2682 IN UINT8 SlotId,\r
2683 IN UINT32 MaxPacketSize\r
2684 )\r
2685{\r
2686 EFI_STATUS Status;\r
2687 CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu;\r
2688 EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
2689 INPUT_CONTEXT *InputContext;\r
2690\r
2691 ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);\r
2692\r
2693 //\r
2694 // 4.6.7 Evaluate Context\r
2695 //\r
2696 InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r
2697 ZeroMem (InputContext, sizeof (INPUT_CONTEXT));\r
2698\r
2699 InputContext->InputControlContext.Dword2 |= BIT1;\r
2700 InputContext->EP[0].MaxPacketSize = MaxPacketSize;\r
2701\r
2702 ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));\r
2703 CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (InputContext);\r
2704 CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (InputContext);\r
2705 CmdTrbEvalu.CycleBit = 1;\r
2706 CmdTrbEvalu.Type = TRB_TYPE_EVALU_CONTXT;\r
2707 CmdTrbEvalu.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r
2708 DEBUG ((EFI_D_INFO, "Evaluate context\n"));\r
2709 Status = XhcCmdTransfer (\r
2710 Xhc,\r
2711 (TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,\r
2712 XHC_GENERIC_TIMEOUT,\r
2713 (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
2714 );\r
2715 ASSERT (!EFI_ERROR(Status));\r
2716\r
2717 return Status;\r
2718}\r
2719\r
2720/**\r
2721 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.\r
2722\r
2723 @param Xhc The XHCI Instance.\r
2724 @param SlotId The slot id to be evaluated.\r
2725 @param MaxPacketSize The max packet size supported by the device control transfer.\r
2726\r
2727 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.\r
2728\r
2729**/\r
2730EFI_STATUS\r
2731EFIAPI\r
2732XhcEvaluateContext64 (\r
2733 IN USB_XHCI_INSTANCE *Xhc,\r
2734 IN UINT8 SlotId,\r
2735 IN UINT32 MaxPacketSize\r
2736 )\r
2737{\r
2738 EFI_STATUS Status;\r
2739 CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu;\r
2740 EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
2741 INPUT_CONTEXT_64 *InputContext;\r
2742\r
2743 ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);\r
2744\r
2745 //\r
2746 // 4.6.7 Evaluate Context\r
2747 //\r
2748 InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r
2749 ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));\r
2750\r
2751 InputContext->InputControlContext.Dword2 |= BIT1;\r
2752 InputContext->EP[0].MaxPacketSize = MaxPacketSize;\r
2753\r
2754 ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));\r
2755 CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (InputContext);\r
2756 CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (InputContext);\r
2757 CmdTrbEvalu.CycleBit = 1;\r
2758 CmdTrbEvalu.Type = TRB_TYPE_EVALU_CONTXT;\r
2759 CmdTrbEvalu.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r
2760 DEBUG ((EFI_D_INFO, "Evaluate context\n"));\r
2761 Status = XhcCmdTransfer (\r
2762 Xhc,\r
2763 (TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,\r
2764 XHC_GENERIC_TIMEOUT,\r
2765 (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
2766 );\r
2767 ASSERT (!EFI_ERROR(Status));\r
2768\r
2769 return Status;\r
2770}\r
2771\r
2772\r
2773/**\r
2774 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.\r
2775\r
2776 @param Xhc The XHCI Instance.\r
2777 @param SlotId The slot id to be configured.\r
2778 @param PortNum The total number of downstream port supported by the hub.\r
2779 @param TTT The TT think time of the hub device.\r
2780 @param MTT The multi-TT of the hub device.\r
2781\r
2782 @retval EFI_SUCCESS Successfully configure the hub device's slot context.\r
2783\r
2784**/\r
2785EFI_STATUS\r
2786XhcConfigHubContext (\r
2787 IN USB_XHCI_INSTANCE *Xhc,\r
2788 IN UINT8 SlotId,\r
2789 IN UINT8 PortNum,\r
2790 IN UINT8 TTT,\r
2791 IN UINT8 MTT\r
2792 )\r
2793{\r
2794 EFI_STATUS Status;\r
2795\r
2796 EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
2797 INPUT_CONTEXT *InputContext;\r
2798 DEVICE_CONTEXT *OutputContext;\r
2799 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;\r
2800\r
2801 ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);\r
2802 InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r
2803 OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;\r
2804\r
2805 //\r
2806 // 4.6.7 Evaluate Context\r
2807 //\r
2808 ZeroMem (InputContext, sizeof (INPUT_CONTEXT));\r
2809\r
2810 InputContext->InputControlContext.Dword2 |= BIT0;\r
2811\r
2812 //\r
2813 // Copy the slot context from OutputContext to Input context\r
2814 //\r
2815 CopyMem(&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT));\r
2816 InputContext->Slot.Hub = 1;\r
2817 InputContext->Slot.PortNum = PortNum;\r
2818 InputContext->Slot.TTT = TTT;\r
2819 InputContext->Slot.MTT = MTT;\r
2820\r
2821 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));\r
2822 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (InputContext);\r
2823 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (InputContext);\r
2824 CmdTrbCfgEP.CycleBit = 1;\r
2825 CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;\r
2826 CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r
2827 DEBUG ((EFI_D_INFO, "Configure Hub Slot Context\n"));\r
2828 Status = XhcCmdTransfer (\r
2829 Xhc,\r
2830 (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,\r
2831 XHC_GENERIC_TIMEOUT,\r
2832 (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
2833 );\r
2834 ASSERT (!EFI_ERROR(Status));\r
2835\r
2836 return Status;\r
2837}\r
2838\r
2839/**\r
2840 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.\r
2841\r
2842 @param Xhc The XHCI Instance.\r
2843 @param SlotId The slot id to be configured.\r
2844 @param PortNum The total number of downstream port supported by the hub.\r
2845 @param TTT The TT think time of the hub device.\r
2846 @param MTT The multi-TT of the hub device.\r
2847\r
2848 @retval EFI_SUCCESS Successfully configure the hub device's slot context.\r
2849\r
2850**/\r
2851EFI_STATUS\r
2852XhcConfigHubContext64 (\r
2853 IN USB_XHCI_INSTANCE *Xhc,\r
2854 IN UINT8 SlotId,\r
2855 IN UINT8 PortNum,\r
2856 IN UINT8 TTT,\r
2857 IN UINT8 MTT\r
2858 )\r
2859{\r
2860 EFI_STATUS Status;\r
2861\r
2862 EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
2863 INPUT_CONTEXT_64 *InputContext;\r
2864 DEVICE_CONTEXT_64 *OutputContext;\r
2865 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;\r
2866\r
2867 ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);\r
2868 InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r
2869 OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;\r
2870\r
2871 //\r
2872 // 4.6.7 Evaluate Context\r
2873 //\r
2874 ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));\r
2875\r
2876 InputContext->InputControlContext.Dword2 |= BIT0;\r
2877\r
2878 //\r
2879 // Copy the slot context from OutputContext to Input context\r
2880 //\r
2881 CopyMem(&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT_64));\r
2882 InputContext->Slot.Hub = 1;\r
2883 InputContext->Slot.PortNum = PortNum;\r
2884 InputContext->Slot.TTT = TTT;\r
2885 InputContext->Slot.MTT = MTT;\r
2886\r
2887 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));\r
2888 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (InputContext);\r
2889 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (InputContext);\r
2890 CmdTrbCfgEP.CycleBit = 1;\r
2891 CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;\r
2892 CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r
2893 DEBUG ((EFI_D_INFO, "Configure Hub Slot Context\n"));\r
2894 Status = XhcCmdTransfer (\r
2895 Xhc,\r
2896 (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,\r
2897 XHC_GENERIC_TIMEOUT,\r
2898 (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
2899 );\r
2900 ASSERT (!EFI_ERROR(Status));\r
2901\r
2902 return Status;\r
2903}\r
2904\r
2905\r
EFI Development Kit II mirror for PVE