[mirror_edk2.git] / MdePkg / Include / IndustryStandard / Pal.h

/** @file\r
  Main PAL API's defined in IPF PAL Spec.\r
\r
  Copyright (c) 2006 - 2007, Intel Corporation\r
  All rights reserved. This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
  Module Name:  PalApi.h\r
\r
**/\r
\r
#ifndef __PAL_API_H__\r
#define __PAL_API_H__\r
\r
//\r
// IPF Specific Functions\r
//\r
#ifdef _MSC_VER\r
//\r
// Disabling bitfield type checking warnings.\r
//\r
#pragma warning ( disable : 4214 )\r
#endif\r
  \r
typedef struct {\r
  UINT64                    Status;\r
  UINT64                    r9;\r
  UINT64                    r10;\r
  UINT64                    r11;\r
} PAL_CALL_RETURN;\r
\r
\r
\r
//\r
// CacheType of PAL_CACHE_FLUSH.\r
//\r
#define PAL_CACHE_FLUSH_INSTRUCTION_ALL 	1\r
#define PAL_CACHE_FLUSH_DATA_ALL 					2\r
#define PAL_CACHE_FLUSH_ALL								3\r
#define PAL_CACHE_FLUSH_SYNC_TO_DATA   		4\r
\r
\r
//\r
// Bitmask of Opearation of PAL_CACHE_FLUSH.\r
// \r
#define PAL_CACHE_FLUSH_INVIDED_LINES			BIT0\r
#define PAL_CACHE_FLUSH_PROBE_INTERRUPT		BIT1\r
\r
/**\r
   \r
  Flush the instruction or data caches. It is required by IPF.\r
  The PAL procedure supports the Static Registers calling\r
  convention. It could be called at virtual mode and physical\r
  mode.\r
\r
  @param Index 							Index of PAL_CACHE_FLUSH within the\r
														list of PAL procedures.\r
  \r
  @param CacheType					Unsigned 64-bit integer indicating\r
														which cache to flush.\r
\r
  @param Operation 					Formatted bit vector indicating the\r
														operation of this call.\r
\r
  @param ProgressIndicator  Unsigned 64-bit integer specifying\r
                            the starting position of the flush\r
                            operation.\r
  \r
  @return R9			Unsigned 64-bit integer specifying the vector\r
									number of the pending interrupt.\r
  \r
  @return R10			Unsigned 64-bit integer specifying the\r
                  starting position of the flush operation.\r
  \r
  @return R11			Unsigned 64-bit integer specifying the vector\r
									number of the pending interrupt.\r
  \r
  @return Status	2 - Call completed without error, but a PMI\r
                  was taken during the execution of this\r
                  procedure.\r
\r
  @return Status	1 - Call has not completed flushing due to\r
                  a pending interrupt.\r
\r
  @return Status  0 - Call completed without error\r
\r
  @return Status  -2 - Invalid argument\r
\r
  @return Status  -3 - Call completed with error\r
   \r
**/\r
#define PAL_CACHE_FLUSH 	1\r
\r
\r
//\r
// Attributes of PAL_CACHE_CONFIG_INFO1\r
// \r
#define PAL_CACHE_ATTR_WT 	0\r
#define PAL_CACHE_ATTR_WB		1\r
\r
//\r
// PAL_CACHE_CONFIG_INFO1.StoreHint\r
// \r
#define PAL_CACHE_STORE_TEMPORAL			0\r
#define PAL_CACHE_STORE_NONE_TEMPORAL	3\r
\r
//\r
// PAL_CACHE_CONFIG_INFO1.StoreHint\r
// \r
#define PAL_CACHE_STORE_TEMPORAL_LVL_1				0\r
#define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL	3\r
\r
//\r
// PAL_CACHE_CONFIG_INFO1.StoreHint\r
// \r
#define PAL_CACHE_LOAD_TEMPORAL_LVL_1					0\r
#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1		1\r
#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL	3\r
\r
//\r
// Detail the characteristics of a given processor controlled\r
// cache in the cache hierarchy.\r
// \r
typedef struct {\r
	UINT64	IsUnified 	: 1;\r
	UINT64	Attributes	:	2;\r
	UINT64	Associativity:8;\r
	UINT64	LineSize:8;\r
	UINT64	Stride:8;\r
	UINT64	StoreLatency:8;\r
	UINT64	StoreHint:8;\r
	UINT64	LoadHint:8;\r
} PAL_CACHE_INFO_RETURN1;\r
\r
//\r
// Detail the characteristics of a given processor controlled\r
// cache in the cache hierarchy.\r
// \r
typedef struct {\r
	UINT64	CacheSize:32;\r
	UINT64	AliasBoundary:8;\r
	UINT64	TagLsBits:8;\r
	UINT64	TagMsBits:8;\r
} PAL_CACHE_INFO_RETURN2;\r
\r
/**\r
   \r
  Return detailed instruction or data cache information. It is\r
  required by IPF. The PAL procedure supports the Static\r
  Registers calling convention. It could be called at virtual\r
  mode and physical mode.\r
  \r
  @param Index 				Index of PAL_CACHE_INFO within the list of\r
											PAL procedures.\r
  \r
  @param CacheLevel		Unsigned 64-bit integer specifying the\r
                      level in the cache hierarchy for which\r
                      information is requested. This value must\r
                      be between 0 and one less than the value\r
                      returned in the cache_levels return value\r
                      from PAL_CACHE_SUMMARY.\r
  \r
  @param CacheType    Unsigned 64-bit integer with a value of 1\r
                      for instruction cache and 2 for data or\r
                      unified cache. All other values are\r
                      reserved.\r
  \r
  @param Reserved 		Should be 0.\r
  \r
  \r
  @return R9			Detail the characteristics of a given\r
                  processor controlled cache in the cache\r
                  hierarchy. See PAL_CACHE_INFO_RETURN1.\r
  \r
  @return R10			Detail the characteristics of a given\r
                  processor controlled cache in the cache\r
                  hierarchy. See PAL_CACHE_INFO_RETURN2.\r
  \r
  @return R11			Reserved with 0.\r
  \r
  \r
  @return Status  0 - Call completed without error\r
\r
  @return Status  -2 - Invalid argument\r
\r
  @return Status  -3 - Call completed with error\r
   \r
**/\r
#define PAL_CACHE_INFO 		2\r
\r
\r
\r
//\r
// Level of PAL_CACHE_INIT.\r
// \r
#define PAL_CACHE_INIT_ALL	0xffffffffffffffffULL\r
\r
//\r
// Restrict of PAL_CACHE_INIT.\r
// \r
#define PAL_CACHE_INIT_NO_RESTRICT	0\r
#define PAL_CACHE_INIT_RESTRICTED		1\r
\r
/**\r
   \r
  Initialize the instruction or data caches. It is required by\r
  IPF. The PAL procedure supports the Static Registers calling\r
  convention. It could be called at physical mode.\r
\r
  @param Index 	Index of PAL_CACHE_INIT within the list of PAL\r
                procedures.\r
  \r
  @param Level 	Unsigned 64-bit integer containing the level of\r
                cache to initialize. If the cache level can be\r
                initialized independently, only that level will\r
                be initialized. Otherwise\r
                implementation-dependent side-effects will\r
                occur.\r
  \r
  @param CacheType 	Unsigned 64-bit integer with a value of 1 to\r
                    initialize the instruction cache, 2 to\r
                    initialize the data cache, or 3 to\r
                    initialize both. All other values are\r
                    reserved.\r
\r
  @param Restrict 	Unsigned 64-bit integer with a value of 0 or\r
                    1. All other values are reserved. If\r
                    restrict is 1 and initializing the specified\r
                    level and cache_type of the cache would\r
                    cause side-effects, PAL_CACHE_INIT will\r
                    return -4 instead of initializing the cache.\r
 \r
  \r
  @return Status  0 - Call completed without error\r
\r
  @return Status  -2 - Invalid argument\r
\r
  @return Status  -3 - Call completed with error.\r
  \r
  @return Status  -4 - Call could not initialize the specified\r
                  level and cache_type of the cache without\r
									side-effects and restrict was 1.  \r
   \r
**/\r
#define PAL_CACHE_INIT 		3 \r
\r
\r
//\r
// PAL_CACHE_PROTECTION.Method.\r
// \r
#define PAL_CACHE_PROTECTION_NONE_PROTECT		0\r
#define PAL_CACHE_PROTECTION_ODD_PROTECT		1\r
#define PAL_CACHE_PROTECTION_EVEN_PROTECT		2\r
#define PAL_CACHE_PROTECTION_ECC_PROTECT		3\r
\r
\r
\r
//\r
// PAL_CACHE_PROTECTION.TagOrData.\r
// \r
#define PAL_CACHE_PROTECTION_PROTECT_DATA		0\r
#define PAL_CACHE_PROTECTION_PROTECT_TAG		1\r
#define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA		2\r
#define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG		3\r
\r
//\r
// 32-bit protection information structures.\r
// \r
typedef struct {\r
	UINT32 	DataBits:8;\r
	UINT32 	TagProtLsb:6;\r
	UINT32	TagProtMsb:6;\r
	UINT32	ProtBits:6;\r
	UINT32	Method:4;\r
	UINT32	TagOrData:2;\r
} PAL_CACHE_PROTECTION;\r
\r
/**\r
   \r
  Return instruction or data cache protection information. It is\r
  required by IPF. The PAL procedure supports the Static\r
  Registers calling convention. It could be called at physical\r
  mode and Virtual mode.\r
\r
  @param Index 	Index of PAL_CACHE_PROT_INFO within the list of\r
                PAL procedures.\r
\r
  @param CacheLevel	Unsigned 64-bit integer specifying the level\r
                    in the cache hierarchy for which information\r
                    is requested. This value must be between 0\r
                    and one less than the value returned in the\r
                    cache_levels return value from\r
                    PAL_CACHE_SUMMARY.\r
\r
  @param CacheType	Unsigned 64-bit integer with a value of 1\r
                    for instruction cache and 2 for data or\r
                    unified cache. All other values are\r
                    reserved.\r
  \r
  @return R9			Detail the characteristics of a given\r
                  processor controlled cache in the cache\r
                  hierarchy. See PAL_CACHE_PROTECTION[0..1].\r
  \r
  @return R10			Detail the characteristics of a given\r
                  processor controlled cache in the cache\r
                  hierarchy. See PAL_CACHE_PROTECTION[2..3].\r
  \r
  @return R11			Detail the characteristics of a given\r
                  processor controlled cache in the cache\r
                  hierarchy. See PAL_CACHE_PROTECTION[4..5].\r
  \r
  \r
  @return Status  0 - Call completed without error\r
\r
  @return Status  -2 - Invalid argument\r
\r
  @return Status  -3 - Call completed with error.\r
   \r
**/\r
#define PAL_CACHE_PROT_INFO 		38\r
\r
\r
\r
\r
\r
\r
\r
///\r
// ?????????\r
\r
\r
\r
/**\r
   \r
  Returns information on which logical processors share caches.\r
  It is optional.\r
\r
  @param CallingConvention  Static Registers\r
\r
  @param Mode               Physical/Virtual\r
   \r
**/\r
#define PAL_CACHE_SHARED_INFO 	43\r
\r
\r
/**\r
   \r
  Return a summary of the cache hierarchy. It is required by\r
  IPF.\r
\r
  @param CallingConvention  Static Registers\r
\r
  @param Mode               Physical/Virtual\r
   \r
**/\r
#define PAL_CACHE_SUMMARY		4\r
\r
/**\r
   \r
  Return a list of supported memory attributes.. It is required\r
  by IPF.\r
\r
  @param CallingConvention  Static Registers\r
\r
  @param Mode               Physical/Virtual\r
   \r
**/\r
#define PAL_MEM_ATTRIB 			5\r
\r
/**\r
   \r
  Used in architected sequence to transition pages from a\r
  cacheable, speculative attribute to an uncacheable attribute.\r
  It is required by IPF.\r
\r
  @param CallingConvention  Static Registers\r
\r
  @param Mode               Physical/Virtual\r
   \r
**/\r
#define PAL_PREFETCH_VISIBILITY 	41\r
\r
/**\r
   \r
  Return information needed for ptc.e instruction to purge\r
  entire TC. It is required by IPF.\r
\r
  @param CallingConvention  Static Registers\r
\r
  @param Mode               Physical/Virtual\r
   \r
**/\r
#define PAL_PTCE_INFO 		6\r
\r
/**\r
   \r
  Return detailed information about virtual memory features\r
  supported in the processor. It is required by IPF.\r
\r
  @param CallingConvention  Static Registers\r
\r
  @param Mode               Physical/Virtual\r
   \r
**/\r
#define PAL_VM_INFO 			7\r
\r
\r
/**\r
   \r
  Return virtual memory TC and hardware walker page sizes\r
  supported in the processor. It is required by IPF.\r
\r
  @param CallingConvention  Static Registers\r
\r
  @param Mode               Physical\r
   \r
**/\r
#define PAL_VM_PAGE_SIZE 34\r
\r
/**\r
   \r
  Return summary information about virtual memory features\r
  supported in the processor. It is required by IPF.\r
\r
  @param CallingConvention  Static Registers\r
\r
  @param Mode               Physical/Virtual\r
   \r
**/\r
#define PAL_VM_SUMMARY 	8\r
\r
/**\r
   \r
  Read contents of a translation register. It is required by\r
  IPF.\r
\r
  @param CallingConvention  Stacked Register\r
\r
  @param Mode               Physical\r
   \r
**/\r
#define PAL_VM_TR_READ 	261 \r
\r
/**\r
   \r
  Return configurable processor bus interface features and their\r
  current settings. It is required by IPF.\r
\r
  @param CallingConvention  Static Registers\r
\r
  @param Mode               Physical\r
   \r
**/\r
#define PAL_BUS_GET_FEATURES 9\r
\r
\r
/**\r
   \r
  Enable or disable configurable features in processor bus\r
  interface. It is required by IPF.\r
\r
  @param CallingConvention  Static Registers\r
\r
  @param Mode               Physical\r
   \r
**/\r
#define PAL_BUS_SET_FEATURES 10\r
\r
\r
/**\r
   \r
  Return the number of instruction and data breakpoint\r
  registers. It is required by IPF.\r
\r
  @param CallingConvention  Static Registers\r
\r
  @param Mode               Physical/Virtual\r
   \r
**/\r
#define PAL_DEBUG_INFO 	11\r
\r
/**\r
   \r
Commit	Line	Data
	1	/** @file\r
	2	Main PAL API's defined in IPF PAL Spec.\r
	3	\r
	4	Copyright (c) 2006 - 2007, Intel Corporation\r
	5	All rights reserved. This program and the accompanying materials\r
	6	are licensed and made available under the terms and conditions of the BSD License\r
	7	which accompanies this distribution. The full text of the license may be found at\r
	8	http://opensource.org/licenses/bsd-license.php\r
	9	\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	12	\r
	13	Module Name: PalApi.h\r
	14	\r
	15	**/\r
	16	\r
	17	#ifndef __PAL_API_H__\r
	18	#define __PAL_API_H__\r
	19	\r
	20	//\r
	21	// IPF Specific Functions\r
	22	//\r
	23	#ifdef _MSC_VER\r
	24	//\r
	25	// Disabling bitfield type checking warnings.\r
	26	//\r
	27	#pragma warning ( disable : 4214 )\r
	28	#endif\r
	29	\r
	30	typedef struct {\r
	31	UINT64 Status;\r
	32	UINT64 r9;\r
	33	UINT64 r10;\r
	34	UINT64 r11;\r
	35	} PAL_CALL_RETURN;\r
	36	\r
	37	\r
	38	\r
	39	//\r
	40	// CacheType of PAL_CACHE_FLUSH.\r
	41	//\r
	42	#define PAL_CACHE_FLUSH_INSTRUCTION_ALL 1\r
	43	#define PAL_CACHE_FLUSH_DATA_ALL 2\r
	44	#define PAL_CACHE_FLUSH_ALL 3\r
	45	#define PAL_CACHE_FLUSH_SYNC_TO_DATA 4\r
	46	\r
	47	\r
	48	//\r
	49	// Bitmask of Opearation of PAL_CACHE_FLUSH.\r
	50	// \r
	51	#define PAL_CACHE_FLUSH_INVIDED_LINES BIT0\r
	52	#define PAL_CACHE_FLUSH_PROBE_INTERRUPT BIT1\r
	53	\r
	54	/**\r
	55	\r
	56	Flush the instruction or data caches. It is required by IPF.\r
	57	The PAL procedure supports the Static Registers calling\r
	58	convention. It could be called at virtual mode and physical\r
	59	mode.\r
	60	\r
	61	@param Index Index of PAL_CACHE_FLUSH within the\r
	62	list of PAL procedures.\r
	63	\r
	64	@param CacheType Unsigned 64-bit integer indicating\r
	65	which cache to flush.\r
	66	\r
	67	@param Operation Formatted bit vector indicating the\r
	68	operation of this call.\r
	69	\r
	70	@param ProgressIndicator Unsigned 64-bit integer specifying\r
	71	the starting position of the flush\r
	72	operation.\r
	73	\r
	74	@return R9 Unsigned 64-bit integer specifying the vector\r
	75	number of the pending interrupt.\r
	76	\r
	77	@return R10 Unsigned 64-bit integer specifying the\r
	78	starting position of the flush operation.\r
	79	\r
	80	@return R11 Unsigned 64-bit integer specifying the vector\r
	81	number of the pending interrupt.\r
	82	\r
	83	@return Status 2 - Call completed without error, but a PMI\r
	84	was taken during the execution of this\r
	85	procedure.\r
	86	\r
	87	@return Status 1 - Call has not completed flushing due to\r
	88	a pending interrupt.\r
	89	\r
	90	@return Status 0 - Call completed without error\r
	91	\r
	92	@return Status -2 - Invalid argument\r
	93	\r
	94	@return Status -3 - Call completed with error\r
	95	\r
	96	**/\r
	97	#define PAL_CACHE_FLUSH 1\r
	98	\r
	99	\r
	100	//\r
	101	// Attributes of PAL_CACHE_CONFIG_INFO1\r
	102	// \r
	103	#define PAL_CACHE_ATTR_WT 0\r
	104	#define PAL_CACHE_ATTR_WB 1\r
	105	\r
	106	//\r
	107	// PAL_CACHE_CONFIG_INFO1.StoreHint\r
	108	// \r
	109	#define PAL_CACHE_STORE_TEMPORAL 0\r
	110	#define PAL_CACHE_STORE_NONE_TEMPORAL 3\r
	111	\r
	112	//\r
	113	// PAL_CACHE_CONFIG_INFO1.StoreHint\r
	114	// \r
	115	#define PAL_CACHE_STORE_TEMPORAL_LVL_1 0\r
	116	#define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3\r
	117	\r
	118	//\r
	119	// PAL_CACHE_CONFIG_INFO1.StoreHint\r
	120	// \r
	121	#define PAL_CACHE_LOAD_TEMPORAL_LVL_1 0\r
	122	#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1 1\r
	123	#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL 3\r
	124	\r
	125	//\r
	126	// Detail the characteristics of a given processor controlled\r
	127	// cache in the cache hierarchy.\r
	128	// \r
	129	typedef struct {\r
	130	UINT64 IsUnified : 1;\r
	131	UINT64 Attributes : 2;\r
	132	UINT64 Associativity:8;\r
	133	UINT64 LineSize:8;\r
	134	UINT64 Stride:8;\r
	135	UINT64 StoreLatency:8;\r
	136	UINT64 StoreHint:8;\r
	137	UINT64 LoadHint:8;\r
	138	} PAL_CACHE_INFO_RETURN1;\r
	139	\r
	140	//\r
	141	// Detail the characteristics of a given processor controlled\r
	142	// cache in the cache hierarchy.\r
	143	// \r
	144	typedef struct {\r
	145	UINT64 CacheSize:32;\r
	146	UINT64 AliasBoundary:8;\r
	147	UINT64 TagLsBits:8;\r
	148	UINT64 TagMsBits:8;\r
	149	} PAL_CACHE_INFO_RETURN2;\r
	150	\r
	151	/**\r
	152	\r
	153	Return detailed instruction or data cache information. It is\r
	154	required by IPF. The PAL procedure supports the Static\r
	155	Registers calling convention. It could be called at virtual\r
	156	mode and physical mode.\r
	157	\r
	158	@param Index Index of PAL_CACHE_INFO within the list of\r
	159	PAL procedures.\r
	160	\r
	161	@param CacheLevel Unsigned 64-bit integer specifying the\r
	162	level in the cache hierarchy for which\r
	163	information is requested. This value must\r
	164	be between 0 and one less than the value\r
	165	returned in the cache_levels return value\r
	166	from PAL_CACHE_SUMMARY.\r
	167	\r
	168	@param CacheType Unsigned 64-bit integer with a value of 1\r
	169	for instruction cache and 2 for data or\r
	170	unified cache. All other values are\r
	171	reserved.\r
	172	\r
	173	@param Reserved Should be 0.\r
	174	\r
	175	\r
	176	@return R9 Detail the characteristics of a given\r
	177	processor controlled cache in the cache\r
	178	hierarchy. See PAL_CACHE_INFO_RETURN1.\r
	179	\r
	180	@return R10 Detail the characteristics of a given\r
	181	processor controlled cache in the cache\r
	182	hierarchy. See PAL_CACHE_INFO_RETURN2.\r
	183	\r
	184	@return R11 Reserved with 0.\r
	185	\r
	186	\r
	187	@return Status 0 - Call completed without error\r
	188	\r
	189	@return Status -2 - Invalid argument\r
	190	\r
	191	@return Status -3 - Call completed with error\r
	192	\r
	193	**/\r
	194	#define PAL_CACHE_INFO 2\r
	195	\r
	196	\r
	197	\r
	198	//\r
	199	// Level of PAL_CACHE_INIT.\r
	200	// \r
	201	#define PAL_CACHE_INIT_ALL 0xffffffffffffffffULL\r
	202	\r
	203	//\r
	204	// Restrict of PAL_CACHE_INIT.\r
	205	// \r
	206	#define PAL_CACHE_INIT_NO_RESTRICT 0\r
	207	#define PAL_CACHE_INIT_RESTRICTED 1\r
	208	\r
	209	/**\r
	210	\r
	211	Initialize the instruction or data caches. It is required by\r
	212	IPF. The PAL procedure supports the Static Registers calling\r
	213	convention. It could be called at physical mode.\r
	214	\r
	215	@param Index Index of PAL_CACHE_INIT within the list of PAL\r
	216	procedures.\r
	217	\r
	218	@param Level Unsigned 64-bit integer containing the level of\r
	219	cache to initialize. If the cache level can be\r
	220	initialized independently, only that level will\r
	221	be initialized. Otherwise\r
	222	implementation-dependent side-effects will\r
	223	occur.\r
	224	\r
	225	@param CacheType Unsigned 64-bit integer with a value of 1 to\r
	226	initialize the instruction cache, 2 to\r
	227	initialize the data cache, or 3 to\r
	228	initialize both. All other values are\r
	229	reserved.\r
	230	\r
	231	@param Restrict Unsigned 64-bit integer with a value of 0 or\r
	232	1. All other values are reserved. If\r
	233	restrict is 1 and initializing the specified\r
	234	level and cache_type of the cache would\r
	235	cause side-effects, PAL_CACHE_INIT will\r
	236	return -4 instead of initializing the cache.\r
	237	\r
	238	\r
	239	@return Status 0 - Call completed without error\r
	240	\r
	241	@return Status -2 - Invalid argument\r
	242	\r
	243	@return Status -3 - Call completed with error.\r
	244	\r
	245	@return Status -4 - Call could not initialize the specified\r
	246	level and cache_type of the cache without\r
	247	side-effects and restrict was 1. \r
	248	\r
	249	**/\r
	250	#define PAL_CACHE_INIT 3 \r
	251	\r
	252	\r
	253	//\r
	254	// PAL_CACHE_PROTECTION.Method.\r
	255	// \r
	256	#define PAL_CACHE_PROTECTION_NONE_PROTECT 0\r
	257	#define PAL_CACHE_PROTECTION_ODD_PROTECT 1\r
	258	#define PAL_CACHE_PROTECTION_EVEN_PROTECT 2\r
	259	#define PAL_CACHE_PROTECTION_ECC_PROTECT 3\r
	260	\r
	261	\r
	262	\r
	263	//\r
	264	// PAL_CACHE_PROTECTION.TagOrData.\r
	265	// \r
	266	#define PAL_CACHE_PROTECTION_PROTECT_DATA 0\r
	267	#define PAL_CACHE_PROTECTION_PROTECT_TAG 1\r
	268	#define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA 2\r
	269	#define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG 3\r
	270	\r
	271	//\r
	272	// 32-bit protection information structures.\r
	273	// \r
	274	typedef struct {\r
	275	UINT32 DataBits:8;\r
	276	UINT32 TagProtLsb:6;\r
	277	UINT32 TagProtMsb:6;\r
	278	UINT32 ProtBits:6;\r
	279	UINT32 Method:4;\r
	280	UINT32 TagOrData:2;\r
	281	} PAL_CACHE_PROTECTION;\r
	282	\r
	283	/**\r
	284	\r
	285	Return instruction or data cache protection information. It is\r
	286	required by IPF. The PAL procedure supports the Static\r
	287	Registers calling convention. It could be called at physical\r
	288	mode and Virtual mode.\r
	289	\r
	290	@param Index Index of PAL_CACHE_PROT_INFO within the list of\r
	291	PAL procedures.\r
	292	\r
	293	@param CacheLevel Unsigned 64-bit integer specifying the level\r
	294	in the cache hierarchy for which information\r
	295	is requested. This value must be between 0\r
	296	and one less than the value returned in the\r
	297	cache_levels return value from\r
	298	PAL_CACHE_SUMMARY.\r
	299	\r
	300	@param CacheType Unsigned 64-bit integer with a value of 1\r
	301	for instruction cache and 2 for data or\r
	302	unified cache. All other values are\r
	303	reserved.\r
	304	\r
	305	@return R9 Detail the characteristics of a given\r
	306	processor controlled cache in the cache\r
	307	hierarchy. See PAL_CACHE_PROTECTION[0..1].\r
	308	\r
	309	@return R10 Detail the characteristics of a given\r
	310	processor controlled cache in the cache\r
	311	hierarchy. See PAL_CACHE_PROTECTION[2..3].\r
	312	\r
	313	@return R11 Detail the characteristics of a given\r
	314	processor controlled cache in the cache\r
	315	hierarchy. See PAL_CACHE_PROTECTION[4..5].\r
	316	\r
	317	\r
	318	@return Status 0 - Call completed without error\r
	319	\r
	320	@return Status -2 - Invalid argument\r
	321	\r
	322	@return Status -3 - Call completed with error.\r
	323	\r
	324	**/\r
	325	#define PAL_CACHE_PROT_INFO 38\r
	326	\r
	327	\r
	328	\r
	329	\r
	330	\r
	331	\r
	332	\r
	333	///\r
	334	// ?????????\r
	335	\r
	336	\r
	337	\r
	338	/**\r
	339	\r
	340	Returns information on which logical processors share caches.\r
	341	It is optional.\r
	342	\r
	343	@param CallingConvention Static Registers\r
	344	\r
	345	@param Mode Physical/Virtual\r
	346	\r
	347	**/\r
	348	#define PAL_CACHE_SHARED_INFO 43\r
	349	\r
	350	\r
	351	/**\r
	352	\r
	353	Return a summary of the cache hierarchy. It is required by\r
	354	IPF.\r
	355	\r
	356	@param CallingConvention Static Registers\r
	357	\r
	358	@param Mode Physical/Virtual\r
	359	\r
	360	**/\r
	361	#define PAL_CACHE_SUMMARY 4\r
	362	\r
	363	/**\r
	364	\r
	365	Return a list of supported memory attributes.. It is required\r
	366	by IPF.\r
	367	\r
	368	@param CallingConvention Static Registers\r
	369	\r
	370	@param Mode Physical/Virtual\r
	371	\r
	372	**/\r
	373	#define PAL_MEM_ATTRIB 5\r
	374	\r
	375	/**\r
	376	\r
	377	Used in architected sequence to transition pages from a\r
	378	cacheable, speculative attribute to an uncacheable attribute.\r
	379	It is required by IPF.\r
	380	\r
	381	@param CallingConvention Static Registers\r
	382	\r
	383	@param Mode Physical/Virtual\r
	384	\r
	385	**/\r
	386	#define PAL_PREFETCH_VISIBILITY 41\r
	387	\r
	388	/**\r
	389	\r
	390	Return information needed for ptc.e instruction to purge\r
	391	entire TC. It is required by IPF.\r
	392	\r
	393	@param CallingConvention Static Registers\r
	394	\r
	395	@param Mode Physical/Virtual\r
	396	\r
	397	**/\r
	398	#define PAL_PTCE_INFO 6\r
	399	\r
	400	/**\r
	401	\r
	402	Return detailed information about virtual memory features\r
	403	supported in the processor. It is required by IPF.\r
	404	\r
	405	@param CallingConvention Static Registers\r
	406	\r
	407	@param Mode Physical/Virtual\r
	408	\r
	409	**/\r
	410	#define PAL_VM_INFO 7\r
	411	\r
	412	\r
	413	/**\r
	414	\r
	415	Return virtual memory TC and hardware walker page sizes\r
	416	supported in the processor. It is required by IPF.\r
	417	\r
	418	@param CallingConvention Static Registers\r
	419	\r
	420	@param Mode Physical\r
	421	\r
	422	**/\r
	423	#define PAL_VM_PAGE_SIZE 34\r
	424	\r
	425	/**\r
	426	\r
	427	Return summary information about virtual memory features\r
	428	supported in the processor. It is required by IPF.\r
	429	\r
	430	@param CallingConvention Static Registers\r
	431	\r
	432	@param Mode Physical/Virtual\r
	433	\r
	434	**/\r
	435	#define PAL_VM_SUMMARY 8\r
	436	\r
	437	/**\r
	438	\r
	439	Read contents of a translation register. It is required by\r
	440	IPF.\r
	441	\r
	442	@param CallingConvention Stacked Register\r
	443	\r
	444	@param Mode Physical\r
	445	\r
	446	**/\r
	447	#define PAL_VM_TR_READ 261 \r
	448	\r
	449	/**\r
	450	\r
	451	Return configurable processor bus interface features and their\r
	452	current settings. It is required by IPF.\r
	453	\r
	454	@param CallingConvention Static Registers\r
	455	\r
	456	@param Mode Physical\r
	457	\r
	458	**/\r
	459	#define PAL_BUS_GET_FEATURES 9\r
	460	\r
	461	\r
	462	/**\r
	463	\r
	464	Enable or disable configurable features in processor bus\r
	465	interface. It is required by IPF.\r
	466	\r
	467	@param CallingConvention Static Registers\r
	468	\r
	469	@param Mode Physical\r
	470	\r
	471	**/\r
	472	#define PAL_BUS_SET_FEATURES 10\r
	473	\r
	474	\r
	475	/**\r
	476	\r
	477	Return the number of instruction and data breakpoint\r
	478	registers. It is required by IPF.\r
	479	\r
	480	@param CallingConvention Static Registers\r
	481	\r
	482	@param Mode Physical/Virtual\r
	483	\r
	484	**/\r
	485	#define PAL_DEBUG_INFO 11\r
	486	\r
	487	/**\r
	488	\r
	489