| 1 | /** @file\r |
| 2 | Cache Maintenance Functions.\r |
| 3 | \r |
| 4 | Copyright (c) 2006, Intel Corporation<BR>\r |
| 5 | All rights reserved. This program and the accompanying materials\r |
| 6 | are licensed and made available under the terms and conditions of the BSD License\r |
| 7 | which accompanies this distribution. The full text of the license may be found at\r |
| 8 | http://opensource.org/licenses/bsd-license.php\r |
| 9 | \r |
| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| 12 | \r |
| 13 | **/\r |
| 14 | \r |
| 15 | \r |
| 16 | /**\r |
| 17 | Invalidates the entire instruction cache in cache coherency domain of the\r |
| 18 | calling CPU.\r |
| 19 | \r |
| 20 | Invalidates the entire instruction cache in cache coherency domain of the\r |
| 21 | calling CPU.\r |
| 22 | \r |
| 23 | **/\r |
| 24 | VOID\r |
| 25 | EFIAPI\r |
| 26 | InvalidateInstructionCache (\r |
| 27 | VOID\r |
| 28 | )\r |
| 29 | {\r |
| 30 | PalCallStatic (NULL, 1, 1, 1, 0);\r |
| 31 | }\r |
| 32 | \r |
| 33 | /**\r |
| 34 | Invalidates a range of instruction cache lines in the cache coherency domain\r |
| 35 | of the calling CPU.\r |
| 36 | \r |
| 37 | Invalidates the instruction cache lines specified by Address and Length. If\r |
| 38 | Address is not aligned on a cache line boundary, then entire instruction\r |
| 39 | cache line containing Address is invalidated. If Address + Length is not\r |
| 40 | aligned on a cache line boundary, then the entire instruction cache line\r |
| 41 | containing Address + Length -1 is invalidated. This function may choose to\r |
| 42 | invalidate the entire instruction cache if that is more efficient than\r |
| 43 | invalidating the specified range. If Length is 0, the no instruction cache\r |
| 44 | lines are invalidated. Address is returned.\r |
| 45 | \r |
| 46 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r |
| 47 | \r |
| 48 | @param Address The base address of the instruction cache lines to\r |
| 49 | invalidate. If the CPU is in a physical addressing mode, then\r |
| 50 | Address is a physical address. If the CPU is in a virtual\r |
| 51 | addressing mode, then Address is a virtual address.\r |
| 52 | \r |
| 53 | @param Length The number of bytes to invalidate from the instruction cache.\r |
| 54 | \r |
| 55 | @return Address\r |
| 56 | \r |
| 57 | **/\r |
| 58 | VOID *\r |
| 59 | EFIAPI\r |
| 60 | InvalidateInstructionCacheRange (\r |
| 61 | IN VOID *Address,\r |
| 62 | IN UINTN Length\r |
| 63 | )\r |
| 64 | {\r |
| 65 | return IpfInvalidateInstructionCacheRange (Address, Length);\r |
| 66 | }\r |
| 67 | \r |
| 68 | /**\r |
| 69 | Writes Back and Invalidates the entire data cache in cache coherency domain\r |
| 70 | of the calling CPU.\r |
| 71 | \r |
| 72 | Writes Back and Invalidates the entire data cache in cache coherency domain\r |
| 73 | of the calling CPU. This function guarantees that all dirty cache lines are\r |
| 74 | written back to system memory, and also invalidates all the data cache lines\r |
| 75 | in the cache coherency domain of the calling CPU.\r |
| 76 | \r |
| 77 | **/\r |
| 78 | VOID\r |
| 79 | EFIAPI\r |
| 80 | WriteBackInvalidateDataCache (\r |
| 81 | VOID\r |
| 82 | )\r |
| 83 | {\r |
| 84 | PalCallStatic (NULL, 1, 2, 1, 0);\r |
| 85 | }\r |
| 86 | \r |
| 87 | /**\r |
| 88 | Writes Back and Invalidates a range of data cache lines in the cache\r |
| 89 | coherency domain of the calling CPU.\r |
| 90 | \r |
| 91 | Writes Back and Invalidate the data cache lines specified by Address and\r |
| 92 | Length. If Address is not aligned on a cache line boundary, then entire data\r |
| 93 | cache line containing Address is written back and invalidated. If Address +\r |
| 94 | Length is not aligned on a cache line boundary, then the entire data cache\r |
| 95 | line containing Address + Length -1 is written back and invalidated. This\r |
| 96 | function may choose to write back and invalidate the entire data cache if\r |
| 97 | that is more efficient than writing back and invalidating the specified\r |
| 98 | range. If Length is 0, the no data cache lines are written back and\r |
| 99 | invalidated. Address is returned.\r |
| 100 | \r |
| 101 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r |
| 102 | \r |
| 103 | @param Address The base address of the data cache lines to write back and\r |
| 104 | invalidate. If the CPU is in a physical addressing mode, then\r |
| 105 | Address is a physical address. If the CPU is in a virtual\r |
| 106 | addressing mode, then Address is a virtual address.\r |
| 107 | @param Length The number of bytes to write back and invalidate from the\r |
| 108 | data cache.\r |
| 109 | \r |
| 110 | @return Address\r |
| 111 | \r |
| 112 | **/\r |
| 113 | VOID *\r |
| 114 | EFIAPI\r |
| 115 | WriteBackInvalidateDataCacheRange (\r |
| 116 | IN VOID *Address,\r |
| 117 | IN UINTN Length\r |
| 118 | )\r |
| 119 | {\r |
| 120 | ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r |
| 121 | \r |
| 122 | if (Length > 0) {\r |
| 123 | WriteBackInvalidateDataCache ();\r |
| 124 | }\r |
| 125 | return Address;\r |
| 126 | }\r |
| 127 | \r |
| 128 | /**\r |
| 129 | Writes Back the entire data cache in cache coherency domain of the calling\r |
| 130 | CPU.\r |
| 131 | \r |
| 132 | Writes Back the entire data cache in cache coherency domain of the calling\r |
| 133 | CPU. This function guarantees that all dirty cache lines are written back to\r |
| 134 | system memory. This function may also invalidate all the data cache lines in\r |
| 135 | the cache coherency domain of the calling CPU.\r |
| 136 | \r |
| 137 | **/\r |
| 138 | VOID\r |
| 139 | EFIAPI\r |
| 140 | WriteBackDataCache (\r |
| 141 | VOID\r |
| 142 | )\r |
| 143 | {\r |
| 144 | PalCallStatic (NULL, 1, 2, 0, 0);\r |
| 145 | }\r |
| 146 | \r |
| 147 | /**\r |
| 148 | Writes Back a range of data cache lines in the cache coherency domain of the\r |
| 149 | calling CPU.\r |
| 150 | \r |
| 151 | Writes Back the data cache lines specified by Address and Length. If Address\r |
| 152 | is not aligned on a cache line boundary, then entire data cache line\r |
| 153 | containing Address is written back. If Address + Length is not aligned on a\r |
| 154 | cache line boundary, then the entire data cache line containing Address +\r |
| 155 | Length -1 is written back. This function may choose to write back the entire\r |
| 156 | data cache if that is more efficient than writing back the specified range.\r |
| 157 | If Length is 0, the no data cache lines are written back. This function may\r |
| 158 | also invalidate all the data cache lines in the specified range of the cache\r |
| 159 | coherency domain of the calling CPU. Address is returned.\r |
| 160 | \r |
| 161 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r |
| 162 | \r |
| 163 | @param Address The base address of the data cache lines to write back. If\r |
| 164 | the CPU is in a physical addressing mode, then Address is a\r |
| 165 | physical address. If the CPU is in a virtual addressing\r |
| 166 | mode, then Address is a virtual address.\r |
| 167 | @param Length The number of bytes to write back from the data cache.\r |
| 168 | \r |
| 169 | @return Address\r |
| 170 | \r |
| 171 | **/\r |
| 172 | VOID *\r |
| 173 | EFIAPI\r |
| 174 | WriteBackDataCacheRange (\r |
| 175 | IN VOID *Address,\r |
| 176 | IN UINTN Length\r |
| 177 | )\r |
| 178 | {\r |
| 179 | ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r |
| 180 | \r |
| 181 | if (Length > 0) {\r |
| 182 | WriteBackDataCache ();\r |
| 183 | }\r |
| 184 | return Address;\r |
| 185 | }\r |
| 186 | \r |
| 187 | /**\r |
| 188 | Invalidates the entire data cache in cache coherency domain of the calling\r |
| 189 | CPU.\r |
| 190 | \r |
| 191 | Invalidates the entire data cache in cache coherency domain of the calling\r |
| 192 | CPU. This function must be used with care because dirty cache lines are not\r |
| 193 | written back to system memory. It is typically used for cache diagnostics. If\r |
| 194 | the CPU does not support invalidation of the entire data cache, then a write\r |
| 195 | back and invalidate operation should be performed on the entire data cache.\r |
| 196 | \r |
| 197 | **/\r |
| 198 | VOID\r |
| 199 | EFIAPI\r |
| 200 | InvalidateDataCache (\r |
| 201 | VOID\r |
| 202 | )\r |
| 203 | {\r |
| 204 | WriteBackInvalidateDataCache ();\r |
| 205 | }\r |
| 206 | \r |
| 207 | /**\r |
| 208 | Invalidates a range of data cache lines in the cache coherency domain of the\r |
| 209 | calling CPU.\r |
| 210 | \r |
| 211 | Invalidates the data cache lines specified by Address and Length. If Address\r |
| 212 | is not aligned on a cache line boundary, then entire data cache line\r |
| 213 | containing Address is invalidated. If Address + Length is not aligned on a\r |
| 214 | cache line boundary, then the entire data cache line containing Address +\r |
| 215 | Length -1 is invalidated. This function must never invalidate any cache lines\r |
| 216 | outside the specified range. If Length is 0, the no data cache lines are\r |
| 217 | invalidated. Address is returned. This function must be used with care\r |
| 218 | because dirty cache lines are not written back to system memory. It is\r |
| 219 | typically used for cache diagnostics. If the CPU does not support\r |
| 220 | invalidation of a data cache range, then a write back and invalidate\r |
| 221 | operation should be performed on the data cache range.\r |
| 222 | \r |
| 223 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r |
| 224 | \r |
| 225 | @param Address The base address of the data cache lines to invalidate. If\r |
| 226 | the CPU is in a physical addressing mode, then Address is a\r |
| 227 | physical address. If the CPU is in a virtual addressing mode,\r |
| 228 | then Address is a virtual address.\r |
| 229 | @param Length The number of bytes to invalidate from the data cache.\r |
| 230 | \r |
| 231 | @return Address\r |
| 232 | \r |
| 233 | **/\r |
| 234 | VOID *\r |
| 235 | EFIAPI\r |
| 236 | InvalidateDataCacheRange (\r |
| 237 | IN VOID *Address,\r |
| 238 | IN UINTN Length\r |
| 239 | )\r |
| 240 | {\r |
| 241 | return WriteBackInvalidateDataCacheRange (Address, Length);\r |
| 242 | }\r |