[mirror_edk2.git] / OvmfPkg / Include / Register / QemuSmramSaveStateMap.h

/** @file\r
SMRAM Save State Map Definitions.\r
\r
SMRAM Save State Map definitions based on contents of the\r
Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
  Volume 3C, Section 34.4 SMRAM\r
  Volume 3C, Section 34.5 SMI Handler Execution Environment\r
  Volume 3C, Section 34.7 Managing Synchronous and Asynchronous SMIs\r
\r
and the AMD64 Architecture Programmer's Manual\r
  Volume 2, Section 10.2 SMM Resources\r
\r
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2015, Red Hat, Inc.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef __QEMU_SMRAM_SAVE_STATE_MAP_H__\r
#define __QEMU_SMRAM_SAVE_STATE_MAP_H__\r
\r
#pragma pack (1)\r
\r
///\r
/// 32-bit SMRAM Save State Map\r
///\r
typedef struct {\r
  UINT8     Reserved0[0x200]; // 7c00h\r
  UINT8     Reserved1[0xf8];  // 7e00h\r
  UINT32    SMBASE;           // 7ef8h\r
  UINT32    SMMRevId;         // 7efch\r
  UINT16    IORestart;        // 7f00h\r
  UINT16    AutoHALTRestart;  // 7f02h\r
  UINT8     Reserved2[0x9C];  // 7f08h\r
  UINT32    IOMemAddr;        // 7fa0h\r
  UINT32    IOMisc;           // 7fa4h\r
  UINT32    _ES;              // 7fa8h\r
  UINT32    _CS;              // 7fach\r
  UINT32    _SS;              // 7fb0h\r
  UINT32    _DS;              // 7fb4h\r
  UINT32    _FS;              // 7fb8h\r
  UINT32    _GS;              // 7fbch\r
  UINT32    Reserved3;        // 7fc0h\r
  UINT32    _TR;              // 7fc4h\r
  UINT32    _DR7;             // 7fc8h\r
  UINT32    _DR6;             // 7fcch\r
  UINT32    _EAX;             // 7fd0h\r
  UINT32    _ECX;             // 7fd4h\r
  UINT32    _EDX;             // 7fd8h\r
  UINT32    _EBX;             // 7fdch\r
  UINT32    _ESP;             // 7fe0h\r
  UINT32    _EBP;             // 7fe4h\r
  UINT32    _ESI;             // 7fe8h\r
  UINT32    _EDI;             // 7fech\r
  UINT32    _EIP;             // 7ff0h\r
  UINT32    _EFLAGS;          // 7ff4h\r
  UINT32    _CR3;             // 7ff8h\r
  UINT32    _CR0;             // 7ffch\r
} QEMU_SMRAM_SAVE_STATE_MAP32;\r
\r
///\r
/// 64-bit SMRAM Save State Map\r
///\r
typedef struct {\r
  UINT8     Reserved0[0x200]; // 7c00h\r
\r
  UINT16    _ES;             // 7e00h\r
  UINT16    _ESAccessRights; // 7e02h\r
  UINT32    _ESLimit;        // 7e04h\r
  UINT64    _ESBase;         // 7e08h\r
\r
  UINT16    _CS;             // 7e10h\r
  UINT16    _CSAccessRights; // 7e12h\r
  UINT32    _CSLimit;        // 7e14h\r
  UINT64    _CSBase;         // 7e18h\r
\r
  UINT16    _SS;             // 7e20h\r
  UINT16    _SSAccessRights; // 7e22h\r
  UINT32    _SSLimit;        // 7e24h\r
  UINT64    _SSBase;         // 7e28h\r
\r
  UINT16    _DS;             // 7e30h\r
  UINT16    _DSAccessRights; // 7e32h\r
  UINT32    _DSLimit;        // 7e34h\r
  UINT64    _DSBase;         // 7e38h\r
\r
  UINT16    _FS;             // 7e40h\r
  UINT16    _FSAccessRights; // 7e42h\r
  UINT32    _FSLimit;        // 7e44h\r
  UINT64    _FSBase;         // 7e48h\r
\r
  UINT16    _GS;             // 7e50h\r
  UINT16    _GSAccessRights; // 7e52h\r
  UINT32    _GSLimit;        // 7e54h\r
  UINT64    _GSBase;         // 7e58h\r
\r
  UINT32    _GDTRReserved1;  // 7e60h\r
  UINT16    _GDTRLimit;      // 7e64h\r
  UINT16    _GDTRReserved2;  // 7e66h\r
  UINT64    _GDTRBase;       // 7e68h\r
\r
  UINT16    _LDTR;             // 7e70h\r
  UINT16    _LDTRAccessRights; // 7e72h\r
  UINT32    _LDTRLimit;        // 7e74h\r
  UINT64    _LDTRBase;         // 7e78h\r
\r
  UINT32    _IDTRReserved1;  // 7e80h\r
  UINT16    _IDTRLimit;      // 7e84h\r
  UINT16    _IDTRReserved2;  // 7e86h\r
  UINT64    _IDTRBase;       // 7e88h\r
\r
  UINT16    _TR;             // 7e90h\r
  UINT16    _TRAccessRights; // 7e92h\r
  UINT32    _TRLimit;        // 7e94h\r
  UINT64    _TRBase;         // 7e98h\r
\r
  UINT64    IO_RIP;          // 7ea0h\r
  UINT64    IO_RCX;          // 7ea8h\r
  UINT64    IO_RSI;          // 7eb0h\r
  UINT64    IO_RDI;          // 7eb8h\r
  UINT32    IO_DWord;        // 7ec0h\r
  UINT8     Reserved1[0x04]; // 7ec4h\r
  UINT8     IORestart;       // 7ec8h\r
  UINT8     AutoHALTRestart; // 7ec9h\r
  UINT8     Reserved2[0x06]; // 7ecah\r
\r
  UINT64    IA32_EFER;       // 7ed0h\r
  UINT64    SVM_Guest;       // 7ed8h\r
  UINT64    SVM_GuestVMCB;   // 7ee0h\r
  UINT64    SVM_GuestVIntr;  // 7ee8h\r
  UINT8     Reserved3[0x0c]; // 7ef0h\r
\r
  UINT32    SMMRevId;        // 7efch\r
  UINT32    SMBASE;          // 7f00h\r
\r
  UINT8     Reserved4[0x1c];   // 7f04h\r
  UINT64    SVM_GuestPAT;      // 7f20h\r
  UINT64    SVM_HostIA32_EFER; // 7f28h\r
  UINT64    SVM_HostCR4;       // 7f30h\r
  UINT64    SVM_HostCR3;       // 7f38h\r
  UINT64    SVM_HostCR0;       // 7f40h\r
\r
  UINT64    _CR4;            // 7f48h\r
  UINT64    _CR3;            // 7f50h\r
  UINT64    _CR0;            // 7f58h\r
  UINT64    _DR7;            // 7f60h\r
  UINT64    _DR6;            // 7f68h\r
  UINT64    _RFLAGS;         // 7f70h\r
  UINT64    _RIP;            // 7f78h\r
  UINT64    _R15;            // 7f80h\r
  UINT64    _R14;            // 7f88h\r
  UINT64    _R13;            // 7f90h\r
  UINT64    _R12;            // 7f98h\r
  UINT64    _R11;            // 7fa0h\r
  UINT64    _R10;            // 7fa8h\r
  UINT64    _R9;             // 7fb0h\r
  UINT64    _R8;             // 7fb8h\r
  UINT64    _RDI;            // 7fc0h\r
  UINT64    _RSI;            // 7fc8h\r
  UINT64    _RBP;            // 7fd0h\r
  UINT64    _RSP;            // 7fd8h\r
  UINT64    _RBX;            // 7fe0h\r
  UINT64    _RDX;            // 7fe8h\r
  UINT64    _RCX;            // 7ff0h\r
  UINT64    _RAX;            // 7ff8h\r
} QEMU_SMRAM_SAVE_STATE_MAP64;\r
\r
///\r
/// Union of 32-bit and 64-bit SMRAM Save State Maps\r
///\r
typedef union  {\r
  QEMU_SMRAM_SAVE_STATE_MAP32    x86;\r
  QEMU_SMRAM_SAVE_STATE_MAP64    x64;\r
} QEMU_SMRAM_SAVE_STATE_MAP;\r
\r
#pragma pack ()\r
\r
#endif\r
Commit	Line	Data
	1	/** @file\r
	2	SMRAM Save State Map Definitions.\r
	3	\r
	4	SMRAM Save State Map definitions based on contents of the\r
	5	Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
	6	Volume 3C, Section 34.4 SMRAM\r
	7	Volume 3C, Section 34.5 SMI Handler Execution Environment\r
	8	Volume 3C, Section 34.7 Managing Synchronous and Asynchronous SMIs\r
	9	\r
	10	and the AMD64 Architecture Programmer's Manual\r
	11	Volume 2, Section 10.2 SMM Resources\r
	12	\r
	13	Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
	14	Copyright (c) 2015, Red Hat, Inc.<BR>\r
	15	SPDX-License-Identifier: BSD-2-Clause-Patent\r
	16	\r
	17	**/\r
	18	\r
	19	#ifndef __QEMU_SMRAM_SAVE_STATE_MAP_H__\r
	20	#define __QEMU_SMRAM_SAVE_STATE_MAP_H__\r
	21	\r
	22	#pragma pack (1)\r
	23	\r
	24	///\r
	25	/// 32-bit SMRAM Save State Map\r
	26	///\r
	27	typedef struct {\r
	28	UINT8 Reserved0[0x200]; // 7c00h\r
	29	UINT8 Reserved1[0xf8]; // 7e00h\r
	30	UINT32 SMBASE; // 7ef8h\r
	31	UINT32 SMMRevId; // 7efch\r
	32	UINT16 IORestart; // 7f00h\r
	33	UINT16 AutoHALTRestart; // 7f02h\r
	34	UINT8 Reserved2[0x9C]; // 7f08h\r
	35	UINT32 IOMemAddr; // 7fa0h\r
	36	UINT32 IOMisc; // 7fa4h\r
	37	UINT32 _ES; // 7fa8h\r
	38	UINT32 _CS; // 7fach\r
	39	UINT32 _SS; // 7fb0h\r
	40	UINT32 _DS; // 7fb4h\r
	41	UINT32 _FS; // 7fb8h\r
	42	UINT32 _GS; // 7fbch\r
	43	UINT32 Reserved3; // 7fc0h\r
	44	UINT32 _TR; // 7fc4h\r
	45	UINT32 _DR7; // 7fc8h\r
	46	UINT32 _DR6; // 7fcch\r
	47	UINT32 _EAX; // 7fd0h\r
	48	UINT32 _ECX; // 7fd4h\r
	49	UINT32 _EDX; // 7fd8h\r
	50	UINT32 _EBX; // 7fdch\r
	51	UINT32 _ESP; // 7fe0h\r
	52	UINT32 _EBP; // 7fe4h\r
	53	UINT32 _ESI; // 7fe8h\r
	54	UINT32 _EDI; // 7fech\r
	55	UINT32 _EIP; // 7ff0h\r
	56	UINT32 _EFLAGS; // 7ff4h\r
	57	UINT32 _CR3; // 7ff8h\r
	58	UINT32 _CR0; // 7ffch\r
	59	} QEMU_SMRAM_SAVE_STATE_MAP32;\r
	60	\r
	61	///\r
	62	/// 64-bit SMRAM Save State Map\r
	63	///\r
	64	typedef struct {\r
	65	UINT8 Reserved0[0x200]; // 7c00h\r
	66	\r
	67	UINT16 _ES; // 7e00h\r
	68	UINT16 _ESAccessRights; // 7e02h\r
	69	UINT32 _ESLimit; // 7e04h\r
	70	UINT64 _ESBase; // 7e08h\r
	71	\r
	72	UINT16 _CS; // 7e10h\r
	73	UINT16 _CSAccessRights; // 7e12h\r
	74	UINT32 _CSLimit; // 7e14h\r
	75	UINT64 _CSBase; // 7e18h\r
	76	\r
	77	UINT16 _SS; // 7e20h\r
	78	UINT16 _SSAccessRights; // 7e22h\r
	79	UINT32 _SSLimit; // 7e24h\r
	80	UINT64 _SSBase; // 7e28h\r
	81	\r
	82	UINT16 _DS; // 7e30h\r
	83	UINT16 _DSAccessRights; // 7e32h\r
	84	UINT32 _DSLimit; // 7e34h\r
	85	UINT64 _DSBase; // 7e38h\r
	86	\r
	87	UINT16 _FS; // 7e40h\r
	88	UINT16 _FSAccessRights; // 7e42h\r
	89	UINT32 _FSLimit; // 7e44h\r
	90	UINT64 _FSBase; // 7e48h\r
	91	\r
	92	UINT16 _GS; // 7e50h\r
	93	UINT16 _GSAccessRights; // 7e52h\r
	94	UINT32 _GSLimit; // 7e54h\r
	95	UINT64 _GSBase; // 7e58h\r
	96	\r
	97	UINT32 _GDTRReserved1; // 7e60h\r
	98	UINT16 _GDTRLimit; // 7e64h\r
	99	UINT16 _GDTRReserved2; // 7e66h\r
	100	UINT64 _GDTRBase; // 7e68h\r
	101	\r
	102	UINT16 _LDTR; // 7e70h\r
	103	UINT16 _LDTRAccessRights; // 7e72h\r
	104	UINT32 _LDTRLimit; // 7e74h\r
	105	UINT64 _LDTRBase; // 7e78h\r
	106	\r
	107	UINT32 _IDTRReserved1; // 7e80h\r
	108	UINT16 _IDTRLimit; // 7e84h\r
	109	UINT16 _IDTRReserved2; // 7e86h\r
	110	UINT64 _IDTRBase; // 7e88h\r
	111	\r
	112	UINT16 _TR; // 7e90h\r
	113	UINT16 _TRAccessRights; // 7e92h\r
	114	UINT32 _TRLimit; // 7e94h\r
	115	UINT64 _TRBase; // 7e98h\r
	116	\r
	117	UINT64 IO_RIP; // 7ea0h\r
	118	UINT64 IO_RCX; // 7ea8h\r
	119	UINT64 IO_RSI; // 7eb0h\r
	120	UINT64 IO_RDI; // 7eb8h\r
	121	UINT32 IO_DWord; // 7ec0h\r
	122	UINT8 Reserved1[0x04]; // 7ec4h\r
	123	UINT8 IORestart; // 7ec8h\r
	124	UINT8 AutoHALTRestart; // 7ec9h\r
	125	UINT8 Reserved2[0x06]; // 7ecah\r
	126	\r
	127	UINT64 IA32_EFER; // 7ed0h\r
	128	UINT64 SVM_Guest; // 7ed8h\r
	129	UINT64 SVM_GuestVMCB; // 7ee0h\r
	130	UINT64 SVM_GuestVIntr; // 7ee8h\r
	131	UINT8 Reserved3[0x0c]; // 7ef0h\r
	132	\r
	133	UINT32 SMMRevId; // 7efch\r
	134	UINT32 SMBASE; // 7f00h\r
	135	\r
	136	UINT8 Reserved4[0x1c]; // 7f04h\r
	137	UINT64 SVM_GuestPAT; // 7f20h\r
	138	UINT64 SVM_HostIA32_EFER; // 7f28h\r
	139	UINT64 SVM_HostCR4; // 7f30h\r
	140	UINT64 SVM_HostCR3; // 7f38h\r
	141	UINT64 SVM_HostCR0; // 7f40h\r
	142	\r
	143	UINT64 _CR4; // 7f48h\r
	144	UINT64 _CR3; // 7f50h\r
	145	UINT64 _CR0; // 7f58h\r
	146	UINT64 _DR7; // 7f60h\r
	147	UINT64 _DR6; // 7f68h\r
	148	UINT64 _RFLAGS; // 7f70h\r
	149	UINT64 _RIP; // 7f78h\r
	150	UINT64 _R15; // 7f80h\r
	151	UINT64 _R14; // 7f88h\r
	152	UINT64 _R13; // 7f90h\r
	153	UINT64 _R12; // 7f98h\r
	154	UINT64 _R11; // 7fa0h\r
	155	UINT64 _R10; // 7fa8h\r
	156	UINT64 _R9; // 7fb0h\r
	157	UINT64 _R8; // 7fb8h\r
	158	UINT64 _RDI; // 7fc0h\r
	159	UINT64 _RSI; // 7fc8h\r
	160	UINT64 _RBP; // 7fd0h\r
	161	UINT64 _RSP; // 7fd8h\r
	162	UINT64 _RBX; // 7fe0h\r
	163	UINT64 _RDX; // 7fe8h\r
	164	UINT64 _RCX; // 7ff0h\r
	165	UINT64 _RAX; // 7ff8h\r
	166	} QEMU_SMRAM_SAVE_STATE_MAP64;\r
	167	\r
	168	///\r
	169	/// Union of 32-bit and 64-bit SMRAM Save State Maps\r
	170	///\r
	171	typedef union {\r
	172	QEMU_SMRAM_SAVE_STATE_MAP32 x86;\r
	173	QEMU_SMRAM_SAVE_STATE_MAP64 x64;\r
	174	} QEMU_SMRAM_SAVE_STATE_MAP;\r
	175	\r
	176	#pragma pack ()\r
	177	\r
	178	#endif\r