[mirror_edk2.git] / OvmfPkg / OvmfPkg.dec

## @file\r
#  EFI/Framework Open Virtual Machine Firmware (OVMF) platform\r
#\r
#  Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>\r
#\r
#  This program and the accompanying materials\r
#  are licensed and made available under the terms and conditions of the BSD License\r
#  which accompanies this distribution. The full text of the license may be found at\r
#  http://opensource.org/licenses/bsd-license.php\r
#\r
#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
#\r
##\r
\r
[Defines]\r
  DEC_SPECIFICATION              = 0x00010005\r
  PACKAGE_NAME                   = OvmfPkg\r
  PACKAGE_GUID                   = 2daf5f34-50e5-4b9d-b8e3-5562334d87e5\r
  PACKAGE_VERSION                = 0.1\r
\r
[Includes]\r
  Include\r
\r
[LibraryClasses]\r
  ##  @libraryclass  Loads and boots a Linux kernel image\r
  #\r
  LoadLinuxLib|Include/Library/LoadLinuxLib.h\r
\r
  ##  @libraryclass  Save and restore variables using a file\r
  #\r
  NvVarsFileLib|Include/Library/NvVarsFileLib.h\r
\r
  ##  @libraryclass  Access QEMU's firmware configuration interface\r
  #\r
  QemuFwCfgLib|Include/Library/QemuFwCfgLib.h\r
\r
  ##  @libraryclass  Rewrite the BootOrder NvVar based on QEMU's "bootorder"\r
  #                  fw_cfg file.\r
  #\r
  QemuBootOrderLib|Include/Library/QemuBootOrderLib.h\r
\r
  ##  @libraryclass  Serialize (and deserialize) variables\r
  #\r
  SerializeVariablesLib|Include/Library/SerializeVariablesLib.h\r
\r
  ##  @libraryclass  Invoke Xen hypercalls\r
  #\r
  XenHypercallLib|Include/Library/XenHypercallLib.h\r
\r
  ##  @libraryclass  Manage XenBus device path and I/O handles\r
  #\r
  XenIoMmioLib|Include/Library/XenIoMmioLib.h\r
\r
[Guids]\r
  gUefiOvmfPkgTokenSpaceGuid          = {0x93bb96af, 0xb9f2, 0x4eb8, {0x94, 0x62, 0xe0, 0xba, 0x74, 0x56, 0x42, 0x36}}\r
  gEfiXenInfoGuid                     = {0xd3b46f3b, 0xd441, 0x1244, {0x9a, 0x12, 0x0, 0x12, 0x27, 0x3f, 0xc1, 0x4d}}\r
  gOvmfPlatformConfigGuid             = {0x7235c51c, 0x0c80, 0x4cab, {0x87, 0xac, 0x3b, 0x08, 0x4a, 0x63, 0x04, 0xb1}}\r
  gVirtioMmioTransportGuid            = {0x837dca9e, 0xe874, 0x4d82, {0xb2, 0x9a, 0x23, 0xfe, 0x0e, 0x23, 0xd1, 0xe2}}\r
  gXenBusRootDeviceGuid               = {0xa732241f, 0x383d, 0x4d9c, {0x8a, 0xe1, 0x8e, 0x09, 0x83, 0x75, 0x89, 0xd7}}\r
  gRootBridgesConnectedEventGroupGuid = {0x24a2d66f, 0xeedd, 0x4086, {0x90, 0x42, 0xf2, 0x6e, 0x47, 0x97, 0xee, 0x69}}\r
\r
[Protocols]\r
  gVirtioDeviceProtocolGuid           = {0xfa920010, 0x6785, 0x4941, {0xb6, 0xec, 0x49, 0x8c, 0x57, 0x9f, 0x16, 0x0a}}\r
  gBlockMmioProtocolGuid              = {0x6b558ce3, 0x69e5, 0x4c67, {0xa6, 0x34, 0xf7, 0xfe, 0x72, 0xad, 0xbe, 0x84}}\r
  gXenBusProtocolGuid                 = {0x3d3ca290, 0xb9a5, 0x11e3, {0xb7, 0x5d, 0xb8, 0xac, 0x6f, 0x7d, 0x65, 0xe6}}\r
  gXenIoProtocolGuid                  = {0x6efac84f, 0x0ab0, 0x4747, {0x81, 0xbe, 0x85, 0x55, 0x62, 0x59, 0x04, 0x49}}\r
\r
[PcdsFixedAtBuild]\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase|0x0|UINT32|0\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvSize|0x0|UINT32|1\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase|0x0|UINT32|0x15\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize|0x0|UINT32|0x16\r
\r
  ## This flag is used to control the destination port for PlatformDebugLibIoPort\r
  gUefiOvmfPkgTokenSpaceGuid.PcdDebugIoPort|0x402|UINT16|4\r
\r
  ## This flag determines the Power Management Base Address of choice, written\r
  #  to PIIX4 function 3 offset 0x40-0x43 bits [15:6].\r
  gUefiOvmfPkgTokenSpaceGuid.PcdAcpiPmBaseAddress|0xB000|UINT16|5\r
\r
  ## When VirtioScsiDxe is instantiated for a HBA, the numbers of targets and\r
  #  LUNs are retrieved from the host during virtio-scsi setup.\r
  #  MdeModulePkg/Bus/Scsi/ScsiBusDxe then scans all MaxTarget * MaxLun\r
  #  possible devices. This can take extremely long, for example with\r
  #  MaxTarget=255 and MaxLun=16383. The *inclusive* constants below limit\r
  #  MaxTarget and MaxLun, independently, should the host report higher values,\r
  #  so that scanning the number of devices given by their product is still\r
  #  acceptably fast.\r
  gUefiOvmfPkgTokenSpaceGuid.PcdVirtioScsiMaxTargetLimit|31|UINT16|6\r
  gUefiOvmfPkgTokenSpaceGuid.PcdVirtioScsiMaxLunLimit|7|UINT32|7\r
\r
  ## The following setting controls how many megabytes we configure as TSEG on\r
  #  Q35, for SMRAM purposes. Permitted values are: 1, 2, 8. Other values cause\r
  #  undefined behavior.\r
  #\r
  #  This PCD is only consulted if PcdSmmSmramRequire is TRUE (see below).\r
  gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes|8|UINT8|0x20\r
\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogBase|0x0|UINT32|0x8\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogSize|0x0|UINT32|0x9\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize|0x0|UINT32|0xa\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareBlockSize|0|UINT32|0xb\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase|0x0|UINT32|0xc\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwSpareBase|0x0|UINT32|0xd\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwWorkingBase|0x0|UINT32|0xe\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress|0x0|UINT32|0xf\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase|0x0|UINT32|0x11\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesSize|0x0|UINT32|0x12\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase|0x0|UINT32|0x13\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize|0x0|UINT32|0x14\r
  gUefiOvmfPkgTokenSpaceGuid.PcdS3AcpiReservedMemoryBase|0x0|UINT32|0x17\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageBase|0x0|UINT32|0x18\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageSize|0x0|UINT32|0x19\r
  gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize|0x0|UINT32|0x1a\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd|0x0|UINT32|0x1f\r
\r
  ## The IO port aperture shared by all PCI root bridges.\r
  #\r
  gUefiOvmfPkgTokenSpaceGuid.PcdPciIoBase|0xC000|UINT64|0x22\r
  gUefiOvmfPkgTokenSpaceGuid.PcdPciIoSize|0x4000|UINT64|0x23\r
\r
[PcdsDynamic, PcdsDynamicEx]\r
  gUefiOvmfPkgTokenSpaceGuid.PcdEmuVariableEvent|0|UINT64|2\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable|FALSE|BOOLEAN|0x10\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId|0|UINT16|0x1b\r
  gUefiOvmfPkgTokenSpaceGuid.PcdQemuSmbiosValidated|FALSE|BOOLEAN|0x21\r
\r
  ## The 32-bit MMIO aperture shared by all PCI root bridges.\r
  #\r
  gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT64|0x24\r
  gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT64|0x25\r
\r
[PcdsFeatureFlag]\r
  gUefiOvmfPkgTokenSpaceGuid.PcdSecureBootEnable|FALSE|BOOLEAN|3\r
  gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderPciTranslation|TRUE|BOOLEAN|0x1c\r
  gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderMmioTranslation|FALSE|BOOLEAN|0x1d\r
\r
  ## This feature flag enables SMM/SMRAM support. Note that it also requires\r
  #  such support from the underlying QEMU instance; if that support is not\r
  #  present, the firmware will reject continuing after a certain point.\r
  #\r
  #  The flag also acts as a general "security switch"; when TRUE, many\r
  #  components will change behavior, with the goal of preventing a malicious\r
  #  runtime OS from tampering with firmware structures (special memory ranges\r
  #  used by OVMF, the varstore pflash chip, LockBox etc).\r
  gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire|FALSE|BOOLEAN|0x1e\r
Commit	Line	Data
	1	## @file\r
	2	# EFI/Framework Open Virtual Machine Firmware (OVMF) platform\r
	3	#\r
	4	# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>\r
	5	#\r
	6	# This program and the accompanying materials\r
	7	# are licensed and made available under the terms and conditions of the BSD License\r
	8	# which accompanies this distribution. The full text of the license may be found at\r
	9	# http://opensource.org/licenses/bsd-license.php\r
	10	#\r
	11	# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	#\r
	14	##\r
	15	\r
	16	[Defines]\r
	17	DEC_SPECIFICATION = 0x00010005\r
	18	PACKAGE_NAME = OvmfPkg\r
	19	PACKAGE_GUID = 2daf5f34-50e5-4b9d-b8e3-5562334d87e5\r
	20	PACKAGE_VERSION = 0.1\r
	21	\r
	22	[Includes]\r
	23	Include\r
	24	\r
	25	[LibraryClasses]\r
	26	## @libraryclass Loads and boots a Linux kernel image\r
	27	#\r
	28	LoadLinuxLib\|Include/Library/LoadLinuxLib.h\r
	29	\r
	30	## @libraryclass Save and restore variables using a file\r
	31	#\r
	32	NvVarsFileLib\|Include/Library/NvVarsFileLib.h\r
	33	\r
	34	## @libraryclass Access QEMU's firmware configuration interface\r
	35	#\r
	36	QemuFwCfgLib\|Include/Library/QemuFwCfgLib.h\r
	37	\r
	38	## @libraryclass Rewrite the BootOrder NvVar based on QEMU's "bootorder"\r
	39	# fw_cfg file.\r
	40	#\r
	41	QemuBootOrderLib\|Include/Library/QemuBootOrderLib.h\r
	42	\r
	43	## @libraryclass Serialize (and deserialize) variables\r
	44	#\r
	45	SerializeVariablesLib\|Include/Library/SerializeVariablesLib.h\r
	46	\r
	47	## @libraryclass Invoke Xen hypercalls\r
	48	#\r
	49	XenHypercallLib\|Include/Library/XenHypercallLib.h\r
	50	\r
	51	## @libraryclass Manage XenBus device path and I/O handles\r
	52	#\r
	53	XenIoMmioLib\|Include/Library/XenIoMmioLib.h\r
	54	\r
	55	[Guids]\r
	56	gUefiOvmfPkgTokenSpaceGuid = {0x93bb96af, 0xb9f2, 0x4eb8, {0x94, 0x62, 0xe0, 0xba, 0x74, 0x56, 0x42, 0x36}}\r
	57	gEfiXenInfoGuid = {0xd3b46f3b, 0xd441, 0x1244, {0x9a, 0x12, 0x0, 0x12, 0x27, 0x3f, 0xc1, 0x4d}}\r
	58	gOvmfPlatformConfigGuid = {0x7235c51c, 0x0c80, 0x4cab, {0x87, 0xac, 0x3b, 0x08, 0x4a, 0x63, 0x04, 0xb1}}\r
	59	gVirtioMmioTransportGuid = {0x837dca9e, 0xe874, 0x4d82, {0xb2, 0x9a, 0x23, 0xfe, 0x0e, 0x23, 0xd1, 0xe2}}\r
	60	gXenBusRootDeviceGuid = {0xa732241f, 0x383d, 0x4d9c, {0x8a, 0xe1, 0x8e, 0x09, 0x83, 0x75, 0x89, 0xd7}}\r
	61	gRootBridgesConnectedEventGroupGuid = {0x24a2d66f, 0xeedd, 0x4086, {0x90, 0x42, 0xf2, 0x6e, 0x47, 0x97, 0xee, 0x69}}\r
	62	\r
	63	[Protocols]\r
	64	gVirtioDeviceProtocolGuid = {0xfa920010, 0x6785, 0x4941, {0xb6, 0xec, 0x49, 0x8c, 0x57, 0x9f, 0x16, 0x0a}}\r
	65	gBlockMmioProtocolGuid = {0x6b558ce3, 0x69e5, 0x4c67, {0xa6, 0x34, 0xf7, 0xfe, 0x72, 0xad, 0xbe, 0x84}}\r
	66	gXenBusProtocolGuid = {0x3d3ca290, 0xb9a5, 0x11e3, {0xb7, 0x5d, 0xb8, 0xac, 0x6f, 0x7d, 0x65, 0xe6}}\r
	67	gXenIoProtocolGuid = {0x6efac84f, 0x0ab0, 0x4747, {0x81, 0xbe, 0x85, 0x55, 0x62, 0x59, 0x04, 0x49}}\r
	68	\r
	69	[PcdsFixedAtBuild]\r
	70	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase\|0x0\|UINT32\|0\r
	71	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvSize\|0x0\|UINT32\|1\r
	72	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase\|0x0\|UINT32\|0x15\r
	73	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize\|0x0\|UINT32\|0x16\r
	74	\r
	75	## This flag is used to control the destination port for PlatformDebugLibIoPort\r
	76	gUefiOvmfPkgTokenSpaceGuid.PcdDebugIoPort\|0x402\|UINT16\|4\r
	77	\r
	78	## This flag determines the Power Management Base Address of choice, written\r
	79	# to PIIX4 function 3 offset 0x40-0x43 bits [15:6].\r
	80	gUefiOvmfPkgTokenSpaceGuid.PcdAcpiPmBaseAddress\|0xB000\|UINT16\|5\r
	81	\r
	82	## When VirtioScsiDxe is instantiated for a HBA, the numbers of targets and\r
	83	# LUNs are retrieved from the host during virtio-scsi setup.\r
	84	# MdeModulePkg/Bus/Scsi/ScsiBusDxe then scans all MaxTarget * MaxLun\r
	85	# possible devices. This can take extremely long, for example with\r
	86	# MaxTarget=255 and MaxLun=16383. The inclusive constants below limit\r
	87	# MaxTarget and MaxLun, independently, should the host report higher values,\r
	88	# so that scanning the number of devices given by their product is still\r
	89	# acceptably fast.\r
	90	gUefiOvmfPkgTokenSpaceGuid.PcdVirtioScsiMaxTargetLimit\|31\|UINT16\|6\r
	91	gUefiOvmfPkgTokenSpaceGuid.PcdVirtioScsiMaxLunLimit\|7\|UINT32\|7\r
	92	\r
	93	## The following setting controls how many megabytes we configure as TSEG on\r
	94	# Q35, for SMRAM purposes. Permitted values are: 1, 2, 8. Other values cause\r
	95	# undefined behavior.\r
	96	#\r
	97	# This PCD is only consulted if PcdSmmSmramRequire is TRUE (see below).\r
	98	gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes\|8\|UINT8\|0x20\r
	99	\r
	100	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogBase\|0x0\|UINT32\|0x8\r
	101	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogSize\|0x0\|UINT32\|0x9\r
	102	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize\|0x0\|UINT32\|0xa\r
	103	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareBlockSize\|0\|UINT32\|0xb\r
	104	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase\|0x0\|UINT32\|0xc\r
	105	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwSpareBase\|0x0\|UINT32\|0xd\r
	106	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwWorkingBase\|0x0\|UINT32\|0xe\r
	107	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress\|0x0\|UINT32\|0xf\r
	108	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase\|0x0\|UINT32\|0x11\r
	109	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesSize\|0x0\|UINT32\|0x12\r
	110	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase\|0x0\|UINT32\|0x13\r
	111	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize\|0x0\|UINT32\|0x14\r
	112	gUefiOvmfPkgTokenSpaceGuid.PcdS3AcpiReservedMemoryBase\|0x0\|UINT32\|0x17\r
	113	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageBase\|0x0\|UINT32\|0x18\r
	114	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageSize\|0x0\|UINT32\|0x19\r
	115	gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize\|0x0\|UINT32\|0x1a\r
	116	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd\|0x0\|UINT32\|0x1f\r
	117	\r
	118	## The IO port aperture shared by all PCI root bridges.\r
	119	#\r
	120	gUefiOvmfPkgTokenSpaceGuid.PcdPciIoBase\|0xC000\|UINT64\|0x22\r
	121	gUefiOvmfPkgTokenSpaceGuid.PcdPciIoSize\|0x4000\|UINT64\|0x23\r
	122	\r
	123	[PcdsDynamic, PcdsDynamicEx]\r
	124	gUefiOvmfPkgTokenSpaceGuid.PcdEmuVariableEvent\|0\|UINT64\|2\r
	125	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable\|FALSE\|BOOLEAN\|0x10\r
	126	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId\|0\|UINT16\|0x1b\r
	127	gUefiOvmfPkgTokenSpaceGuid.PcdQemuSmbiosValidated\|FALSE\|BOOLEAN\|0x21\r
	128	\r
	129	## The 32-bit MMIO aperture shared by all PCI root bridges.\r
	130	#\r
	131	gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base\|0x0\|UINT64\|0x24\r
	132	gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size\|0x0\|UINT64\|0x25\r
	133	\r
	134	[PcdsFeatureFlag]\r
	135	gUefiOvmfPkgTokenSpaceGuid.PcdSecureBootEnable\|FALSE\|BOOLEAN\|3\r
	136	gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderPciTranslation\|TRUE\|BOOLEAN\|0x1c\r
	137	gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderMmioTranslation\|FALSE\|BOOLEAN\|0x1d\r
	138	\r
	139	## This feature flag enables SMM/SMRAM support. Note that it also requires\r
	140	# such support from the underlying QEMU instance; if that support is not\r
	141	# present, the firmware will reject continuing after a certain point.\r
	142	#\r
	143	# The flag also acts as a general "security switch"; when TRUE, many\r
	144	# components will change behavior, with the goal of preventing a malicious\r
	145	# runtime OS from tampering with firmware structures (special memory ranges\r
	146	# used by OVMF, the varstore pflash chip, LockBox etc).\r
	147	gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire\|FALSE\|BOOLEAN\|0x1e\r