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OvmfPkg/PlatformPei: Skip various items for S3 resume
[mirror_edk2.git] / OvmfPkg / PlatformPei / Platform.c
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1/**@file\r
2 Platform PEI driver\r
3\r
4 Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
5 Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
6\r
7 This program and the accompanying materials\r
8 are licensed and made available under the terms and conditions of the BSD License\r
9 which accompanies this distribution. The full text of the license may be found at\r
10 http://opensource.org/licenses/bsd-license.php\r
11\r
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14\r
15**/\r
16\r
17//\r
18// The package level header files this module uses\r
19//\r
20#include <PiPei.h>\r
21\r
22//\r
23// The Library classes this module consumes\r
24//\r
25#include <Library/DebugLib.h>\r
26#include <Library/HobLib.h>\r
27#include <Library/IoLib.h>\r
28#include <Library/MemoryAllocationLib.h>\r
29#include <Library/PcdLib.h>\r
30#include <Library/PciLib.h>\r
31#include <Library/PeimEntryPoint.h>\r
32#include <Library/PeiServicesLib.h>\r
33#include <Library/QemuFwCfgLib.h>\r
34#include <Library/ResourcePublicationLib.h>\r
35#include <Guid/MemoryTypeInformation.h>\r
36#include <Ppi/MasterBootMode.h>\r
37#include <IndustryStandard/Pci22.h>\r
38\r
39#include "Platform.h"\r
40#include "Cmos.h"\r
41\r
42EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r
43 { EfiACPIMemoryNVS, 0x004 },\r
44 { EfiACPIReclaimMemory, 0x008 },\r
45 { EfiReservedMemoryType, 0x004 },\r
46 { EfiRuntimeServicesData, 0x024 },\r
47 { EfiRuntimeServicesCode, 0x030 },\r
48 { EfiBootServicesCode, 0x180 },\r
49 { EfiBootServicesData, 0xF00 },\r
50 { EfiMaxMemoryType, 0x000 }\r
51};\r
52\r
53\r
54EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r
55 {\r
56 EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
57 &gEfiPeiMasterBootModePpiGuid,\r
58 NULL\r
59 }\r
60};\r
61\r
62\r
63EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r
64\r
65BOOLEAN mS3Supported = FALSE;\r
66\r
67\r
68VOID\r
69AddIoMemoryBaseSizeHob (\r
70 EFI_PHYSICAL_ADDRESS MemoryBase,\r
71 UINT64 MemorySize\r
72 )\r
73{\r
74 BuildResourceDescriptorHob (\r
75 EFI_RESOURCE_MEMORY_MAPPED_IO,\r
76 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
77 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
78 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
79 EFI_RESOURCE_ATTRIBUTE_TESTED,\r
80 MemoryBase,\r
81 MemorySize\r
82 );\r
83}\r
84\r
85VOID\r
86AddReservedMemoryBaseSizeHob (\r
87 EFI_PHYSICAL_ADDRESS MemoryBase,\r
88 UINT64 MemorySize\r
89 )\r
90{\r
91 BuildResourceDescriptorHob (\r
92 EFI_RESOURCE_MEMORY_RESERVED,\r
93 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
94 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
95 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
96 EFI_RESOURCE_ATTRIBUTE_TESTED,\r
97 MemoryBase,\r
98 MemorySize\r
99 );\r
100}\r
101\r
102VOID\r
103AddIoMemoryRangeHob (\r
104 EFI_PHYSICAL_ADDRESS MemoryBase,\r
105 EFI_PHYSICAL_ADDRESS MemoryLimit\r
106 )\r
107{\r
108 AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
109}\r
110\r
111\r
112VOID\r
113AddMemoryBaseSizeHob (\r
114 EFI_PHYSICAL_ADDRESS MemoryBase,\r
115 UINT64 MemorySize\r
116 )\r
117{\r
118 BuildResourceDescriptorHob (\r
119 EFI_RESOURCE_SYSTEM_MEMORY,\r
120 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
121 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
122 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
123 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
124 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
125 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
126 EFI_RESOURCE_ATTRIBUTE_TESTED,\r
127 MemoryBase,\r
128 MemorySize\r
129 );\r
130}\r
131\r
132\r
133VOID\r
134AddMemoryRangeHob (\r
135 EFI_PHYSICAL_ADDRESS MemoryBase,\r
136 EFI_PHYSICAL_ADDRESS MemoryLimit\r
137 )\r
138{\r
139 AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
140}\r
141\r
142\r
143VOID\r
144AddUntestedMemoryBaseSizeHob (\r
145 EFI_PHYSICAL_ADDRESS MemoryBase,\r
146 UINT64 MemorySize\r
147 )\r
148{\r
149 BuildResourceDescriptorHob (\r
150 EFI_RESOURCE_SYSTEM_MEMORY,\r
151 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
152 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
153 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
154 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
155 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
156 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,\r
157 MemoryBase,\r
158 MemorySize\r
159 );\r
160}\r
161\r
162\r
163VOID\r
164AddUntestedMemoryRangeHob (\r
165 EFI_PHYSICAL_ADDRESS MemoryBase,\r
166 EFI_PHYSICAL_ADDRESS MemoryLimit\r
167 )\r
168{\r
169 AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
170}\r
171\r
172VOID\r
173MemMapInitialization (\r
174 VOID\r
175 )\r
176{\r
177 //\r
178 // Create Memory Type Information HOB\r
179 //\r
180 BuildGuidDataHob (\r
181 &gEfiMemoryTypeInformationGuid,\r
182 mDefaultMemoryTypeInformation,\r
183 sizeof(mDefaultMemoryTypeInformation)\r
184 );\r
185\r
186 //\r
187 // Add PCI IO Port space available for PCI resource allocations.\r
188 //\r
189 BuildResourceDescriptorHob (\r
190 EFI_RESOURCE_IO,\r
191 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
192 EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
193 0xC000,\r
194 0x4000\r
195 );\r
196\r
197 //\r
198 // Video memory + Legacy BIOS region\r
199 //\r
200 AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
201\r
202 if (!mXen) {\r
203 UINT32 TopOfLowRam;\r
204 TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
205\r
206 //\r
207 // address purpose size\r
208 // ------------ -------- -------------------------\r
209 // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r
210 // 0xFC000000 gap 44 MB\r
211 // 0xFEC00000 IO-APIC 4 KB\r
212 // 0xFEC01000 gap 1020 KB\r
213 // 0xFED00000 HPET 1 KB\r
214 // 0xFED00400 gap 1023 KB\r
215 // 0xFEE00000 LAPIC 1 MB\r
216 //\r
217 AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ?\r
218 BASE_2GB : TopOfLowRam, 0xFC000000);\r
219 AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
220 AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
221 AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
222 }\r
223}\r
224\r
225\r
226VOID\r
227MiscInitialization (\r
228 VOID\r
229 )\r
230{\r
231 //\r
232 // Disable A20 Mask\r
233 //\r
234 IoOr8 (0x92, BIT1);\r
235\r
236 //\r
237 // Build the CPU hob with 36-bit addressing and 16-bits of IO space.\r
238 //\r
239 BuildCpuHob (36, 16);\r
240\r
241 //\r
242 // If PMREGMISC/PMIOSE is set, assume the ACPI PMBA has been configured (for\r
243 // example by Xen) and skip the setup here. This matches the logic in\r
244 // AcpiTimerLibConstructor ().\r
245 //\r
246 if ((PciRead8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80)) & 0x01) == 0) {\r
247 //\r
248 // The PEI phase should be exited with fully accessibe PIIX4 IO space:\r
249 // 1. set PMBA\r
250 //\r
251 PciAndThenOr32 (\r
252 PCI_LIB_ADDRESS (0, 1, 3, 0x40),\r
253 (UINT32) ~0xFFC0,\r
254 PcdGet16 (PcdAcpiPmBaseAddress)\r
255 );\r
256\r
257 //\r
258 // 2. set PCICMD/IOSE\r
259 //\r
260 PciOr8 (\r
261 PCI_LIB_ADDRESS (0, 1, 3, PCI_COMMAND_OFFSET),\r
262 EFI_PCI_COMMAND_IO_SPACE\r
263 );\r
264\r
265 //\r
266 // 3. set PMREGMISC/PMIOSE\r
267 //\r
268 PciOr8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80), 0x01);\r
269 }\r
270}\r
271\r
272\r
273VOID\r
274BootModeInitialization (\r
275 VOID\r
276 )\r
277{\r
278 EFI_STATUS Status;\r
279\r
280 if (CmosRead8 (0xF) == 0xFE) {\r
281 mBootMode = BOOT_ON_S3_RESUME;\r
282 }\r
283\r
284 Status = PeiServicesSetBootMode (mBootMode);\r
285 ASSERT_EFI_ERROR (Status);\r
286\r
287 Status = PeiServicesInstallPpi (mPpiBootMode);\r
288 ASSERT_EFI_ERROR (Status);\r
289}\r
290\r
291\r
292VOID\r
293ReserveEmuVariableNvStore (\r
294 )\r
295{\r
296 EFI_PHYSICAL_ADDRESS VariableStore;\r
297\r
298 //\r
299 // Allocate storage for NV variables early on so it will be\r
300 // at a consistent address. Since VM memory is preserved\r
301 // across reboots, this allows the NV variable storage to survive\r
302 // a VM reboot.\r
303 //\r
304 VariableStore =\r
305 (EFI_PHYSICAL_ADDRESS)(UINTN)\r
306 AllocateAlignedRuntimePages (\r
307 EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),\r
308 PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r
309 );\r
310 DEBUG ((EFI_D_INFO,\r
311 "Reserved variable store memory: 0x%lX; size: %dkb\n",\r
312 VariableStore,\r
313 (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r
314 ));\r
315 PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);\r
316}\r
317\r
318\r
319VOID\r
320DebugDumpCmos (\r
321 VOID\r
322 )\r
323{\r
324 UINTN Loop;\r
325\r
326 DEBUG ((EFI_D_INFO, "CMOS:\n"));\r
327\r
328 for (Loop = 0; Loop < 0x80; Loop++) {\r
329 if ((Loop % 0x10) == 0) {\r
330 DEBUG ((EFI_D_INFO, "%02x:", Loop));\r
331 }\r
332 DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));\r
333 if ((Loop % 0x10) == 0xf) {\r
334 DEBUG ((EFI_D_INFO, "\n"));\r
335 }\r
336 }\r
337}\r
338\r
339\r
340/**\r
341 Perform Platform PEI initialization.\r
342\r
343 @param FileHandle Handle of the file being invoked.\r
344 @param PeiServices Describes the list of possible PEI Services.\r
345\r
346 @return EFI_SUCCESS The PEIM initialized successfully.\r
347\r
348**/\r
349EFI_STATUS\r
350EFIAPI\r
351InitializePlatform (\r
352 IN EFI_PEI_FILE_HANDLE FileHandle,\r
353 IN CONST EFI_PEI_SERVICES **PeiServices\r
354 )\r
355{\r
356 DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
357\r
358 DebugDumpCmos ();\r
359\r
360 XenDetect ();\r
361\r
362 if (QemuFwCfgS3Enabled ()) {\r
363 DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));\r
364 mS3Supported = TRUE;\r
365 }\r
366\r
367 BootModeInitialization ();\r
368\r
369 PublishPeiMemory ();\r
370\r
371 InitializeRamRegions ();\r
372\r
373 if (mXen) {\r
374 DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r
375 InitializeXen ();\r
376 }\r
377\r
378 if (mBootMode != BOOT_ON_S3_RESUME) {\r
379 ReserveEmuVariableNvStore ();\r
380\r
381 PeiFvInitialization ();\r
382\r
383 MemMapInitialization ();\r
384 }\r
385\r
386 MiscInitialization ();\r
387\r
388 return EFI_SUCCESS;\r
389}\r
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