| 1 | ## @file\r |
| 2 | # Public definitions for PcAtChipset package.\r |
| 3 | #\r |
| 4 | # This package is designed to public interfaces and implementation which follows\r |
| 5 | # PcAt defacto standard.\r |
| 6 | #\r |
| 7 | # Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>\r |
| 8 | #\r |
| 9 | # This program and the accompanying materials\r |
| 10 | # are licensed and made available under the terms and conditions of the BSD License\r |
| 11 | # which accompanies this distribution. The full text of the license may be found at\r |
| 12 | # http://opensource.org/licenses/bsd-license.php\r |
| 13 | #\r |
| 14 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 15 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| 16 | #\r |
| 17 | ##\r |
| 18 | \r |
| 19 | [Defines]\r |
| 20 | DEC_SPECIFICATION = 0x00010005\r |
| 21 | PACKAGE_NAME = PcAtChipsetPkg\r |
| 22 | PACKAGE_GUID = B728689A-52D3-4b8c-AE89-2CE5514CC6DC\r |
| 23 | PACKAGE_VERSION = 0.3\r |
| 24 | \r |
| 25 | [Includes]\r |
| 26 | Include\r |
| 27 | \r |
| 28 | [LibraryClasses]\r |
| 29 | ## @libraryclass Provides functions to manage I/O APIC Redirection Table Entries.\r |
| 30 | #\r |
| 31 | IoApicLib|Include/Library/IoApicLib.h\r |
| 32 | \r |
| 33 | [Guids]\r |
| 34 | gPcAtChipsetPkgTokenSpaceGuid = { 0x326ae723, 0xae32, 0x4589, { 0x98, 0xb8, 0xca, 0xc2, 0x3c, 0xdc, 0xc1, 0xb1 } }\r |
| 35 | \r |
| 36 | [PcdsFeatureFlag]\r |
| 37 | ## If TRUE, then the HPET Timer will be configured to use MSI interrupts if the HPET timer supports them.\r |
| 38 | # If FALSE, then the HPET Timer will be configued to use I/O APIC interrupts.\r |
| 39 | gPcAtChipsetPkgTokenSpaceGuid.PcdHpetMsiEnable|TRUE|BOOLEAN|0x00001000\r |
| 40 | \r |
| 41 | [PcdsFixedAtBuild, PcdsDynamic, PcdsDynamicEx, PcdsPatchableInModule]\r |
| 42 | ## Pcd8259LegacyModeMask defines the default mask value for platform. This value is determined\r |
| 43 | # 1) If platform only support pure UEFI, value should be set to 0xFFFF or 0xFFFE;\r |
| 44 | # Because only clock interrupt is allowed in legacy mode in pure UEFI platform.\r |
| 45 | # 2) If platform install CSM and use thunk module:\r |
| 46 | # a) If thunk call provided by CSM binary requires some legacy interrupt support, the corresponding bit \r |
| 47 | # should be opened as 0.\r |
| 48 | # For example, if keyboard interfaces provided CSM binary use legacy keyboard interrupt in 8259 bit 2, then\r |
| 49 | # the value should be set to 0xFFFC\r |
| 50 | # b) If all thunk call provied by CSM binary do not require legacy interrupt support, value should be set\r |
| 51 | # to 0xFFFF or 0xFFFE.\r |
| 52 | #\r |
| 53 | # The default value of legacy mode mask could be changed by EFI_LEGACY_8259_PROTOCOL->SetMask(). But it is rarely\r |
| 54 | # need change it except some special cases such as when initializing the CSM binary, it should be set to 0xFFFF to \r |
| 55 | # mask all legacy interrupt. Please restore the original legacy mask value if changing is made for these special case.\r |
| 56 | #\r |
| 57 | gPcAtChipsetPkgTokenSpaceGuid.Pcd8259LegacyModeMask|0xFFFF|UINT16|0x00000001\r |
| 58 | \r |
| 59 | ## Pcd8259LegacyModeEdgeLevel defines the default edge level for legacy mode's interrrupt controller.\r |
| 60 | gPcAtChipsetPkgTokenSpaceGuid.Pcd8259LegacyModeEdgeLevel|0x0000|UINT16|0x00000002\r |
| 61 | \r |
| 62 | ## This PCD specifies whether we need enable IsaAcpiCom1 device.\r |
| 63 | gPcAtChipsetPkgTokenSpaceGuid.PcdIsaAcpiCom1Enable|TRUE|BOOLEAN|0x00000003\r |
| 64 | \r |
| 65 | ## This PCD specifies whether we need enable IsaAcpiCom2 device.\r |
| 66 | gPcAtChipsetPkgTokenSpaceGuid.PcdIsaAcpiCom2Enable|TRUE|BOOLEAN|0x00000004\r |
| 67 | \r |
| 68 | ## This PCD specifies whether we need enable IsaAcpiPs2Keyboard device.\r |
| 69 | gPcAtChipsetPkgTokenSpaceGuid.PcdIsaAcpiPs2KeyboardEnable|TRUE|BOOLEAN|0x00000005\r |
| 70 | \r |
| 71 | ## This PCD specifies whether we need enable IsaAcpiPs2Mouse device.\r |
| 72 | gPcAtChipsetPkgTokenSpaceGuid.PcdIsaAcpiPs2MouseEnable|TRUE|BOOLEAN|0x00000006\r |
| 73 | \r |
| 74 | ## This PCD specifies whether we need enable IsaAcpiFloppyA device.\r |
| 75 | gPcAtChipsetPkgTokenSpaceGuid.PcdIsaAcpiFloppyAEnable|TRUE|BOOLEAN|0x00000007\r |
| 76 | \r |
| 77 | ## This PCD specifies whether we need enable IsaAcpiFloppyB device.\r |
| 78 | gPcAtChipsetPkgTokenSpaceGuid.PcdIsaAcpiFloppyBEnable|TRUE|BOOLEAN|0x00000008\r |
| 79 | \r |
| 80 | ## This PCD specifies the base address of the HPET timer.\r |
| 81 | gPcAtChipsetPkgTokenSpaceGuid.PcdHpetBaseAddress|0xFED00000|UINT32|0x00000009\r |
| 82 | \r |
| 83 | ## This PCD specifies the Local APIC Interrupt Vector for the HPET Timer.\r |
| 84 | gPcAtChipsetPkgTokenSpaceGuid.PcdHpetLocalApicVector|0x40|UINT8|0x0000000A\r |
| 85 | \r |
| 86 | ## This PCD specifies the defaut period of the HPET Timer in 100 ns units.\r |
| 87 | # The default value of 100000 100 ns units is the same as 10 ms.\r |
| 88 | gPcAtChipsetPkgTokenSpaceGuid.PcdHpetDefaultTimerPeriod|100000|UINT64|0x0000000B\r |
| 89 | \r |
| 90 | ## This PCD specifies the base address of the HPET timer.\r |
| 91 | gPcAtChipsetPkgTokenSpaceGuid.PcdIoApicBaseAddress|0xFEC00000|UINT32|0x0000000C\r |
| 92 | \r |
| 93 | [PcdsFixedAtBuild, PcdsPatchableInModule]\r |
| 94 | ## Defines the ACPI register set base address.\r |
| 95 | # The invalid 0xFFFF is as its default value. It must be configured to the real value. \r |
| 96 | # @Prompt ACPI Timer IO Port Address\r |
| 97 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress |0xFFFF|UINT16|0x00000010\r |
| 98 | \r |
| 99 | ## Defines the PCI Bus Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.\r |
| 100 | # @Prompt ACPI Hardware PCI Bus Number\r |
| 101 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber | 0x00| UINT8|0x00000011\r |
| 102 | \r |
| 103 | ## Defines the PCI Device Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.\r |
| 104 | # The invalid 0xFF is as its default value. It must be configured to the real value. \r |
| 105 | # @Prompt ACPI Hardware PCI Device Number\r |
| 106 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber | 0xFF| UINT8|0x00000012\r |
| 107 | \r |
| 108 | ## Defines the PCI Function Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.\r |
| 109 | # The invalid 0xFF is as its default value. It must be configured to the real value. \r |
| 110 | # @Prompt ACPI Hardware PCI Function Number\r |
| 111 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber | 0xFF| UINT8|0x00000013\r |
| 112 | \r |
| 113 | ## Defines the PCI Register Offset of the PCI device that contains the Enable for ACPI hardware registers.\r |
| 114 | # The invalid 0xFFFF is as its default value. It must be configured to the real value. \r |
| 115 | # @Prompt ACPI Hardware PCI Register Offset\r |
| 116 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset |0xFFFF|UINT16|0x00000014\r |
| 117 | \r |
| 118 | ## Defines the bit mask that must be set to enable the APIC hardware register BAR.\r |
| 119 | # @Prompt ACPI Hardware PCI Bar Enable BitMask\r |
| 120 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask | 0x00| UINT8|0x00000015\r |
| 121 | \r |
| 122 | ## Defines the PCI Register Offset of the PCI device that contains the BAR for ACPI hardware registers.\r |
| 123 | # The invalid 0xFFFF is as its default value. It must be configured to the real value. \r |
| 124 | # @Prompt ACPI Hardware PCI Bar Register Offset\r |
| 125 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset |0xFFFF|UINT16|0x00000016\r |
| 126 | \r |
| 127 | ## Defines the offset to the 32-bit Timer Value register that resides within the ACPI BAR.\r |
| 128 | # @Prompt Offset to 32-bit Timer register in ACPI BAR\r |
| 129 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset |0x0008|UINT16|0x00000017\r |