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1/** @file\r
2 Main file for Pci shell Debug1 function.\r
3\r
4 Copyright (c) 2013 Hewlett-Packard Development Company, L.P.\r
5 Copyright (c) 2005 - 2014, Intel Corporation. All rights reserved.<BR>\r
6 This program and the accompanying materials\r
7 are licensed and made available under the terms and conditions of the BSD License\r
8 which accompanies this distribution. The full text of the license may be found at\r
9 http://opensource.org/licenses/bsd-license.php\r
10\r
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15\r
16#include "UefiShellDebug1CommandsLib.h"\r
17#include <Protocol/PciRootBridgeIo.h>\r
18#include <Library/ShellLib.h>\r
19#include <IndustryStandard/Pci.h>\r
20#include <IndustryStandard/Acpi.h>\r
21#include "Pci.h"\r
22\r
23#define PCI_CLASS_STRING_LIMIT 54\r
24//\r
25// Printable strings for Pci class code\r
26//\r
27typedef struct {\r
28 CHAR16 *BaseClass; // Pointer to the PCI base class string\r
29 CHAR16 *SubClass; // Pointer to the PCI sub class string\r
30 CHAR16 *PIFClass; // Pointer to the PCI programming interface string\r
31} PCI_CLASS_STRINGS;\r
32\r
33//\r
34// a structure holding a single entry, which also points to its lower level\r
35// class\r
36//\r
37typedef struct PCI_CLASS_ENTRY_TAG {\r
38 UINT8 Code; // Class, subclass or I/F code\r
39 CHAR16 *DescText; // Description string\r
40 struct PCI_CLASS_ENTRY_TAG *LowerLevelClass; // Subclass or I/F if any\r
41} PCI_CLASS_ENTRY;\r
42\r
43//\r
44// Declarations of entries which contain printable strings for class codes\r
45// in PCI configuration space\r
46//\r
47PCI_CLASS_ENTRY PCIBlankEntry[];\r
48PCI_CLASS_ENTRY PCISubClass_00[];\r
49PCI_CLASS_ENTRY PCISubClass_01[];\r
50PCI_CLASS_ENTRY PCISubClass_02[];\r
51PCI_CLASS_ENTRY PCISubClass_03[];\r
52PCI_CLASS_ENTRY PCISubClass_04[];\r
53PCI_CLASS_ENTRY PCISubClass_05[];\r
54PCI_CLASS_ENTRY PCISubClass_06[];\r
55PCI_CLASS_ENTRY PCISubClass_07[];\r
56PCI_CLASS_ENTRY PCISubClass_08[];\r
57PCI_CLASS_ENTRY PCISubClass_09[];\r
58PCI_CLASS_ENTRY PCISubClass_0a[];\r
59PCI_CLASS_ENTRY PCISubClass_0b[];\r
60PCI_CLASS_ENTRY PCISubClass_0c[];\r
61PCI_CLASS_ENTRY PCISubClass_0d[];\r
62PCI_CLASS_ENTRY PCISubClass_0e[];\r
63PCI_CLASS_ENTRY PCISubClass_0f[];\r
64PCI_CLASS_ENTRY PCISubClass_10[];\r
65PCI_CLASS_ENTRY PCISubClass_11[];\r
66PCI_CLASS_ENTRY PCIPIFClass_0101[];\r
67PCI_CLASS_ENTRY PCIPIFClass_0300[];\r
68PCI_CLASS_ENTRY PCIPIFClass_0604[];\r
69PCI_CLASS_ENTRY PCIPIFClass_0700[];\r
70PCI_CLASS_ENTRY PCIPIFClass_0701[];\r
71PCI_CLASS_ENTRY PCIPIFClass_0703[];\r
72PCI_CLASS_ENTRY PCIPIFClass_0800[];\r
73PCI_CLASS_ENTRY PCIPIFClass_0801[];\r
74PCI_CLASS_ENTRY PCIPIFClass_0802[];\r
75PCI_CLASS_ENTRY PCIPIFClass_0803[];\r
76PCI_CLASS_ENTRY PCIPIFClass_0904[];\r
77PCI_CLASS_ENTRY PCIPIFClass_0c00[];\r
78PCI_CLASS_ENTRY PCIPIFClass_0c03[];\r
79PCI_CLASS_ENTRY PCIPIFClass_0e00[];\r
80\r
81//\r
82// Base class strings entries\r
83//\r
84PCI_CLASS_ENTRY gClassStringList[] = {\r
85 {\r
86 0x00,\r
87 L"Pre 2.0 device",\r
88 PCISubClass_00\r
89 },\r
90 {\r
91 0x01,\r
92 L"Mass Storage Controller",\r
93 PCISubClass_01\r
94 },\r
95 {\r
96 0x02,\r
97 L"Network Controller",\r
98 PCISubClass_02\r
99 },\r
100 {\r
101 0x03,\r
102 L"Display Controller",\r
103 PCISubClass_03\r
104 },\r
105 {\r
106 0x04,\r
107 L"Multimedia Device",\r
108 PCISubClass_04\r
109 },\r
110 {\r
111 0x05,\r
112 L"Memory Controller",\r
113 PCISubClass_05\r
114 },\r
115 {\r
116 0x06,\r
117 L"Bridge Device",\r
118 PCISubClass_06\r
119 },\r
120 {\r
121 0x07,\r
122 L"Simple Communications Controllers",\r
123 PCISubClass_07\r
124 },\r
125 {\r
126 0x08,\r
127 L"Base System Peripherals",\r
128 PCISubClass_08\r
129 },\r
130 {\r
131 0x09,\r
132 L"Input Devices",\r
133 PCISubClass_09\r
134 },\r
135 {\r
136 0x0a,\r
137 L"Docking Stations",\r
138 PCISubClass_0a\r
139 },\r
140 {\r
141 0x0b,\r
142 L"Processors",\r
143 PCISubClass_0b\r
144 },\r
145 {\r
146 0x0c,\r
147 L"Serial Bus Controllers",\r
148 PCISubClass_0c\r
149 },\r
150 {\r
151 0x0d,\r
152 L"Wireless Controllers",\r
153 PCISubClass_0d\r
154 },\r
155 {\r
156 0x0e,\r
157 L"Intelligent IO Controllers",\r
158 PCISubClass_0e\r
159 },\r
160 {\r
161 0x0f,\r
162 L"Satellite Communications Controllers",\r
163 PCISubClass_0f\r
164 },\r
165 {\r
166 0x10,\r
167 L"Encryption/Decryption Controllers",\r
168 PCISubClass_10\r
169 },\r
170 {\r
171 0x11,\r
172 L"Data Acquisition & Signal Processing Controllers",\r
173 PCISubClass_11\r
174 },\r
175 {\r
176 0xff,\r
177 L"Device does not fit in any defined classes",\r
178 PCIBlankEntry\r
179 },\r
180 {\r
181 0x00,\r
182 NULL,\r
183 /* null string ends the list */NULL\r
184 }\r
185};\r
186\r
187//\r
188// Subclass strings entries\r
189//\r
190PCI_CLASS_ENTRY PCIBlankEntry[] = {\r
191 {\r
192 0x00,\r
193 L"",\r
194 PCIBlankEntry\r
195 },\r
196 {\r
197 0x00,\r
198 NULL,\r
199 /* null string ends the list */NULL\r
200 }\r
201};\r
202\r
203PCI_CLASS_ENTRY PCISubClass_00[] = {\r
204 {\r
205 0x00,\r
206 L"All devices other than VGA",\r
207 PCIBlankEntry\r
208 },\r
209 {\r
210 0x01,\r
211 L"VGA-compatible devices",\r
212 PCIBlankEntry\r
213 },\r
214 {\r
215 0x00,\r
216 NULL,\r
217 /* null string ends the list */NULL\r
218 }\r
219};\r
220\r
221PCI_CLASS_ENTRY PCISubClass_01[] = {\r
222 {\r
223 0x00,\r
224 L"SCSI controller",\r
225 PCIBlankEntry\r
226 },\r
227 {\r
228 0x01,\r
229 L"IDE controller",\r
230 PCIPIFClass_0101\r
231 },\r
232 {\r
233 0x02,\r
234 L"Floppy disk controller",\r
235 PCIBlankEntry\r
236 },\r
237 {\r
238 0x03,\r
239 L"IPI controller",\r
240 PCIBlankEntry\r
241 },\r
242 {\r
243 0x04,\r
244 L"RAID controller",\r
245 PCIBlankEntry\r
246 },\r
247 {\r
248 0x80,\r
249 L"Other mass storage controller",\r
250 PCIBlankEntry\r
251 },\r
252 {\r
253 0x00,\r
254 NULL,\r
255 /* null string ends the list */NULL\r
256 }\r
257};\r
258\r
259PCI_CLASS_ENTRY PCISubClass_02[] = {\r
260 {\r
261 0x00,\r
262 L"Ethernet controller",\r
263 PCIBlankEntry\r
264 },\r
265 {\r
266 0x01,\r
267 L"Token ring controller",\r
268 PCIBlankEntry\r
269 },\r
270 {\r
271 0x02,\r
272 L"FDDI controller",\r
273 PCIBlankEntry\r
274 },\r
275 {\r
276 0x03,\r
277 L"ATM controller",\r
278 PCIBlankEntry\r
279 },\r
280 {\r
281 0x04,\r
282 L"ISDN controller",\r
283 PCIBlankEntry\r
284 },\r
285 {\r
286 0x80,\r
287 L"Other network controller",\r
288 PCIBlankEntry\r
289 },\r
290 {\r
291 0x00,\r
292 NULL,\r
293 /* null string ends the list */NULL\r
294 }\r
295};\r
296\r
297PCI_CLASS_ENTRY PCISubClass_03[] = {\r
298 {\r
299 0x00,\r
300 L"VGA/8514 controller",\r
301 PCIPIFClass_0300\r
302 },\r
303 {\r
304 0x01,\r
305 L"XGA controller",\r
306 PCIBlankEntry\r
307 },\r
308 {\r
309 0x02,\r
310 L"3D controller",\r
311 PCIBlankEntry\r
312 },\r
313 {\r
314 0x80,\r
315 L"Other display controller",\r
316 PCIBlankEntry\r
317 },\r
318 {\r
319 0x00,\r
320 NULL,\r
321 /* null string ends the list */PCIBlankEntry\r
322 }\r
323};\r
324\r
325PCI_CLASS_ENTRY PCISubClass_04[] = {\r
326 {\r
327 0x00,\r
328 L"Video device",\r
329 PCIBlankEntry\r
330 },\r
331 {\r
332 0x01,\r
333 L"Audio device",\r
334 PCIBlankEntry\r
335 },\r
336 {\r
337 0x02,\r
338 L"Computer Telephony device",\r
339 PCIBlankEntry\r
340 },\r
341 {\r
342 0x80,\r
343 L"Other multimedia device",\r
344 PCIBlankEntry\r
345 },\r
346 {\r
347 0x00,\r
348 NULL,\r
349 /* null string ends the list */NULL\r
350 }\r
351};\r
352\r
353PCI_CLASS_ENTRY PCISubClass_05[] = {\r
354 {\r
355 0x00,\r
356 L"RAM memory controller",\r
357 PCIBlankEntry\r
358 },\r
359 {\r
360 0x01,\r
361 L"Flash memory controller",\r
362 PCIBlankEntry\r
363 },\r
364 {\r
365 0x80,\r
366 L"Other memory controller",\r
367 PCIBlankEntry\r
368 },\r
369 {\r
370 0x00,\r
371 NULL,\r
372 /* null string ends the list */NULL\r
373 }\r
374};\r
375\r
376PCI_CLASS_ENTRY PCISubClass_06[] = {\r
377 {\r
378 0x00,\r
379 L"Host/PCI bridge",\r
380 PCIBlankEntry\r
381 },\r
382 {\r
383 0x01,\r
384 L"PCI/ISA bridge",\r
385 PCIBlankEntry\r
386 },\r
387 {\r
388 0x02,\r
389 L"PCI/EISA bridge",\r
390 PCIBlankEntry\r
391 },\r
392 {\r
393 0x03,\r
394 L"PCI/Micro Channel bridge",\r
395 PCIBlankEntry\r
396 },\r
397 {\r
398 0x04,\r
399 L"PCI/PCI bridge",\r
400 PCIPIFClass_0604\r
401 },\r
402 {\r
403 0x05,\r
404 L"PCI/PCMCIA bridge",\r
405 PCIBlankEntry\r
406 },\r
407 {\r
408 0x06,\r
409 L"NuBus bridge",\r
410 PCIBlankEntry\r
411 },\r
412 {\r
413 0x07,\r
414 L"CardBus bridge",\r
415 PCIBlankEntry\r
416 },\r
417 {\r
418 0x08,\r
419 L"RACEway bridge",\r
420 PCIBlankEntry\r
421 },\r
422 {\r
423 0x80,\r
424 L"Other bridge type",\r
425 PCIBlankEntry\r
426 },\r
427 {\r
428 0x00,\r
429 NULL,\r
430 /* null string ends the list */NULL\r
431 }\r
432};\r
433\r
434PCI_CLASS_ENTRY PCISubClass_07[] = {\r
435 {\r
436 0x00,\r
437 L"Serial controller",\r
438 PCIPIFClass_0700\r
439 },\r
440 {\r
441 0x01,\r
442 L"Parallel port",\r
443 PCIPIFClass_0701\r
444 },\r
445 {\r
446 0x02,\r
447 L"Multiport serial controller",\r
448 PCIBlankEntry\r
449 },\r
450 {\r
451 0x03,\r
452 L"Modem",\r
453 PCIPIFClass_0703\r
454 },\r
455 {\r
456 0x80,\r
457 L"Other communication device",\r
458 PCIBlankEntry\r
459 },\r
460 {\r
461 0x00,\r
462 NULL,\r
463 /* null string ends the list */NULL\r
464 }\r
465};\r
466\r
467PCI_CLASS_ENTRY PCISubClass_08[] = {\r
468 {\r
469 0x00,\r
470 L"PIC",\r
471 PCIPIFClass_0800\r
472 },\r
473 {\r
474 0x01,\r
475 L"DMA controller",\r
476 PCIPIFClass_0801\r
477 },\r
478 {\r
479 0x02,\r
480 L"System timer",\r
481 PCIPIFClass_0802\r
482 },\r
483 {\r
484 0x03,\r
485 L"RTC controller",\r
486 PCIPIFClass_0803\r
487 },\r
488 {\r
489 0x04,\r
490 L"Generic PCI Hot-Plug controller",\r
491 PCIBlankEntry\r
492 },\r
493 {\r
494 0x80,\r
495 L"Other system peripheral",\r
496 PCIBlankEntry\r
497 },\r
498 {\r
499 0x00,\r
500 NULL,\r
501 /* null string ends the list */NULL\r
502 }\r
503};\r
504\r
505PCI_CLASS_ENTRY PCISubClass_09[] = {\r
506 {\r
507 0x00,\r
508 L"Keyboard controller",\r
509 PCIBlankEntry\r
510 },\r
511 {\r
512 0x01,\r
513 L"Digitizer (pen)",\r
514 PCIBlankEntry\r
515 },\r
516 {\r
517 0x02,\r
518 L"Mouse controller",\r
519 PCIBlankEntry\r
520 },\r
521 {\r
522 0x03,\r
523 L"Scanner controller",\r
524 PCIBlankEntry\r
525 },\r
526 {\r
527 0x04,\r
528 L"Gameport controller",\r
529 PCIPIFClass_0904\r
530 },\r
531 {\r
532 0x80,\r
533 L"Other input controller",\r
534 PCIBlankEntry\r
535 },\r
536 {\r
537 0x00,\r
538 NULL,\r
539 /* null string ends the list */NULL\r
540 }\r
541};\r
542\r
543PCI_CLASS_ENTRY PCISubClass_0a[] = {\r
544 {\r
545 0x00,\r
546 L"Generic docking station",\r
547 PCIBlankEntry\r
548 },\r
549 {\r
550 0x80,\r
551 L"Other type of docking station",\r
552 PCIBlankEntry\r
553 },\r
554 {\r
555 0x00,\r
556 NULL,\r
557 /* null string ends the list */NULL\r
558 }\r
559};\r
560\r
561PCI_CLASS_ENTRY PCISubClass_0b[] = {\r
562 {\r
563 0x00,\r
564 L"386",\r
565 PCIBlankEntry\r
566 },\r
567 {\r
568 0x01,\r
569 L"486",\r
570 PCIBlankEntry\r
571 },\r
572 {\r
573 0x02,\r
574 L"Pentium",\r
575 PCIBlankEntry\r
576 },\r
577 {\r
578 0x10,\r
579 L"Alpha",\r
580 PCIBlankEntry\r
581 },\r
582 {\r
583 0x20,\r
584 L"PowerPC",\r
585 PCIBlankEntry\r
586 },\r
587 {\r
588 0x30,\r
589 L"MIPS",\r
590 PCIBlankEntry\r
591 },\r
592 {\r
593 0x40,\r
594 L"Co-processor",\r
595 PCIBlankEntry\r
596 },\r
597 {\r
598 0x80,\r
599 L"Other processor",\r
600 PCIBlankEntry\r
601 },\r
602 {\r
603 0x00,\r
604 NULL,\r
605 /* null string ends the list */NULL\r
606 }\r
607};\r
608\r
609PCI_CLASS_ENTRY PCISubClass_0c[] = {\r
610 {\r
611 0x00,\r
612 L"Firewire(IEEE 1394)",\r
613 PCIPIFClass_0c03\r
614 },\r
615 {\r
616 0x01,\r
617 L"ACCESS.bus",\r
618 PCIBlankEntry\r
619 },\r
620 {\r
621 0x02,\r
622 L"SSA",\r
623 PCIBlankEntry\r
624 },\r
625 {\r
626 0x03,\r
627 L"USB",\r
628 PCIPIFClass_0c00\r
629 },\r
630 {\r
631 0x04,\r
632 L"Fibre Channel",\r
633 PCIBlankEntry\r
634 },\r
635 {\r
636 0x05,\r
637 L"System Management Bus",\r
638 PCIBlankEntry\r
639 },\r
640 {\r
641 0x80,\r
642 L"Other bus type",\r
643 PCIBlankEntry\r
644 },\r
645 {\r
646 0x00,\r
647 NULL,\r
648 /* null string ends the list */NULL\r
649 }\r
650};\r
651\r
652PCI_CLASS_ENTRY PCISubClass_0d[] = {\r
653 {\r
654 0x00,\r
655 L"iRDA compatible controller",\r
656 PCIBlankEntry\r
657 },\r
658 {\r
659 0x01,\r
660 L"Consumer IR controller",\r
661 PCIBlankEntry\r
662 },\r
663 {\r
664 0x10,\r
665 L"RF controller",\r
666 PCIBlankEntry\r
667 },\r
668 {\r
669 0x80,\r
670 L"Other type of wireless controller",\r
671 PCIBlankEntry\r
672 },\r
673 {\r
674 0x00,\r
675 NULL,\r
676 /* null string ends the list */NULL\r
677 }\r
678};\r
679\r
680PCI_CLASS_ENTRY PCISubClass_0e[] = {\r
681 {\r
682 0x00,\r
683 L"I2O Architecture",\r
684 PCIPIFClass_0e00\r
685 },\r
686 {\r
687 0x00,\r
688 NULL,\r
689 /* null string ends the list */NULL\r
690 }\r
691};\r
692\r
693PCI_CLASS_ENTRY PCISubClass_0f[] = {\r
694 {\r
695 0x00,\r
696 L"TV",\r
697 PCIBlankEntry\r
698 },\r
699 {\r
700 0x01,\r
701 L"Audio",\r
702 PCIBlankEntry\r
703 },\r
704 {\r
705 0x02,\r
706 L"Voice",\r
707 PCIBlankEntry\r
708 },\r
709 {\r
710 0x03,\r
711 L"Data",\r
712 PCIBlankEntry\r
713 },\r
714 {\r
715 0x00,\r
716 NULL,\r
717 /* null string ends the list */NULL\r
718 }\r
719};\r
720\r
721PCI_CLASS_ENTRY PCISubClass_10[] = {\r
722 {\r
723 0x00,\r
724 L"Network & computing Encrypt/Decrypt",\r
725 PCIBlankEntry\r
726 },\r
727 {\r
728 0x01,\r
729 L"Entertainment Encrypt/Decrypt",\r
730 PCIBlankEntry\r
731 },\r
732 {\r
733 0x80,\r
734 L"Other Encrypt/Decrypt",\r
735 PCIBlankEntry\r
736 },\r
737 {\r
738 0x00,\r
739 NULL,\r
740 /* null string ends the list */NULL\r
741 }\r
742};\r
743\r
744PCI_CLASS_ENTRY PCISubClass_11[] = {\r
745 {\r
746 0x00,\r
747 L"DPIO modules",\r
748 PCIBlankEntry\r
749 },\r
750 {\r
751 0x80,\r
752 L"Other DAQ & SP controllers",\r
753 PCIBlankEntry\r
754 },\r
755 {\r
756 0x00,\r
757 NULL,\r
758 /* null string ends the list */NULL\r
759 }\r
760};\r
761\r
762//\r
763// Programming Interface entries\r
764//\r
765PCI_CLASS_ENTRY PCIPIFClass_0101[] = {\r
766 {\r
767 0x00,\r
768 L"",\r
769 PCIBlankEntry\r
770 },\r
771 {\r
772 0x01,\r
773 L"OM-primary",\r
774 PCIBlankEntry\r
775 },\r
776 {\r
777 0x02,\r
778 L"PI-primary",\r
779 PCIBlankEntry\r
780 },\r
781 {\r
782 0x03,\r
783 L"OM/PI-primary",\r
784 PCIBlankEntry\r
785 },\r
786 {\r
787 0x04,\r
788 L"OM-secondary",\r
789 PCIBlankEntry\r
790 },\r
791 {\r
792 0x05,\r
793 L"OM-primary, OM-secondary",\r
794 PCIBlankEntry\r
795 },\r
796 {\r
797 0x06,\r
798 L"PI-primary, OM-secondary",\r
799 PCIBlankEntry\r
800 },\r
801 {\r
802 0x07,\r
803 L"OM/PI-primary, OM-secondary",\r
804 PCIBlankEntry\r
805 },\r
806 {\r
807 0x08,\r
808 L"OM-secondary",\r
809 PCIBlankEntry\r
810 },\r
811 {\r
812 0x09,\r
813 L"OM-primary, PI-secondary",\r
814 PCIBlankEntry\r
815 },\r
816 {\r
817 0x0a,\r
818 L"PI-primary, PI-secondary",\r
819 PCIBlankEntry\r
820 },\r
821 {\r
822 0x0b,\r
823 L"OM/PI-primary, PI-secondary",\r
824 PCIBlankEntry\r
825 },\r
826 {\r
827 0x0c,\r
828 L"OM-secondary",\r
829 PCIBlankEntry\r
830 },\r
831 {\r
832 0x0d,\r
833 L"OM-primary, OM/PI-secondary",\r
834 PCIBlankEntry\r
835 },\r
836 {\r
837 0x0e,\r
838 L"PI-primary, OM/PI-secondary",\r
839 PCIBlankEntry\r
840 },\r
841 {\r
842 0x0f,\r
843 L"OM/PI-primary, OM/PI-secondary",\r
844 PCIBlankEntry\r
845 },\r
846 {\r
847 0x80,\r
848 L"Master",\r
849 PCIBlankEntry\r
850 },\r
851 {\r
852 0x81,\r
853 L"Master, OM-primary",\r
854 PCIBlankEntry\r
855 },\r
856 {\r
857 0x82,\r
858 L"Master, PI-primary",\r
859 PCIBlankEntry\r
860 },\r
861 {\r
862 0x83,\r
863 L"Master, OM/PI-primary",\r
864 PCIBlankEntry\r
865 },\r
866 {\r
867 0x84,\r
868 L"Master, OM-secondary",\r
869 PCIBlankEntry\r
870 },\r
871 {\r
872 0x85,\r
873 L"Master, OM-primary, OM-secondary",\r
874 PCIBlankEntry\r
875 },\r
876 {\r
877 0x86,\r
878 L"Master, PI-primary, OM-secondary",\r
879 PCIBlankEntry\r
880 },\r
881 {\r
882 0x87,\r
883 L"Master, OM/PI-primary, OM-secondary",\r
884 PCIBlankEntry\r
885 },\r
886 {\r
887 0x88,\r
888 L"Master, OM-secondary",\r
889 PCIBlankEntry\r
890 },\r
891 {\r
892 0x89,\r
893 L"Master, OM-primary, PI-secondary",\r
894 PCIBlankEntry\r
895 },\r
896 {\r
897 0x8a,\r
898 L"Master, PI-primary, PI-secondary",\r
899 PCIBlankEntry\r
900 },\r
901 {\r
902 0x8b,\r
903 L"Master, OM/PI-primary, PI-secondary",\r
904 PCIBlankEntry\r
905 },\r
906 {\r
907 0x8c,\r
908 L"Master, OM-secondary",\r
909 PCIBlankEntry\r
910 },\r
911 {\r
912 0x8d,\r
913 L"Master, OM-primary, OM/PI-secondary",\r
914 PCIBlankEntry\r
915 },\r
916 {\r
917 0x8e,\r
918 L"Master, PI-primary, OM/PI-secondary",\r
919 PCIBlankEntry\r
920 },\r
921 {\r
922 0x8f,\r
923 L"Master, OM/PI-primary, OM/PI-secondary",\r
924 PCIBlankEntry\r
925 },\r
926 {\r
927 0x00,\r
928 NULL,\r
929 /* null string ends the list */NULL\r
930 }\r
931};\r
932\r
933PCI_CLASS_ENTRY PCIPIFClass_0300[] = {\r
934 {\r
935 0x00,\r
936 L"VGA compatible",\r
937 PCIBlankEntry\r
938 },\r
939 {\r
940 0x01,\r
941 L"8514 compatible",\r
942 PCIBlankEntry\r
943 },\r
944 {\r
945 0x00,\r
946 NULL,\r
947 /* null string ends the list */NULL\r
948 }\r
949};\r
950\r
951PCI_CLASS_ENTRY PCIPIFClass_0604[] = {\r
952 {\r
953 0x00,\r
954 L"",\r
955 PCIBlankEntry\r
956 },\r
957 {\r
958 0x01,\r
959 L"Subtractive decode",\r
960 PCIBlankEntry\r
961 },\r
962 {\r
963 0x00,\r
964 NULL,\r
965 /* null string ends the list */NULL\r
966 }\r
967};\r
968\r
969PCI_CLASS_ENTRY PCIPIFClass_0700[] = {\r
970 {\r
971 0x00,\r
972 L"Generic XT-compatible",\r
973 PCIBlankEntry\r
974 },\r
975 {\r
976 0x01,\r
977 L"16450-compatible",\r
978 PCIBlankEntry\r
979 },\r
980 {\r
981 0x02,\r
982 L"16550-compatible",\r
983 PCIBlankEntry\r
984 },\r
985 {\r
986 0x03,\r
987 L"16650-compatible",\r
988 PCIBlankEntry\r
989 },\r
990 {\r
991 0x04,\r
992 L"16750-compatible",\r
993 PCIBlankEntry\r
994 },\r
995 {\r
996 0x05,\r
997 L"16850-compatible",\r
998 PCIBlankEntry\r
999 },\r
1000 {\r
1001 0x06,\r
1002 L"16950-compatible",\r
1003 PCIBlankEntry\r
1004 },\r
1005 {\r
1006 0x00,\r
1007 NULL,\r
1008 /* null string ends the list */NULL\r
1009 }\r
1010};\r
1011\r
1012PCI_CLASS_ENTRY PCIPIFClass_0701[] = {\r
1013 {\r
1014 0x00,\r
1015 L"",\r
1016 PCIBlankEntry\r
1017 },\r
1018 {\r
1019 0x01,\r
1020 L"Bi-directional",\r
1021 PCIBlankEntry\r
1022 },\r
1023 {\r
1024 0x02,\r
1025 L"ECP 1.X-compliant",\r
1026 PCIBlankEntry\r
1027 },\r
1028 {\r
1029 0x03,\r
1030 L"IEEE 1284",\r
1031 PCIBlankEntry\r
1032 },\r
1033 {\r
1034 0xfe,\r
1035 L"IEEE 1284 target (not a controller)",\r
1036 PCIBlankEntry\r
1037 },\r
1038 {\r
1039 0x00,\r
1040 NULL,\r
1041 /* null string ends the list */NULL\r
1042 }\r
1043};\r
1044\r
1045PCI_CLASS_ENTRY PCIPIFClass_0703[] = {\r
1046 {\r
1047 0x00,\r
1048 L"Generic",\r
1049 PCIBlankEntry\r
1050 },\r
1051 {\r
1052 0x01,\r
1053 L"Hayes-compatible 16450",\r
1054 PCIBlankEntry\r
1055 },\r
1056 {\r
1057 0x02,\r
1058 L"Hayes-compatible 16550",\r
1059 PCIBlankEntry\r
1060 },\r
1061 {\r
1062 0x03,\r
1063 L"Hayes-compatible 16650",\r
1064 PCIBlankEntry\r
1065 },\r
1066 {\r
1067 0x04,\r
1068 L"Hayes-compatible 16750",\r
1069 PCIBlankEntry\r
1070 },\r
1071 {\r
1072 0x00,\r
1073 NULL,\r
1074 /* null string ends the list */NULL\r
1075 }\r
1076};\r
1077\r
1078PCI_CLASS_ENTRY PCIPIFClass_0800[] = {\r
1079 {\r
1080 0x00,\r
1081 L"Generic 8259",\r
1082 PCIBlankEntry\r
1083 },\r
1084 {\r
1085 0x01,\r
1086 L"ISA",\r
1087 PCIBlankEntry\r
1088 },\r
1089 {\r
1090 0x02,\r
1091 L"EISA",\r
1092 PCIBlankEntry\r
1093 },\r
1094 {\r
1095 0x10,\r
1096 L"IO APIC",\r
1097 PCIBlankEntry\r
1098 },\r
1099 {\r
1100 0x20,\r
1101 L"IO(x) APIC interrupt controller",\r
1102 PCIBlankEntry\r
1103 },\r
1104 {\r
1105 0x00,\r
1106 NULL,\r
1107 /* null string ends the list */NULL\r
1108 }\r
1109};\r
1110\r
1111PCI_CLASS_ENTRY PCIPIFClass_0801[] = {\r
1112 {\r
1113 0x00,\r
1114 L"Generic 8237",\r
1115 PCIBlankEntry\r
1116 },\r
1117 {\r
1118 0x01,\r
1119 L"ISA",\r
1120 PCIBlankEntry\r
1121 },\r
1122 {\r
1123 0x02,\r
1124 L"EISA",\r
1125 PCIBlankEntry\r
1126 },\r
1127 {\r
1128 0x00,\r
1129 NULL,\r
1130 /* null string ends the list */NULL\r
1131 }\r
1132};\r
1133\r
1134PCI_CLASS_ENTRY PCIPIFClass_0802[] = {\r
1135 {\r
1136 0x00,\r
1137 L"Generic 8254",\r
1138 PCIBlankEntry\r
1139 },\r
1140 {\r
1141 0x01,\r
1142 L"ISA",\r
1143 PCIBlankEntry\r
1144 },\r
1145 {\r
1146 0x02,\r
1147 L"EISA",\r
1148 PCIBlankEntry\r
1149 },\r
1150 {\r
1151 0x00,\r
1152 NULL,\r
1153 /* null string ends the list */NULL\r
1154 }\r
1155};\r
1156\r
1157PCI_CLASS_ENTRY PCIPIFClass_0803[] = {\r
1158 {\r
1159 0x00,\r
1160 L"Generic",\r
1161 PCIBlankEntry\r
1162 },\r
1163 {\r
1164 0x01,\r
1165 L"ISA",\r
1166 PCIBlankEntry\r
1167 },\r
1168 {\r
1169 0x02,\r
1170 L"EISA",\r
1171 PCIBlankEntry\r
1172 },\r
1173 {\r
1174 0x00,\r
1175 NULL,\r
1176 /* null string ends the list */NULL\r
1177 }\r
1178};\r
1179\r
1180PCI_CLASS_ENTRY PCIPIFClass_0904[] = {\r
1181 {\r
1182 0x00,\r
1183 L"Generic",\r
1184 PCIBlankEntry\r
1185 },\r
1186 {\r
1187 0x10,\r
1188 L"",\r
1189 PCIBlankEntry\r
1190 },\r
1191 {\r
1192 0x00,\r
1193 NULL,\r
1194 /* null string ends the list */NULL\r
1195 }\r
1196};\r
1197\r
1198PCI_CLASS_ENTRY PCIPIFClass_0c00[] = {\r
1199 {\r
1200 0x00,\r
1201 L"Universal Host Controller spec",\r
1202 PCIBlankEntry\r
1203 },\r
1204 {\r
1205 0x10,\r
1206 L"Open Host Controller spec",\r
1207 PCIBlankEntry\r
1208 },\r
1209 {\r
1210 0x80,\r
1211 L"No specific programming interface",\r
1212 PCIBlankEntry\r
1213 },\r
1214 {\r
1215 0xfe,\r
1216 L"(Not Host Controller)",\r
1217 PCIBlankEntry\r
1218 },\r
1219 {\r
1220 0x00,\r
1221 NULL,\r
1222 /* null string ends the list */NULL\r
1223 }\r
1224};\r
1225\r
1226PCI_CLASS_ENTRY PCIPIFClass_0c03[] = {\r
1227 {\r
1228 0x00,\r
1229 L"",\r
1230 PCIBlankEntry\r
1231 },\r
1232 {\r
1233 0x10,\r
1234 L"Using 1394 OpenHCI spec",\r
1235 PCIBlankEntry\r
1236 },\r
1237 {\r
1238 0x00,\r
1239 NULL,\r
1240 /* null string ends the list */NULL\r
1241 }\r
1242};\r
1243\r
1244PCI_CLASS_ENTRY PCIPIFClass_0e00[] = {\r
1245 {\r
1246 0x00,\r
1247 L"Message FIFO at offset 40h",\r
1248 PCIBlankEntry\r
1249 },\r
1250 {\r
1251 0x01,\r
1252 L"",\r
1253 PCIBlankEntry\r
1254 },\r
1255 {\r
1256 0x00,\r
1257 NULL,\r
1258 /* null string ends the list */NULL\r
1259 }\r
1260};\r
1261\r
1262\r
1263/**\r
1264 Generates printable Unicode strings that represent PCI device class,\r
1265 subclass and programmed I/F based on a value passed to the function.\r
1266\r
1267 @param[in] ClassCode Value representing the PCI "Class Code" register read from a\r
1268 PCI device. The encodings are:\r
1269 bits 23:16 - Base Class Code\r
1270 bits 15:8 - Sub-Class Code\r
1271 bits 7:0 - Programming Interface\r
1272 @param[in, out] ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains\r
1273 printable class strings corresponding to ClassCode. The\r
1274 caller must not modify the strings that are pointed by\r
1275 the fields in ClassStrings.\r
1276**/\r
1277VOID\r
1278PciGetClassStrings (\r
1279 IN UINT32 ClassCode,\r
1280 IN OUT PCI_CLASS_STRINGS *ClassStrings\r
1281 )\r
1282{\r
1283 INTN Index;\r
1284 UINT8 Code;\r
1285 PCI_CLASS_ENTRY *CurrentClass;\r
1286\r
1287 //\r
1288 // Assume no strings found\r
1289 //\r
1290 ClassStrings->BaseClass = L"UNDEFINED";\r
1291 ClassStrings->SubClass = L"UNDEFINED";\r
1292 ClassStrings->PIFClass = L"UNDEFINED";\r
1293\r
1294 CurrentClass = gClassStringList;\r
1295 Code = (UINT8) (ClassCode >> 16);\r
1296 Index = 0;\r
1297\r
1298 //\r
1299 // Go through all entries of the base class, until the entry with a matching\r
1300 // base class code is found. If reaches an entry with a null description\r
1301 // text, the last entry is met, which means no text for the base class was\r
1302 // found, so no more action is needed.\r
1303 //\r
1304 while (Code != CurrentClass[Index].Code) {\r
1305 if (NULL == CurrentClass[Index].DescText) {\r
1306 return ;\r
1307 }\r
1308\r
1309 Index++;\r
1310 }\r
1311 //\r
1312 // A base class was found. Assign description, and check if this class has\r
1313 // sub-class defined. If sub-class defined, no more action is needed,\r
1314 // otherwise, continue to find description for the sub-class code.\r
1315 //\r
1316 ClassStrings->BaseClass = CurrentClass[Index].DescText;\r
1317 if (NULL == CurrentClass[Index].LowerLevelClass) {\r
1318 return ;\r
1319 }\r
1320 //\r
1321 // find Subclass entry\r
1322 //\r
1323 CurrentClass = CurrentClass[Index].LowerLevelClass;\r
1324 Code = (UINT8) (ClassCode >> 8);\r
1325 Index = 0;\r
1326\r
1327 //\r
1328 // Go through all entries of the sub-class, until the entry with a matching\r
1329 // sub-class code is found. If reaches an entry with a null description\r
1330 // text, the last entry is met, which means no text for the sub-class was\r
1331 // found, so no more action is needed.\r
1332 //\r
1333 while (Code != CurrentClass[Index].Code) {\r
1334 if (NULL == CurrentClass[Index].DescText) {\r
1335 return ;\r
1336 }\r
1337\r
1338 Index++;\r
1339 }\r
1340 //\r
1341 // A class was found for the sub-class code. Assign description, and check if\r
1342 // this sub-class has programming interface defined. If no, no more action is\r
1343 // needed, otherwise, continue to find description for the programming\r
1344 // interface.\r
1345 //\r
1346 ClassStrings->SubClass = CurrentClass[Index].DescText;\r
1347 if (NULL == CurrentClass[Index].LowerLevelClass) {\r
1348 return ;\r
1349 }\r
1350 //\r
1351 // Find programming interface entry\r
1352 //\r
1353 CurrentClass = CurrentClass[Index].LowerLevelClass;\r
1354 Code = (UINT8) ClassCode;\r
1355 Index = 0;\r
1356\r
1357 //\r
1358 // Go through all entries of the I/F entries, until the entry with a\r
1359 // matching I/F code is found. If reaches an entry with a null description\r
1360 // text, the last entry is met, which means no text was found, so no more\r
1361 // action is needed.\r
1362 //\r
1363 while (Code != CurrentClass[Index].Code) {\r
1364 if (NULL == CurrentClass[Index].DescText) {\r
1365 return ;\r
1366 }\r
1367\r
1368 Index++;\r
1369 }\r
1370 //\r
1371 // A class was found for the I/F code. Assign description, done!\r
1372 //\r
1373 ClassStrings->PIFClass = CurrentClass[Index].DescText;\r
1374 return ;\r
1375}\r
1376\r
1377/**\r
1378 Print strings that represent PCI device class, subclass and programmed I/F.\r
1379\r
1380 @param[in] ClassCodePtr Points to the memory which stores register Class Code in PCI\r
1381 configuation space.\r
1382 @param[in] IncludePIF If the printed string should include the programming I/F part\r
1383**/\r
1384VOID\r
1385PciPrintClassCode (\r
1386 IN UINT8 *ClassCodePtr,\r
1387 IN BOOLEAN IncludePIF\r
1388 )\r
1389{\r
1390 UINT32 ClassCode;\r
1391 PCI_CLASS_STRINGS ClassStrings;\r
1392\r
1393 ClassCode = 0;\r
1394 ClassCode |= ClassCodePtr[0];\r
1395 ClassCode |= (ClassCodePtr[1] << 8);\r
1396 ClassCode |= (ClassCodePtr[2] << 16);\r
1397\r
1398 //\r
1399 // Get name from class code\r
1400 //\r
1401 PciGetClassStrings (ClassCode, &ClassStrings);\r
1402\r
1403 if (IncludePIF) {\r
1404 //\r
1405 // Print base class, sub class, and programming inferface name\r
1406 //\r
1407 ShellPrintEx (-1, -1, L"%s - %s - %s",\r
1408 ClassStrings.BaseClass,\r
1409 ClassStrings.SubClass,\r
1410 ClassStrings.PIFClass\r
1411 );\r
1412\r
1413 } else {\r
1414 //\r
1415 // Only print base class and sub class name\r
1416 //\r
1417 ShellPrintEx (-1, -1, L"%s - %s",\r
1418 ClassStrings.BaseClass,\r
1419 ClassStrings.SubClass\r
1420 );\r
1421 }\r
1422}\r
1423\r
1424/**\r
1425 This function finds out the protocol which is in charge of the given\r
1426 segment, and its bus range covers the current bus number. It lookes\r
1427 each instances of RootBridgeIoProtocol handle, until the one meets the\r
1428 criteria is found.\r
1429\r
1430 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
1431 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
1432 @param[in] Segment Segment number of device we are dealing with.\r
1433 @param[in] Bus Bus number of device we are dealing with.\r
1434 @param[out] IoDev Handle used to access configuration space of PCI device.\r
1435\r
1436 @retval EFI_SUCCESS The command completed successfully.\r
1437 @retval EFI_INVALID_PARAMETER Invalid parameter.\r
1438\r
1439**/\r
1440EFI_STATUS\r
1441PciFindProtocolInterface (\r
1442 IN EFI_HANDLE *HandleBuf,\r
1443 IN UINTN HandleCount,\r
1444 IN UINT16 Segment,\r
1445 IN UINT16 Bus,\r
1446 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r
1447 );\r
1448\r
1449/**\r
1450 This function gets the protocol interface from the given handle, and\r
1451 obtains its address space descriptors.\r
1452\r
1453 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.\r
1454 @param[out] IoDev Handle used to access configuration space of PCI device.\r
1455 @param[out] Descriptors Points to the address space descriptors.\r
1456\r
1457 @retval EFI_SUCCESS The command completed successfully\r
1458**/\r
1459EFI_STATUS\r
1460PciGetProtocolAndResource (\r
1461 IN EFI_HANDLE Handle,\r
1462 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r
1463 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r
1464 );\r
1465\r
1466/**\r
1467 This function get the next bus range of given address space descriptors.\r
1468 It also moves the pointer backward a node, to get prepared to be called\r
1469 again.\r
1470\r
1471 @param[in, out] Descriptors Points to current position of a serial of address space\r
1472 descriptors.\r
1473 @param[out] MinBus The lower range of bus number.\r
1474 @param[out] MaxBus The upper range of bus number.\r
1475 @param[out] IsEnd Meet end of the serial of descriptors.\r
1476\r
1477 @retval EFI_SUCCESS The command completed successfully.\r
1478**/\r
1479EFI_STATUS\r
1480PciGetNextBusRange (\r
1481 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,\r
1482 OUT UINT16 *MinBus,\r
1483 OUT UINT16 *MaxBus,\r
1484 OUT BOOLEAN *IsEnd\r
1485 );\r
1486\r
1487/**\r
1488 Explain the data in PCI configuration space. The part which is common for\r
1489 PCI device and bridge is interpreted in this function. It calls other\r
1490 functions to interpret data unique for device or bridge.\r
1491\r
1492 @param[in] ConfigSpace Data in PCI configuration space.\r
1493 @param[in] Address Address used to access configuration space of this PCI device.\r
1494 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1495 @param[in] EnhancedDump The print format for the dump data.\r
1496\r
1497 @retval EFI_SUCCESS The command completed successfully.\r
1498**/\r
1499EFI_STATUS\r
1500PciExplainData (\r
1501 IN PCI_CONFIG_SPACE *ConfigSpace,\r
1502 IN UINT64 Address,\r
1503 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
1504 IN CONST UINT16 EnhancedDump\r
1505 );\r
1506\r
1507/**\r
1508 Explain the device specific part of data in PCI configuration space.\r
1509\r
1510 @param[in] Device Data in PCI configuration space.\r
1511 @param[in] Address Address used to access configuration space of this PCI device.\r
1512 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1513\r
1514 @retval EFI_SUCCESS The command completed successfully.\r
1515**/\r
1516EFI_STATUS\r
1517PciExplainDeviceData (\r
1518 IN PCI_DEVICE_HEADER *Device,\r
1519 IN UINT64 Address,\r
1520 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
1521 );\r
1522\r
1523/**\r
1524 Explain the bridge specific part of data in PCI configuration space.\r
1525\r
1526 @param[in] Bridge Bridge specific data region in PCI configuration space.\r
1527 @param[in] Address Address used to access configuration space of this PCI device.\r
1528 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1529\r
1530 @retval EFI_SUCCESS The command completed successfully.\r
1531**/\r
1532EFI_STATUS\r
1533PciExplainBridgeData (\r
1534 IN PCI_BRIDGE_HEADER *Bridge,\r
1535 IN UINT64 Address,\r
1536 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
1537 );\r
1538\r
1539/**\r
1540 Explain the Base Address Register(Bar) in PCI configuration space.\r
1541\r
1542 @param[in] Bar Points to the Base Address Register intended to interpret.\r
1543 @param[in] Command Points to the register Command.\r
1544 @param[in] Address Address used to access configuration space of this PCI device.\r
1545 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1546 @param[in, out] Index The Index.\r
1547\r
1548 @retval EFI_SUCCESS The command completed successfully.\r
1549**/\r
1550EFI_STATUS\r
1551PciExplainBar (\r
1552 IN UINT32 *Bar,\r
1553 IN UINT16 *Command,\r
1554 IN UINT64 Address,\r
1555 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
1556 IN OUT UINTN *Index\r
1557 );\r
1558\r
1559/**\r
1560 Explain the cardbus specific part of data in PCI configuration space.\r
1561\r
1562 @param[in] CardBus CardBus specific region of PCI configuration space.\r
1563 @param[in] Address Address used to access configuration space of this PCI device.\r
1564 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1565\r
1566 @retval EFI_SUCCESS The command completed successfully.\r
1567**/\r
1568EFI_STATUS\r
1569PciExplainCardBusData (\r
1570 IN PCI_CARDBUS_HEADER *CardBus,\r
1571 IN UINT64 Address,\r
1572 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
1573 );\r
1574\r
1575/**\r
1576 Explain each meaningful bit of register Status. The definition of Status is\r
1577 slightly different depending on the PCI header type.\r
1578\r
1579 @param[in] Status Points to the content of register Status.\r
1580 @param[in] MainStatus Indicates if this register is main status(not secondary\r
1581 status).\r
1582 @param[in] HeaderType Header type of this PCI device.\r
1583\r
1584 @retval EFI_SUCCESS The command completed successfully.\r
1585**/\r
1586EFI_STATUS\r
1587PciExplainStatus (\r
1588 IN UINT16 *Status,\r
1589 IN BOOLEAN MainStatus,\r
1590 IN PCI_HEADER_TYPE HeaderType\r
1591 );\r
1592\r
1593/**\r
1594 Explain each meaningful bit of register Command.\r
1595\r
1596 @param[in] Command Points to the content of register Command.\r
1597\r
1598 @retval EFI_SUCCESS The command completed successfully.\r
1599**/\r
1600EFI_STATUS\r
1601PciExplainCommand (\r
1602 IN UINT16 *Command\r
1603 );\r
1604\r
1605/**\r
1606 Explain each meaningful bit of register Bridge Control.\r
1607\r
1608 @param[in] BridgeControl Points to the content of register Bridge Control.\r
1609 @param[in] HeaderType The headertype.\r
1610\r
1611 @retval EFI_SUCCESS The command completed successfully.\r
1612**/\r
1613EFI_STATUS\r
1614PciExplainBridgeControl (\r
1615 IN UINT16 *BridgeControl,\r
1616 IN PCI_HEADER_TYPE HeaderType\r
1617 );\r
1618\r
1619/**\r
1620 Print each capability structure.\r
1621\r
1622 @param[in] IoDev The pointer to the deivce.\r
1623 @param[in] Address The address to start at.\r
1624 @param[in] CapPtr The offset from the address.\r
1625 @param[in] EnhancedDump The print format for the dump data.\r
1626\r
1627 @retval EFI_SUCCESS The operation was successful.\r
1628**/\r
1629EFI_STATUS\r
1630PciExplainCapabilityStruct (\r
1631 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
1632 IN UINT64 Address,\r
1633 IN UINT8 CapPtr,\r
1634 IN CONST UINT16 EnhancedDump\r
1635 );\r
1636\r
1637/**\r
1638 Display Pcie device structure.\r
1639\r
1640 @param[in] IoDev The pointer to the root pci protocol.\r
1641 @param[in] Address The Address to start at.\r
1642 @param[in] CapabilityPtr The offset from the address to start.\r
1643 @param[in] EnhancedDump The print format for the dump data.\r
1644 \r
1645 @retval EFI_SUCCESS The command completed successfully.\r
1646 @retval @retval EFI_SUCCESS Pci express extend space IO is not suppoted. \r
1647**/\r
1648EFI_STATUS\r
1649PciExplainPciExpress (\r
1650 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
1651 IN UINT64 Address,\r
1652 IN UINT8 CapabilityPtr,\r
1653 IN CONST UINT16 EnhancedDump\r
1654 );\r
1655\r
1656/**\r
1657 Print out information of the capability information.\r
1658\r
1659 @param[in] PciExpressCap The pointer to the structure about the device.\r
1660\r
1661 @retval EFI_SUCCESS The operation was successful.\r
1662**/\r
1663EFI_STATUS\r
1664ExplainPcieCapReg (\r
1665 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1666 );\r
1667\r
1668/**\r
1669 Print out information of the device capability information.\r
1670\r
1671 @param[in] PciExpressCap The pointer to the structure about the device.\r
1672\r
1673 @retval EFI_SUCCESS The operation was successful.\r
1674**/\r
1675EFI_STATUS\r
1676ExplainPcieDeviceCap (\r
1677 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1678 );\r
1679\r
1680/**\r
1681 Print out information of the device control information.\r
1682\r
1683 @param[in] PciExpressCap The pointer to the structure about the device.\r
1684\r
1685 @retval EFI_SUCCESS The operation was successful.\r
1686**/\r
1687EFI_STATUS\r
1688ExplainPcieDeviceControl (\r
1689 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1690 );\r
1691\r
1692/**\r
1693 Print out information of the device status information.\r
1694\r
1695 @param[in] PciExpressCap The pointer to the structure about the device.\r
1696\r
1697 @retval EFI_SUCCESS The operation was successful.\r
1698**/\r
1699EFI_STATUS\r
1700ExplainPcieDeviceStatus (\r
1701 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1702 );\r
1703\r
1704/**\r
1705 Print out information of the device link information.\r
1706\r
1707 @param[in] PciExpressCap The pointer to the structure about the device.\r
1708\r
1709 @retval EFI_SUCCESS The operation was successful.\r
1710**/\r
1711EFI_STATUS\r
1712ExplainPcieLinkCap (\r
1713 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1714 );\r
1715\r
1716/**\r
1717 Print out information of the device link control information.\r
1718\r
1719 @param[in] PciExpressCap The pointer to the structure about the device.\r
1720\r
1721 @retval EFI_SUCCESS The operation was successful.\r
1722**/\r
1723EFI_STATUS\r
1724ExplainPcieLinkControl (\r
1725 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1726 );\r
1727\r
1728/**\r
1729 Print out information of the device link status information.\r
1730\r
1731 @param[in] PciExpressCap The pointer to the structure about the device.\r
1732\r
1733 @retval EFI_SUCCESS The operation was successful.\r
1734**/\r
1735EFI_STATUS\r
1736ExplainPcieLinkStatus (\r
1737 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1738 );\r
1739\r
1740/**\r
1741 Print out information of the device slot information.\r
1742\r
1743 @param[in] PciExpressCap The pointer to the structure about the device.\r
1744\r
1745 @retval EFI_SUCCESS The operation was successful.\r
1746**/\r
1747EFI_STATUS\r
1748ExplainPcieSlotCap (\r
1749 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1750 );\r
1751\r
1752/**\r
1753 Print out information of the device slot control information.\r
1754\r
1755 @param[in] PciExpressCap The pointer to the structure about the device.\r
1756\r
1757 @retval EFI_SUCCESS The operation was successful.\r
1758**/\r
1759EFI_STATUS\r
1760ExplainPcieSlotControl (\r
1761 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1762 );\r
1763\r
1764/**\r
1765 Print out information of the device slot status information.\r
1766\r
1767 @param[in] PciExpressCap The pointer to the structure about the device.\r
1768\r
1769 @retval EFI_SUCCESS The operation was successful.\r
1770**/\r
1771EFI_STATUS\r
1772ExplainPcieSlotStatus (\r
1773 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1774 );\r
1775\r
1776/**\r
1777 Print out information of the device root information.\r
1778\r
1779 @param[in] PciExpressCap The pointer to the structure about the device.\r
1780\r
1781 @retval EFI_SUCCESS The operation was successful.\r
1782**/\r
1783EFI_STATUS\r
1784ExplainPcieRootControl (\r
1785 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1786 );\r
1787\r
1788/**\r
1789 Print out information of the device root capability information.\r
1790\r
1791 @param[in] PciExpressCap The pointer to the structure about the device.\r
1792\r
1793 @retval EFI_SUCCESS The operation was successful.\r
1794**/\r
1795EFI_STATUS\r
1796ExplainPcieRootCap (\r
1797 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1798 );\r
1799\r
1800/**\r
1801 Print out information of the device root status information.\r
1802\r
1803 @param[in] PciExpressCap The pointer to the structure about the device.\r
1804\r
1805 @retval EFI_SUCCESS The operation was successful.\r
1806**/\r
1807EFI_STATUS\r
1808ExplainPcieRootStatus (\r
1809 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1810 );\r
1811\r
1812typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION) (IN PCIE_CAP_STURCTURE *PciExpressCap);\r
1813\r
1814typedef enum {\r
1815 FieldWidthUINT8,\r
1816 FieldWidthUINT16,\r
1817 FieldWidthUINT32\r
1818} PCIE_CAPREG_FIELD_WIDTH;\r
1819\r
1820typedef enum {\r
1821 PcieExplainTypeCommon,\r
1822 PcieExplainTypeDevice,\r
1823 PcieExplainTypeLink,\r
1824 PcieExplainTypeSlot,\r
1825 PcieExplainTypeRoot,\r
1826 PcieExplainTypeMax\r
1827} PCIE_EXPLAIN_TYPE;\r
1828\r
1829typedef struct\r
1830{\r
1831 UINT16 Token;\r
1832 UINTN Offset;\r
1833 PCIE_CAPREG_FIELD_WIDTH Width;\r
1834 PCIE_EXPLAIN_FUNCTION Func;\r
1835 PCIE_EXPLAIN_TYPE Type;\r
1836} PCIE_EXPLAIN_STRUCT;\r
1837\r
1838PCIE_EXPLAIN_STRUCT PcieExplainList[] = {\r
1839 {\r
1840 STRING_TOKEN (STR_PCIEX_CAPABILITY_CAPID),\r
1841 0x00,\r
1842 FieldWidthUINT8,\r
1843 NULL,\r
1844 PcieExplainTypeCommon\r
1845 },\r
1846 {\r
1847 STRING_TOKEN (STR_PCIEX_NEXTCAP_PTR),\r
1848 0x01,\r
1849 FieldWidthUINT8,\r
1850 NULL,\r
1851 PcieExplainTypeCommon\r
1852 },\r
1853 {\r
1854 STRING_TOKEN (STR_PCIEX_CAP_REGISTER),\r
1855 0x02,\r
1856 FieldWidthUINT16,\r
1857 ExplainPcieCapReg,\r
1858 PcieExplainTypeCommon\r
1859 },\r
1860 {\r
1861 STRING_TOKEN (STR_PCIEX_DEVICE_CAP),\r
1862 0x04,\r
1863 FieldWidthUINT32,\r
1864 ExplainPcieDeviceCap,\r
1865 PcieExplainTypeDevice\r
1866 },\r
1867 {\r
1868 STRING_TOKEN (STR_PCIEX_DEVICE_CONTROL),\r
1869 0x08,\r
1870 FieldWidthUINT16,\r
1871 ExplainPcieDeviceControl,\r
1872 PcieExplainTypeDevice\r
1873 },\r
1874 {\r
1875 STRING_TOKEN (STR_PCIEX_DEVICE_STATUS),\r
1876 0x0a,\r
1877 FieldWidthUINT16,\r
1878 ExplainPcieDeviceStatus,\r
1879 PcieExplainTypeDevice\r
1880 },\r
1881 {\r
1882 STRING_TOKEN (STR_PCIEX_LINK_CAPABILITIES),\r
1883 0x0c,\r
1884 FieldWidthUINT32,\r
1885 ExplainPcieLinkCap,\r
1886 PcieExplainTypeLink\r
1887 },\r
1888 {\r
1889 STRING_TOKEN (STR_PCIEX_LINK_CONTROL),\r
1890 0x10,\r
1891 FieldWidthUINT16,\r
1892 ExplainPcieLinkControl,\r
1893 PcieExplainTypeLink\r
1894 },\r
1895 {\r
1896 STRING_TOKEN (STR_PCIEX_LINK_STATUS),\r
1897 0x12,\r
1898 FieldWidthUINT16,\r
1899 ExplainPcieLinkStatus,\r
1900 PcieExplainTypeLink\r
1901 },\r
1902 {\r
1903 STRING_TOKEN (STR_PCIEX_SLOT_CAPABILITIES),\r
1904 0x14,\r
1905 FieldWidthUINT32,\r
1906 ExplainPcieSlotCap,\r
1907 PcieExplainTypeSlot\r
1908 },\r
1909 {\r
1910 STRING_TOKEN (STR_PCIEX_SLOT_CONTROL),\r
1911 0x18,\r
1912 FieldWidthUINT16,\r
1913 ExplainPcieSlotControl,\r
1914 PcieExplainTypeSlot\r
1915 },\r
1916 {\r
1917 STRING_TOKEN (STR_PCIEX_SLOT_STATUS),\r
1918 0x1a,\r
1919 FieldWidthUINT16,\r
1920 ExplainPcieSlotStatus,\r
1921 PcieExplainTypeSlot\r
1922 },\r
1923 {\r
1924 STRING_TOKEN (STR_PCIEX_ROOT_CONTROL),\r
1925 0x1c,\r
1926 FieldWidthUINT16,\r
1927 ExplainPcieRootControl,\r
1928 PcieExplainTypeRoot\r
1929 },\r
1930 {\r
1931 STRING_TOKEN (STR_PCIEX_RSVDP),\r
1932 0x1e,\r
1933 FieldWidthUINT16,\r
1934 ExplainPcieRootCap,\r
1935 PcieExplainTypeRoot\r
1936 },\r
1937 {\r
1938 STRING_TOKEN (STR_PCIEX_ROOT_STATUS),\r
1939 0x20,\r
1940 FieldWidthUINT32,\r
1941 ExplainPcieRootStatus,\r
1942 PcieExplainTypeRoot\r
1943 },\r
1944 {\r
1945 0,\r
1946 0,\r
1947 (PCIE_CAPREG_FIELD_WIDTH)0,\r
1948 NULL,\r
1949 PcieExplainTypeMax\r
1950 }\r
1951};\r
1952\r
1953//\r
1954// Global Variables\r
1955//\r
1956PCI_CONFIG_SPACE *mConfigSpace = NULL;\r
1957STATIC CONST SHELL_PARAM_ITEM ParamList[] = {\r
1958 {L"-s", TypeValue},\r
1959 {L"-i", TypeFlag},\r
1960 {NULL, TypeMax}\r
1961 };\r
1962\r
1963CHAR16 *DevicePortTypeTable[] = {\r
1964 L"PCI Express Endpoint",\r
1965 L"Legacy PCI Express Endpoint",\r
1966 L"Unknown Type",\r
1967 L"Unknonw Type",\r
1968 L"Root Port of PCI Express Root Complex",\r
1969 L"Upstream Port of PCI Express Switch",\r
1970 L"Downstream Port of PCI Express Switch",\r
1971 L"PCI Express to PCI/PCI-X Bridge",\r
1972 L"PCI/PCI-X to PCI Express Bridge",\r
1973 L"Root Complex Integrated Endpoint",\r
1974 L"Root Complex Event Collector"\r
1975};\r
1976\r
1977CHAR16 *L0sLatencyStrTable[] = {\r
1978 L"Less than 64ns",\r
1979 L"64ns to less than 128ns",\r
1980 L"128ns to less than 256ns",\r
1981 L"256ns to less than 512ns",\r
1982 L"512ns to less than 1us",\r
1983 L"1us to less than 2us",\r
1984 L"2us-4us",\r
1985 L"More than 4us"\r
1986};\r
1987\r
1988CHAR16 *L1LatencyStrTable[] = {\r
1989 L"Less than 1us",\r
1990 L"1us to less than 2us",\r
1991 L"2us to less than 4us",\r
1992 L"4us to less than 8us",\r
1993 L"8us to less than 16us",\r
1994 L"16us to less than 32us",\r
1995 L"32us-64us",\r
1996 L"More than 64us"\r
1997};\r
1998\r
1999CHAR16 *ASPMCtrlStrTable[] = {\r
2000 L"Disabled",\r
2001 L"L0s Entry Enabled",\r
2002 L"L1 Entry Enabled",\r
2003 L"L0s and L1 Entry Enabled"\r
2004};\r
2005\r
2006CHAR16 *SlotPwrLmtScaleTable[] = {\r
2007 L"1.0x",\r
2008 L"0.1x",\r
2009 L"0.01x",\r
2010 L"0.001x"\r
2011};\r
2012\r
2013CHAR16 *IndicatorTable[] = {\r
2014 L"Reserved",\r
2015 L"On",\r
2016 L"Blink",\r
2017 L"Off"\r
2018};\r
2019\r
2020\r
2021/**\r
2022 Function for 'pci' command.\r
2023\r
2024 @param[in] ImageHandle Handle to the Image (NULL if Internal).\r
2025 @param[in] SystemTable Pointer to the System Table (NULL if Internal).\r
2026**/\r
2027SHELL_STATUS\r
2028EFIAPI\r
2029ShellCommandRunPci (\r
2030 IN EFI_HANDLE ImageHandle,\r
2031 IN EFI_SYSTEM_TABLE *SystemTable\r
2032 )\r
2033{\r
2034 UINT16 Segment;\r
2035 UINT16 Bus;\r
2036 UINT16 Device;\r
2037 UINT16 Func;\r
2038 UINT64 Address;\r
2039 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev;\r
2040 EFI_STATUS Status;\r
2041 PCI_COMMON_HEADER PciHeader;\r
2042 PCI_CONFIG_SPACE ConfigSpace;\r
2043 UINTN ScreenCount;\r
2044 UINTN TempColumn;\r
2045 UINTN ScreenSize;\r
2046 BOOLEAN ExplainData;\r
2047 UINTN Index;\r
2048 UINTN SizeOfHeader;\r
2049 BOOLEAN PrintTitle;\r
2050 UINTN HandleBufSize;\r
2051 EFI_HANDLE *HandleBuf;\r
2052 UINTN HandleCount;\r
2053 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
2054 UINT16 MinBus;\r
2055 UINT16 MaxBus;\r
2056 BOOLEAN IsEnd;\r
2057 LIST_ENTRY *Package;\r
2058 CHAR16 *ProblemParam;\r
2059 SHELL_STATUS ShellStatus;\r
2060 CONST CHAR16 *Temp;\r
2061 UINT64 RetVal;\r
2062 UINT16 EnhancedDump;\r
2063\r
2064 ShellStatus = SHELL_SUCCESS;\r
2065 Status = EFI_SUCCESS;\r
2066 Address = 0;\r
2067 IoDev = NULL;\r
2068 HandleBuf = NULL;\r
2069 Package = NULL;\r
2070\r
2071 //\r
2072 // initialize the shell lib (we must be in non-auto-init...)\r
2073 //\r
2074 Status = ShellInitialize();\r
2075 ASSERT_EFI_ERROR(Status);\r
2076\r
2077 Status = CommandInit();\r
2078 ASSERT_EFI_ERROR(Status);\r
2079\r
2080 //\r
2081 // parse the command line\r
2082 //\r
2083 Status = ShellCommandLineParse (ParamList, &Package, &ProblemParam, TRUE);\r
2084 if (EFI_ERROR(Status)) {\r
2085 if (Status == EFI_VOLUME_CORRUPTED && ProblemParam != NULL) {\r
2086 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, ProblemParam);\r
2087 FreePool(ProblemParam);\r
2088 ShellStatus = SHELL_INVALID_PARAMETER;\r
2089 } else {\r
2090 ASSERT(FALSE);\r
2091 }\r
2092 } else {\r
2093\r
2094 if (ShellCommandLineGetCount(Package) == 2) {\r
2095 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle);\r
2096 ShellStatus = SHELL_INVALID_PARAMETER;\r
2097 goto Done;\r
2098 }\r
2099\r
2100 if (ShellCommandLineGetCount(Package) > 4) {\r
2101 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle);\r
2102 ShellStatus = SHELL_INVALID_PARAMETER;\r
2103 goto Done;\r
2104 }\r
2105 if (ShellCommandLineGetFlag(Package, L"-s") && ShellCommandLineGetValue(Package, L"-s") == NULL) {\r
2106 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"-s");\r
2107 ShellStatus = SHELL_INVALID_PARAMETER;\r
2108 goto Done;\r
2109 }\r
2110 //\r
2111 // Get all instances of PciRootBridgeIo. Allocate space for 1 EFI_HANDLE and\r
2112 // call LibLocateHandle(), if EFI_BUFFER_TOO_SMALL is returned, allocate enough\r
2113 // space for handles and call it again.\r
2114 //\r
2115 HandleBufSize = sizeof (EFI_HANDLE);\r
2116 HandleBuf = (EFI_HANDLE *) AllocateZeroPool (HandleBufSize);\r
2117 if (HandleBuf == NULL) {\r
2118 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);\r
2119 ShellStatus = SHELL_OUT_OF_RESOURCES;\r
2120 goto Done;\r
2121 }\r
2122\r
2123 Status = gBS->LocateHandle (\r
2124 ByProtocol,\r
2125 &gEfiPciRootBridgeIoProtocolGuid,\r
2126 NULL,\r
2127 &HandleBufSize,\r
2128 HandleBuf\r
2129 );\r
2130\r
2131 if (Status == EFI_BUFFER_TOO_SMALL) {\r
2132 HandleBuf = ReallocatePool (sizeof (EFI_HANDLE), HandleBufSize, HandleBuf);\r
2133 if (HandleBuf == NULL) {\r
2134 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);\r
2135 ShellStatus = SHELL_OUT_OF_RESOURCES;\r
2136 goto Done;\r
2137 }\r
2138\r
2139 Status = gBS->LocateHandle (\r
2140 ByProtocol,\r
2141 &gEfiPciRootBridgeIoProtocolGuid,\r
2142 NULL,\r
2143 &HandleBufSize,\r
2144 HandleBuf\r
2145 );\r
2146 }\r
2147\r
2148 if (EFI_ERROR (Status)) {\r
2149 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PCIRBIO_NF), gShellDebug1HiiHandle);\r
2150 ShellStatus = SHELL_NOT_FOUND;\r
2151 goto Done;\r
2152 }\r
2153\r
2154 HandleCount = HandleBufSize / sizeof (EFI_HANDLE);\r
2155 //\r
2156 // Argument Count == 1(no other argument): enumerate all pci functions\r
2157 //\r
2158 if (ShellCommandLineGetCount(Package) == 1) {\r
2159 gST->ConOut->QueryMode (\r
2160 gST->ConOut,\r
2161 gST->ConOut->Mode->Mode,\r
2162 &TempColumn,\r
2163 &ScreenSize\r
2164 );\r
2165\r
2166 ScreenCount = 0;\r
2167 ScreenSize -= 4;\r
2168 if ((ScreenSize & 1) == 1) {\r
2169 ScreenSize -= 1;\r
2170 }\r
2171\r
2172 PrintTitle = TRUE;\r
2173\r
2174 //\r
2175 // For each handle, which decides a segment and a bus number range,\r
2176 // enumerate all devices on it.\r
2177 //\r
2178 for (Index = 0; Index < HandleCount; Index++) {\r
2179 Status = PciGetProtocolAndResource (\r
2180 HandleBuf[Index],\r
2181 &IoDev,\r
2182 &Descriptors\r
2183 );\r
2184 if (EFI_ERROR (Status)) {\r
2185 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR), gShellDebug1HiiHandle, Status);\r
2186 ShellStatus = SHELL_NOT_FOUND;\r
2187 goto Done;\r
2188 }\r
2189 //\r
2190 // No document say it's impossible for a RootBridgeIo protocol handle\r
2191 // to have more than one address space descriptors, so find out every\r
2192 // bus range and for each of them do device enumeration.\r
2193 //\r
2194 while (TRUE) {\r
2195 Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r
2196\r
2197 if (EFI_ERROR (Status)) {\r
2198 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR), gShellDebug1HiiHandle, Status);\r
2199 ShellStatus = SHELL_NOT_FOUND;\r
2200 goto Done;\r
2201 }\r
2202\r
2203 if (IsEnd) {\r
2204 break;\r
2205 }\r
2206\r
2207 for (Bus = MinBus; Bus <= MaxBus; Bus++) {\r
2208 //\r
2209 // For each devices, enumerate all functions it contains\r
2210 //\r
2211 for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
2212 //\r
2213 // For each function, read its configuration space and print summary\r
2214 //\r
2215 for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {\r
2216 if (ShellGetExecutionBreakFlag ()) {\r
2217 ShellStatus = SHELL_ABORTED;\r
2218 goto Done;\r
2219 }\r
2220 Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r
2221 IoDev->Pci.Read (\r
2222 IoDev,\r
2223 EfiPciWidthUint16,\r
2224 Address,\r
2225 1,\r
2226 &PciHeader.VendorId\r
2227 );\r
2228\r
2229 //\r
2230 // If VendorId = 0xffff, there does not exist a device at this\r
2231 // location. For each device, if there is any function on it,\r
2232 // there must be 1 function at Function 0. So if Func = 0, there\r
2233 // will be no more functions in the same device, so we can break\r
2234 // loop to deal with the next device.\r
2235 //\r
2236 if (PciHeader.VendorId == 0xffff && Func == 0) {\r
2237 break;\r
2238 }\r
2239\r
2240 if (PciHeader.VendorId != 0xffff) {\r
2241\r
2242 if (PrintTitle) {\r
2243 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_TITLE), gShellDebug1HiiHandle);\r
2244 PrintTitle = FALSE;\r
2245 }\r
2246\r
2247 IoDev->Pci.Read (\r
2248 IoDev,\r
2249 EfiPciWidthUint32,\r
2250 Address,\r
2251 sizeof (PciHeader) / sizeof (UINT32),\r
2252 &PciHeader\r
2253 );\r
2254\r
2255 ShellPrintHiiEx(\r
2256 -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P1), gShellDebug1HiiHandle,\r
2257 IoDev->SegmentNumber,\r
2258 Bus,\r
2259 Device,\r
2260 Func\r
2261 );\r
2262\r
2263 PciPrintClassCode (PciHeader.ClassCode, FALSE);\r
2264 ShellPrintHiiEx(\r
2265 -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P2), gShellDebug1HiiHandle,\r
2266 PciHeader.VendorId,\r
2267 PciHeader.DeviceId,\r
2268 PciHeader.ClassCode[0]\r
2269 );\r
2270\r
2271 ScreenCount += 2;\r
2272 if (ScreenCount >= ScreenSize && ScreenSize != 0) {\r
2273 //\r
2274 // If ScreenSize == 0 we have the console redirected so don't\r
2275 // block updates\r
2276 //\r
2277 ScreenCount = 0;\r
2278 }\r
2279 //\r
2280 // If this is not a multi-function device, we can leave the loop\r
2281 // to deal with the next device.\r
2282 //\r
2283 if (Func == 0 && ((PciHeader.HeaderType & HEADER_TYPE_MULTI_FUNCTION) == 0x00)) {\r
2284 break;\r
2285 }\r
2286 }\r
2287 }\r
2288 }\r
2289 }\r
2290 //\r
2291 // If Descriptor is NULL, Configuration() returns EFI_UNSUPPRORED,\r
2292 // we assume the bus range is 0~PCI_MAX_BUS. After enumerated all\r
2293 // devices on all bus, we can leave loop.\r
2294 //\r
2295 if (Descriptors == NULL) {\r
2296 break;\r
2297 }\r
2298 }\r
2299 }\r
2300\r
2301 Status = EFI_SUCCESS;\r
2302 goto Done;\r
2303 }\r
2304\r
2305 ExplainData = FALSE;\r
2306 Segment = 0;\r
2307 Bus = 0;\r
2308 Device = 0;\r
2309 Func = 0;\r
2310 if (ShellCommandLineGetFlag(Package, L"-i")) {\r
2311 ExplainData = TRUE;\r
2312 }\r
2313\r
2314 Temp = ShellCommandLineGetValue(Package, L"-s");\r
2315 if (Temp != NULL) {\r
2316 //\r
2317 // Input converted to hexadecimal number.\r
2318 //\r
2319 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
2320 Segment = (UINT16) RetVal;\r
2321 } else {\r
2322 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r
2323 ShellStatus = SHELL_INVALID_PARAMETER;\r
2324 goto Done;\r
2325 }\r
2326 }\r
2327\r
2328 //\r
2329 // The first Argument(except "-i") is assumed to be Bus number, second\r
2330 // to be Device number, and third to be Func number.\r
2331 //\r
2332 Temp = ShellCommandLineGetRawValue(Package, 1);\r
2333 if (Temp != NULL) {\r
2334 //\r
2335 // Input converted to hexadecimal number.\r
2336 //\r
2337 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
2338 Bus = (UINT16) RetVal;\r
2339 } else {\r
2340 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r
2341 ShellStatus = SHELL_INVALID_PARAMETER;\r
2342 goto Done;\r
2343 }\r
2344\r
2345 if (Bus > MAX_BUS_NUMBER) {\r
2346 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
2347 ShellStatus = SHELL_INVALID_PARAMETER;\r
2348 goto Done;\r
2349 }\r
2350 }\r
2351 Temp = ShellCommandLineGetRawValue(Package, 2);\r
2352 if (Temp != NULL) {\r
2353 //\r
2354 // Input converted to hexadecimal number.\r
2355 //\r
2356 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
2357 Device = (UINT16) RetVal;\r
2358 } else {\r
2359 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r
2360 ShellStatus = SHELL_INVALID_PARAMETER;\r
2361 goto Done;\r
2362 }\r
2363\r
2364 if (Device > MAX_DEVICE_NUMBER){\r
2365 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
2366 ShellStatus = SHELL_INVALID_PARAMETER;\r
2367 goto Done;\r
2368 }\r
2369 }\r
2370\r
2371 Temp = ShellCommandLineGetRawValue(Package, 3);\r
2372 if (Temp != NULL) {\r
2373 //\r
2374 // Input converted to hexadecimal number.\r
2375 //\r
2376 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
2377 Func = (UINT16) RetVal;\r
2378 } else {\r
2379 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r
2380 ShellStatus = SHELL_INVALID_PARAMETER;\r
2381 goto Done;\r
2382 }\r
2383\r
2384 if (Func > MAX_FUNCTION_NUMBER){\r
2385 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
2386 ShellStatus = SHELL_INVALID_PARAMETER;\r
2387 goto Done;\r
2388 }\r
2389 }\r
2390\r
2391 //\r
2392 // Find the protocol interface who's in charge of current segment, and its\r
2393 // bus range covers the current bus\r
2394 //\r
2395 Status = PciFindProtocolInterface (\r
2396 HandleBuf,\r
2397 HandleCount,\r
2398 Segment,\r
2399 Bus,\r
2400 &IoDev\r
2401 );\r
2402\r
2403 if (EFI_ERROR (Status)) {\r
2404 ShellPrintHiiEx(\r
2405 -1, -1, NULL, STRING_TOKEN (STR_PCI_NO_FIND), gShellDebug1HiiHandle,\r
2406 Segment,\r
2407 Bus\r
2408 );\r
2409 ShellStatus = SHELL_NOT_FOUND;\r
2410 goto Done;\r
2411 }\r
2412\r
2413 Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r
2414 Status = IoDev->Pci.Read (\r
2415 IoDev,\r
2416 EfiPciWidthUint8,\r
2417 Address,\r
2418 sizeof (ConfigSpace),\r
2419 &ConfigSpace\r
2420 );\r
2421\r
2422 if (EFI_ERROR (Status)) {\r
2423 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_NO_CFG), gShellDebug1HiiHandle, Status);\r
2424 ShellStatus = SHELL_ACCESS_DENIED;\r
2425 goto Done;\r
2426 }\r
2427\r
2428 mConfigSpace = &ConfigSpace;\r
2429 ShellPrintHiiEx(\r
2430 -1,\r
2431 -1,\r
2432 NULL,\r
2433 STRING_TOKEN (STR_PCI_INFO),\r
2434 gShellDebug1HiiHandle,\r
2435 Segment,\r
2436 Bus,\r
2437 Device,\r
2438 Func,\r
2439 Segment,\r
2440 Bus,\r
2441 Device,\r
2442 Func\r
2443 );\r
2444\r
2445 //\r
2446 // Dump standard header of configuration space\r
2447 //\r
2448 SizeOfHeader = sizeof (ConfigSpace.Common) + sizeof (ConfigSpace.NonCommon);\r
2449\r
2450 DumpHex (2, 0, SizeOfHeader, &ConfigSpace);\r
2451 ShellPrintEx(-1,-1, L"\r\n");\r
2452\r
2453 //\r
2454 // Dump device dependent Part of configuration space\r
2455 //\r
2456 DumpHex (\r
2457 2,\r
2458 SizeOfHeader,\r
2459 sizeof (ConfigSpace) - SizeOfHeader,\r
2460 ConfigSpace.Data\r
2461 );\r
2462\r
2463 //\r
2464 // If "-i" appears in command line, interpret data in configuration space\r
2465 //\r
2466 if (ExplainData) {\r
2467 EnhancedDump = 0;\r
2468 if (ShellCommandLineGetFlag(Package, L"-_e")) {\r
2469 EnhancedDump = 0xFFFF;\r
2470 Temp = ShellCommandLineGetValue(Package, L"-_e");\r
2471 if (Temp != NULL) {\r
2472 EnhancedDump = (UINT16) ShellHexStrToUintn (Temp);\r
2473 }\r
2474 }\r
2475 Status = PciExplainData (&ConfigSpace, Address, IoDev, EnhancedDump);\r
2476 }\r
2477 }\r
2478Done:\r
2479 if (HandleBuf != NULL) {\r
2480 FreePool (HandleBuf);\r
2481 }\r
2482 if (Package != NULL) {\r
2483 ShellCommandLineFreeVarList (Package);\r
2484 }\r
2485 mConfigSpace = NULL;\r
2486 return ShellStatus;\r
2487}\r
2488\r
2489/**\r
2490 This function finds out the protocol which is in charge of the given\r
2491 segment, and its bus range covers the current bus number. It lookes\r
2492 each instances of RootBridgeIoProtocol handle, until the one meets the\r
2493 criteria is found.\r
2494\r
2495 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
2496 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
2497 @param[in] Segment Segment number of device we are dealing with.\r
2498 @param[in] Bus Bus number of device we are dealing with.\r
2499 @param[out] IoDev Handle used to access configuration space of PCI device.\r
2500\r
2501 @retval EFI_SUCCESS The command completed successfully.\r
2502 @retval EFI_INVALID_PARAMETER Invalid parameter.\r
2503\r
2504**/\r
2505EFI_STATUS\r
2506PciFindProtocolInterface (\r
2507 IN EFI_HANDLE *HandleBuf,\r
2508 IN UINTN HandleCount,\r
2509 IN UINT16 Segment,\r
2510 IN UINT16 Bus,\r
2511 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r
2512 )\r
2513{\r
2514 UINTN Index;\r
2515 EFI_STATUS Status;\r
2516 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
2517 UINT16 MinBus;\r
2518 UINT16 MaxBus;\r
2519 BOOLEAN IsEnd;\r
2520\r
2521 //\r
2522 // Go through all handles, until the one meets the criteria is found\r
2523 //\r
2524 for (Index = 0; Index < HandleCount; Index++) {\r
2525 Status = PciGetProtocolAndResource (HandleBuf[Index], IoDev, &Descriptors);\r
2526 if (EFI_ERROR (Status)) {\r
2527 return Status;\r
2528 }\r
2529 //\r
2530 // When Descriptors == NULL, the Configuration() is not implemented,\r
2531 // so we only check the Segment number\r
2532 //\r
2533 if (Descriptors == NULL && Segment == (*IoDev)->SegmentNumber) {\r
2534 return EFI_SUCCESS;\r
2535 }\r
2536\r
2537 if ((*IoDev)->SegmentNumber != Segment) {\r
2538 continue;\r
2539 }\r
2540\r
2541 while (TRUE) {\r
2542 Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r
2543 if (EFI_ERROR (Status)) {\r
2544 return Status;\r
2545 }\r
2546\r
2547 if (IsEnd) {\r
2548 break;\r
2549 }\r
2550\r
2551 if (MinBus <= Bus && MaxBus >= Bus) {\r
2552 return EFI_SUCCESS;\r
2553 }\r
2554 }\r
2555 }\r
2556\r
2557 return EFI_NOT_FOUND;\r
2558}\r
2559\r
2560/**\r
2561 This function gets the protocol interface from the given handle, and\r
2562 obtains its address space descriptors.\r
2563\r
2564 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.\r
2565 @param[out] IoDev Handle used to access configuration space of PCI device.\r
2566 @param[out] Descriptors Points to the address space descriptors.\r
2567\r
2568 @retval EFI_SUCCESS The command completed successfully\r
2569**/\r
2570EFI_STATUS\r
2571PciGetProtocolAndResource (\r
2572 IN EFI_HANDLE Handle,\r
2573 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r
2574 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r
2575 )\r
2576{\r
2577 EFI_STATUS Status;\r
2578\r
2579 //\r
2580 // Get inferface from protocol\r
2581 //\r
2582 Status = gBS->HandleProtocol (\r
2583 Handle,\r
2584 &gEfiPciRootBridgeIoProtocolGuid,\r
2585 (VOID**)IoDev\r
2586 );\r
2587\r
2588 if (EFI_ERROR (Status)) {\r
2589 return Status;\r
2590 }\r
2591 //\r
2592 // Call Configuration() to get address space descriptors\r
2593 //\r
2594 Status = (*IoDev)->Configuration (*IoDev, (VOID**)Descriptors);\r
2595 if (Status == EFI_UNSUPPORTED) {\r
2596 *Descriptors = NULL;\r
2597 return EFI_SUCCESS;\r
2598\r
2599 } else {\r
2600 return Status;\r
2601 }\r
2602}\r
2603\r
2604/**\r
2605 This function get the next bus range of given address space descriptors.\r
2606 It also moves the pointer backward a node, to get prepared to be called\r
2607 again.\r
2608\r
2609 @param[in, out] Descriptors Points to current position of a serial of address space\r
2610 descriptors.\r
2611 @param[out] MinBus The lower range of bus number.\r
2612 @param[out] MaxBus The upper range of bus number.\r
2613 @param[out] IsEnd Meet end of the serial of descriptors.\r
2614\r
2615 @retval EFI_SUCCESS The command completed successfully.\r
2616**/\r
2617EFI_STATUS\r
2618PciGetNextBusRange (\r
2619 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,\r
2620 OUT UINT16 *MinBus,\r
2621 OUT UINT16 *MaxBus,\r
2622 OUT BOOLEAN *IsEnd\r
2623 )\r
2624{\r
2625 *IsEnd = FALSE;\r
2626\r
2627 //\r
2628 // When *Descriptors is NULL, Configuration() is not implemented, so assume\r
2629 // range is 0~PCI_MAX_BUS\r
2630 //\r
2631 if ((*Descriptors) == NULL) {\r
2632 *MinBus = 0;\r
2633 *MaxBus = PCI_MAX_BUS;\r
2634 return EFI_SUCCESS;\r
2635 }\r
2636 //\r
2637 // *Descriptors points to one or more address space descriptors, which\r
2638 // ends with a end tagged descriptor. Examine each of the descriptors,\r
2639 // if a bus typed one is found and its bus range covers bus, this handle\r
2640 // is the handle we are looking for.\r
2641 //\r
2642\r
2643 while ((*Descriptors)->Desc != ACPI_END_TAG_DESCRIPTOR) {\r
2644 if ((*Descriptors)->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {\r
2645 *MinBus = (UINT16) (*Descriptors)->AddrRangeMin;\r
2646 *MaxBus = (UINT16) (*Descriptors)->AddrRangeMax;\r
2647 (*Descriptors)++;\r
2648 return (EFI_SUCCESS);\r
2649 }\r
2650\r
2651 (*Descriptors)++;\r
2652 }\r
2653\r
2654 if ((*Descriptors)->Desc == ACPI_END_TAG_DESCRIPTOR) {\r
2655 *IsEnd = TRUE;\r
2656 }\r
2657\r
2658 return EFI_SUCCESS;\r
2659}\r
2660\r
2661/**\r
2662 Explain the data in PCI configuration space. The part which is common for\r
2663 PCI device and bridge is interpreted in this function. It calls other\r
2664 functions to interpret data unique for device or bridge.\r
2665\r
2666 @param[in] ConfigSpace Data in PCI configuration space.\r
2667 @param[in] Address Address used to access configuration space of this PCI device.\r
2668 @param[in] IoDev Handle used to access configuration space of PCI device.\r
2669 @param[in] EnhancedDump The print format for the dump data.\r
2670\r
2671 @retval EFI_SUCCESS The command completed successfully.\r
2672**/\r
2673EFI_STATUS\r
2674PciExplainData (\r
2675 IN PCI_CONFIG_SPACE *ConfigSpace,\r
2676 IN UINT64 Address,\r
2677 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
2678 IN CONST UINT16 EnhancedDump\r
2679 )\r
2680{\r
2681 PCI_COMMON_HEADER *Common;\r
2682 PCI_HEADER_TYPE HeaderType;\r
2683 EFI_STATUS Status;\r
2684 UINT8 CapPtr;\r
2685\r
2686 Common = &(ConfigSpace->Common);\r
2687\r
2688 ShellPrintEx (-1, -1, L"\r\n");\r
2689\r
2690 //\r
2691 // Print Vendor Id and Device Id\r
2692 //\r
2693 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_VID_DID), gShellDebug1HiiHandle,\r
2694 INDEX_OF (&(Common->VendorId)),\r
2695 Common->VendorId,\r
2696 INDEX_OF (&(Common->DeviceId)),\r
2697 Common->DeviceId\r
2698 );\r
2699\r
2700 //\r
2701 // Print register Command\r
2702 //\r
2703 PciExplainCommand (&(Common->Command));\r
2704\r
2705 //\r
2706 // Print register Status\r
2707 //\r
2708 PciExplainStatus (&(Common->Status), TRUE, PciUndefined);\r
2709\r
2710 //\r
2711 // Print register Revision ID\r
2712 //\r
2713 ShellPrintEx(-1, -1, L"\r\n");\r
2714 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_RID), gShellDebug1HiiHandle,\r
2715 INDEX_OF (&(Common->RevisionId)),\r
2716 Common->RevisionId\r
2717 );\r
2718\r
2719 //\r
2720 // Print register BIST\r
2721 //\r
2722 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_BIST), gShellDebug1HiiHandle, INDEX_OF (&(Common->Bist)));\r
2723 if ((Common->Bist & PCI_BIT_7) != 0) {\r
2724 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP), gShellDebug1HiiHandle, 0x0f & Common->Bist);\r
2725 } else {\r
2726 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP_NO), gShellDebug1HiiHandle);\r
2727 }\r
2728 //\r
2729 // Print register Cache Line Size\r
2730 //\r
2731 ShellPrintHiiEx(-1, -1, NULL,\r
2732 STRING_TOKEN (STR_PCI2_CACHE_LINE_SIZE),\r
2733 gShellDebug1HiiHandle,\r
2734 INDEX_OF (&(Common->CacheLineSize)),\r
2735 Common->CacheLineSize\r
2736 );\r
2737\r
2738 //\r
2739 // Print register Latency Timer\r
2740 //\r
2741 ShellPrintHiiEx(-1, -1, NULL,\r
2742 STRING_TOKEN (STR_PCI2_LATENCY_TIMER),\r
2743 gShellDebug1HiiHandle,\r
2744 INDEX_OF (&(Common->PrimaryLatencyTimer)),\r
2745 Common->PrimaryLatencyTimer\r
2746 );\r
2747\r
2748 //\r
2749 // Print register Header Type\r
2750 //\r
2751 ShellPrintHiiEx(-1, -1, NULL,\r
2752 STRING_TOKEN (STR_PCI2_HEADER_TYPE),\r
2753 gShellDebug1HiiHandle,\r
2754 INDEX_OF (&(Common->HeaderType)),\r
2755 Common->HeaderType\r
2756 );\r
2757\r
2758 if ((Common->HeaderType & PCI_BIT_7) != 0) {\r
2759 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MULTI_FUNCTION), gShellDebug1HiiHandle);\r
2760\r
2761 } else {\r
2762 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SINGLE_FUNCTION), gShellDebug1HiiHandle);\r
2763 }\r
2764\r
2765 HeaderType = (PCI_HEADER_TYPE)(UINT8) (Common->HeaderType & 0x7f);\r
2766 switch (HeaderType) {\r
2767 case PciDevice:\r
2768 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_PCI_DEVICE), gShellDebug1HiiHandle);\r
2769 break;\r
2770\r
2771 case PciP2pBridge:\r
2772 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_P2P_BRIDGE), gShellDebug1HiiHandle);\r
2773 break;\r
2774\r
2775 case PciCardBusBridge:\r
2776 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_BRIDGE), gShellDebug1HiiHandle);\r
2777 break;\r
2778\r
2779 default:\r
2780 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED), gShellDebug1HiiHandle);\r
2781 HeaderType = PciUndefined;\r
2782 }\r
2783\r
2784 //\r
2785 // Print register Class Code\r
2786 //\r
2787 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CLASS), gShellDebug1HiiHandle);\r
2788 PciPrintClassCode ((UINT8 *) Common->ClassCode, TRUE);\r
2789 ShellPrintEx (-1, -1, L"\r\n");\r
2790\r
2791 if (ShellGetExecutionBreakFlag()) {\r
2792 return EFI_SUCCESS;\r
2793 }\r
2794\r
2795 //\r
2796 // Interpret remaining part of PCI configuration header depending on\r
2797 // HeaderType\r
2798 //\r
2799 CapPtr = 0;\r
2800 Status = EFI_SUCCESS;\r
2801 switch (HeaderType) {\r
2802 case PciDevice:\r
2803 Status = PciExplainDeviceData (\r
2804 &(ConfigSpace->NonCommon.Device),\r
2805 Address,\r
2806 IoDev\r
2807 );\r
2808 CapPtr = ConfigSpace->NonCommon.Device.CapabilitiesPtr;\r
2809 break;\r
2810\r
2811 case PciP2pBridge:\r
2812 Status = PciExplainBridgeData (\r
2813 &(ConfigSpace->NonCommon.Bridge),\r
2814 Address,\r
2815 IoDev\r
2816 );\r
2817 CapPtr = ConfigSpace->NonCommon.Bridge.CapabilitiesPtr;\r
2818 break;\r
2819\r
2820 case PciCardBusBridge:\r
2821 Status = PciExplainCardBusData (\r
2822 &(ConfigSpace->NonCommon.CardBus),\r
2823 Address,\r
2824 IoDev\r
2825 );\r
2826 CapPtr = ConfigSpace->NonCommon.CardBus.CapabilitiesPtr;\r
2827 break;\r
2828 case PciUndefined:\r
2829 default:\r
2830 break;\r
2831 }\r
2832 //\r
2833 // If Status bit4 is 1, dump or explain capability structure\r
2834 //\r
2835 if ((Common->Status) & EFI_PCI_STATUS_CAPABILITY) {\r
2836 PciExplainCapabilityStruct (IoDev, Address, CapPtr, EnhancedDump);\r
2837 }\r
2838\r
2839 return Status;\r
2840}\r
2841\r
2842/**\r
2843 Explain the device specific part of data in PCI configuration space.\r
2844\r
2845 @param[in] Device Data in PCI configuration space.\r
2846 @param[in] Address Address used to access configuration space of this PCI device.\r
2847 @param[in] IoDev Handle used to access configuration space of PCI device.\r
2848\r
2849 @retval EFI_SUCCESS The command completed successfully.\r
2850**/\r
2851EFI_STATUS\r
2852PciExplainDeviceData (\r
2853 IN PCI_DEVICE_HEADER *Device,\r
2854 IN UINT64 Address,\r
2855 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
2856 )\r
2857{\r
2858 UINTN Index;\r
2859 BOOLEAN BarExist;\r
2860 EFI_STATUS Status;\r
2861 UINTN BarCount;\r
2862\r
2863 //\r
2864 // Print Base Address Registers(Bar). When Bar = 0, this Bar does not\r
2865 // exist. If these no Bar for this function, print "none", otherwise\r
2866 // list detail information about this Bar.\r
2867 //\r
2868 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDR), gShellDebug1HiiHandle, INDEX_OF (Device->Bar));\r
2869\r
2870 BarExist = FALSE;\r
2871 BarCount = sizeof (Device->Bar) / sizeof (Device->Bar[0]);\r
2872 for (Index = 0; Index < BarCount; Index++) {\r
2873 if (Device->Bar[Index] == 0) {\r
2874 continue;\r
2875 }\r
2876\r
2877 if (!BarExist) {\r
2878 BarExist = TRUE;\r
2879 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE), gShellDebug1HiiHandle);\r
2880 ShellPrintEx (-1, -1, L" --------------------------------------------------------------------------");\r
2881 }\r
2882\r
2883 Status = PciExplainBar (\r
2884 &(Device->Bar[Index]),\r
2885 &(mConfigSpace->Common.Command),\r
2886 Address,\r
2887 IoDev,\r
2888 &Index\r
2889 );\r
2890\r
2891 if (EFI_ERROR (Status)) {\r
2892 break;\r
2893 }\r
2894 }\r
2895\r
2896 if (!BarExist) {\r
2897 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r
2898\r
2899 } else {\r
2900 ShellPrintEx (-1, -1, L"\r\n --------------------------------------------------------------------------");\r
2901 }\r
2902\r
2903 //\r
2904 // Print register Expansion ROM Base Address\r
2905 //\r
2906 if ((Device->ROMBar & PCI_BIT_0) == 0) {\r
2907 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED), gShellDebug1HiiHandle, INDEX_OF (&(Device->ROMBar)));\r
2908\r
2909 } else {\r
2910 ShellPrintHiiEx(-1, -1, NULL,\r
2911 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE),\r
2912 gShellDebug1HiiHandle,\r
2913 INDEX_OF (&(Device->ROMBar)),\r
2914 Device->ROMBar\r
2915 );\r
2916 }\r
2917 //\r
2918 // Print register Cardbus CIS ptr\r
2919 //\r
2920 ShellPrintHiiEx(-1, -1, NULL,\r
2921 STRING_TOKEN (STR_PCI2_CARDBUS_CIS),\r
2922 gShellDebug1HiiHandle,\r
2923 INDEX_OF (&(Device->CardBusCISPtr)),\r
2924 Device->CardBusCISPtr\r
2925 );\r
2926\r
2927 //\r
2928 // Print register Sub-vendor ID and subsystem ID\r
2929 //\r
2930 ShellPrintHiiEx(-1, -1, NULL,\r
2931 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID),\r
2932 gShellDebug1HiiHandle,\r
2933 INDEX_OF (&(Device->SubVendorId)),\r
2934 Device->SubVendorId\r
2935 );\r
2936\r
2937 ShellPrintHiiEx(-1, -1, NULL,\r
2938 STRING_TOKEN (STR_PCI2_SUBSYSTEM_ID),\r
2939 gShellDebug1HiiHandle,\r
2940 INDEX_OF (&(Device->SubSystemId)),\r
2941 Device->SubSystemId\r
2942 );\r
2943\r
2944 //\r
2945 // Print register Capabilities Ptr\r
2946 //\r
2947 ShellPrintHiiEx(-1, -1, NULL,\r
2948 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR),\r
2949 gShellDebug1HiiHandle,\r
2950 INDEX_OF (&(Device->CapabilitiesPtr)),\r
2951 Device->CapabilitiesPtr\r
2952 );\r
2953\r
2954 //\r
2955 // Print register Interrupt Line and interrupt pin\r
2956 //\r
2957 ShellPrintHiiEx(-1, -1, NULL,\r
2958 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE),\r
2959 gShellDebug1HiiHandle,\r
2960 INDEX_OF (&(Device->InterruptLine)),\r
2961 Device->InterruptLine\r
2962 );\r
2963\r
2964 ShellPrintHiiEx(-1, -1, NULL,\r
2965 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),\r
2966 gShellDebug1HiiHandle,\r
2967 INDEX_OF (&(Device->InterruptPin)),\r
2968 Device->InterruptPin\r
2969 );\r
2970\r
2971 //\r
2972 // Print register Min_Gnt and Max_Lat\r
2973 //\r
2974 ShellPrintHiiEx(-1, -1, NULL,\r
2975 STRING_TOKEN (STR_PCI2_MIN_GNT),\r
2976 gShellDebug1HiiHandle,\r
2977 INDEX_OF (&(Device->MinGnt)),\r
2978 Device->MinGnt\r
2979 );\r
2980\r
2981 ShellPrintHiiEx(-1, -1, NULL,\r
2982 STRING_TOKEN (STR_PCI2_MAX_LAT),\r
2983 gShellDebug1HiiHandle,\r
2984 INDEX_OF (&(Device->MaxLat)),\r
2985 Device->MaxLat\r
2986 );\r
2987\r
2988 return EFI_SUCCESS;\r
2989}\r
2990\r
2991/**\r
2992 Explain the bridge specific part of data in PCI configuration space.\r
2993\r
2994 @param[in] Bridge Bridge specific data region in PCI configuration space.\r
2995 @param[in] Address Address used to access configuration space of this PCI device.\r
2996 @param[in] IoDev Handle used to access configuration space of PCI device.\r
2997\r
2998 @retval EFI_SUCCESS The command completed successfully.\r
2999**/\r
3000EFI_STATUS\r
3001PciExplainBridgeData (\r
3002 IN PCI_BRIDGE_HEADER *Bridge,\r
3003 IN UINT64 Address,\r
3004 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
3005 )\r
3006{\r
3007 UINTN Index;\r
3008 BOOLEAN BarExist;\r
3009 UINTN BarCount;\r
3010 UINT32 IoAddress32;\r
3011 EFI_STATUS Status;\r
3012\r
3013 //\r
3014 // Print Base Address Registers. When Bar = 0, this Bar does not\r
3015 // exist. If these no Bar for this function, print "none", otherwise\r
3016 // list detail information about this Bar.\r
3017 //\r
3018 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDRESS), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->Bar)));\r
3019\r
3020 BarExist = FALSE;\r
3021 BarCount = sizeof (Bridge->Bar) / sizeof (Bridge->Bar[0]);\r
3022\r
3023 for (Index = 0; Index < BarCount; Index++) {\r
3024 if (Bridge->Bar[Index] == 0) {\r
3025 continue;\r
3026 }\r
3027\r
3028 if (!BarExist) {\r
3029 BarExist = TRUE;\r
3030 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE_2), gShellDebug1HiiHandle);\r
3031 ShellPrintEx (-1, -1, L" --------------------------------------------------------------------------");\r
3032 }\r
3033\r
3034 Status = PciExplainBar (\r
3035 &(Bridge->Bar[Index]),\r
3036 &(mConfigSpace->Common.Command),\r
3037 Address,\r
3038 IoDev,\r
3039 &Index\r
3040 );\r
3041\r
3042 if (EFI_ERROR (Status)) {\r
3043 break;\r
3044 }\r
3045 }\r
3046\r
3047 if (!BarExist) {\r
3048 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r
3049 } else {\r
3050 ShellPrintEx (-1, -1, L"\r\n --------------------------------------------------------------------------");\r
3051 }\r
3052\r
3053 //\r
3054 // Expansion register ROM Base Address\r
3055 //\r
3056 if ((Bridge->ROMBar & PCI_BIT_0) == 0) {\r
3057 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->ROMBar)));\r
3058\r
3059 } else {\r
3060 ShellPrintHiiEx(-1, -1, NULL,\r
3061 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE_2),\r
3062 gShellDebug1HiiHandle,\r
3063 INDEX_OF (&(Bridge->ROMBar)),\r
3064 Bridge->ROMBar\r
3065 );\r
3066 }\r
3067 //\r
3068 // Print Bus Numbers(Primary, Secondary, and Subordinate\r
3069 //\r
3070 ShellPrintHiiEx(-1, -1, NULL,\r
3071 STRING_TOKEN (STR_PCI2_BUS_NUMBERS),\r
3072 gShellDebug1HiiHandle,\r
3073 INDEX_OF (&(Bridge->PrimaryBus)),\r
3074 INDEX_OF (&(Bridge->SecondaryBus)),\r
3075 INDEX_OF (&(Bridge->SubordinateBus))\r
3076 );\r
3077\r
3078 ShellPrintEx (-1, -1, L" ------------------------------------------------------\r\n");\r
3079\r
3080 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->PrimaryBus);\r
3081 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SecondaryBus);\r
3082 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SubordinateBus);\r
3083\r
3084 //\r
3085 // Print register Secondary Latency Timer\r
3086 //\r
3087 ShellPrintHiiEx(-1, -1, NULL,\r
3088 STRING_TOKEN (STR_PCI2_SECONDARY_TIMER),\r
3089 gShellDebug1HiiHandle,\r
3090 INDEX_OF (&(Bridge->SecondaryLatencyTimer)),\r
3091 Bridge->SecondaryLatencyTimer\r
3092 );\r
3093\r
3094 //\r
3095 // Print register Secondary Status\r
3096 //\r
3097 PciExplainStatus (&(Bridge->SecondaryStatus), FALSE, PciP2pBridge);\r
3098\r
3099 //\r
3100 // Print I/O and memory ranges this bridge forwards. There are 3 resource\r
3101 // types: I/O, memory, and pre-fetchable memory. For each resource type,\r
3102 // base and limit address are listed.\r
3103 //\r
3104 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE), gShellDebug1HiiHandle);\r
3105 ShellPrintEx (-1, -1, L"----------------------------------------------------------------------\r\n");\r
3106\r
3107 //\r
3108 // IO Base & Limit\r
3109 //\r
3110 IoAddress32 = (Bridge->IoBaseUpper << 16 | Bridge->IoBase << 8);\r
3111 IoAddress32 &= 0xfffff000;\r
3112 ShellPrintHiiEx(-1, -1, NULL,\r
3113 STRING_TOKEN (STR_PCI2_TWO_VARS),\r
3114 gShellDebug1HiiHandle,\r
3115 INDEX_OF (&(Bridge->IoBase)),\r
3116 IoAddress32\r
3117 );\r
3118\r
3119 IoAddress32 = (Bridge->IoLimitUpper << 16 | Bridge->IoLimit << 8);\r
3120 IoAddress32 |= 0x00000fff;\r
3121 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR), gShellDebug1HiiHandle, IoAddress32);\r
3122\r
3123 //\r
3124 // Memory Base & Limit\r
3125 //\r
3126 ShellPrintHiiEx(-1, -1, NULL,\r
3127 STRING_TOKEN (STR_PCI2_MEMORY),\r
3128 gShellDebug1HiiHandle,\r
3129 INDEX_OF (&(Bridge->MemoryBase)),\r
3130 (Bridge->MemoryBase << 16) & 0xfff00000\r
3131 );\r
3132\r
3133 ShellPrintHiiEx(-1, -1, NULL,\r
3134 STRING_TOKEN (STR_PCI2_ONE_VAR),\r
3135 gShellDebug1HiiHandle,\r
3136 (Bridge->MemoryLimit << 16) | 0x000fffff\r
3137 );\r
3138\r
3139 //\r
3140 // Pre-fetch-able Memory Base & Limit\r
3141 //\r
3142 ShellPrintHiiEx(-1, -1, NULL,\r
3143 STRING_TOKEN (STR_PCI2_PREFETCHABLE),\r
3144 gShellDebug1HiiHandle,\r
3145 INDEX_OF (&(Bridge->PrefetchableMemBase)),\r
3146 Bridge->PrefetchableBaseUpper,\r
3147 (Bridge->PrefetchableMemBase << 16) & 0xfff00000\r
3148 );\r
3149\r
3150 ShellPrintHiiEx(-1, -1, NULL,\r
3151 STRING_TOKEN (STR_PCI2_TWO_VARS_2),\r
3152 gShellDebug1HiiHandle,\r
3153 Bridge->PrefetchableLimitUpper,\r
3154 (Bridge->PrefetchableMemLimit << 16) | 0x000fffff\r
3155 );\r
3156\r
3157 //\r
3158 // Print register Capabilities Pointer\r
3159 //\r
3160 ShellPrintHiiEx(-1, -1, NULL,\r
3161 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR_2),\r
3162 gShellDebug1HiiHandle,\r
3163 INDEX_OF (&(Bridge->CapabilitiesPtr)),\r
3164 Bridge->CapabilitiesPtr\r
3165 );\r
3166\r
3167 //\r
3168 // Print register Bridge Control\r
3169 //\r
3170 PciExplainBridgeControl (&(Bridge->BridgeControl), PciP2pBridge);\r
3171\r
3172 //\r
3173 // Print register Interrupt Line & PIN\r
3174 //\r
3175 ShellPrintHiiEx(-1, -1, NULL,\r
3176 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_2),\r
3177 gShellDebug1HiiHandle,\r
3178 INDEX_OF (&(Bridge->InterruptLine)),\r
3179 Bridge->InterruptLine\r
3180 );\r
3181\r
3182 ShellPrintHiiEx(-1, -1, NULL,\r
3183 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),\r
3184 gShellDebug1HiiHandle,\r
3185 INDEX_OF (&(Bridge->InterruptPin)),\r
3186 Bridge->InterruptPin\r
3187 );\r
3188\r
3189 return EFI_SUCCESS;\r
3190}\r
3191\r
3192/**\r
3193 Explain the Base Address Register(Bar) in PCI configuration space.\r
3194\r
3195 @param[in] Bar Points to the Base Address Register intended to interpret.\r
3196 @param[in] Command Points to the register Command.\r
3197 @param[in] Address Address used to access configuration space of this PCI device.\r
3198 @param[in] IoDev Handle used to access configuration space of PCI device.\r
3199 @param[in, out] Index The Index.\r
3200\r
3201 @retval EFI_SUCCESS The command completed successfully.\r
3202**/\r
3203EFI_STATUS\r
3204PciExplainBar (\r
3205 IN UINT32 *Bar,\r
3206 IN UINT16 *Command,\r
3207 IN UINT64 Address,\r
3208 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
3209 IN OUT UINTN *Index\r
3210 )\r
3211{\r
3212 UINT16 OldCommand;\r
3213 UINT16 NewCommand;\r
3214 UINT64 Bar64;\r
3215 UINT32 OldBar32;\r
3216 UINT32 NewBar32;\r
3217 UINT64 OldBar64;\r
3218 UINT64 NewBar64;\r
3219 BOOLEAN IsMem;\r
3220 BOOLEAN IsBar32;\r
3221 UINT64 RegAddress;\r
3222\r
3223 IsBar32 = TRUE;\r
3224 Bar64 = 0;\r
3225 NewBar32 = 0;\r
3226 NewBar64 = 0;\r
3227\r
3228 //\r
3229 // According the bar type, list detail about this bar, for example: 32 or\r
3230 // 64 bits; pre-fetchable or not.\r
3231 //\r
3232 if ((*Bar & PCI_BIT_0) == 0) {\r
3233 //\r
3234 // This bar is of memory type\r
3235 //\r
3236 IsMem = TRUE;\r
3237\r
3238 if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) == 0) {\r
3239 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r
3240 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r
3241 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_32_BITS), gShellDebug1HiiHandle);\r
3242\r
3243 } else if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) != 0) {\r
3244 Bar64 = 0x0;\r
3245 CopyMem (&Bar64, Bar, sizeof (UINT64));\r
3246 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_2), gShellDebug1HiiHandle, (UINT32) RShiftU64 ((Bar64 & 0xfffffffffffffff0ULL), 32));\r
3247 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_3), gShellDebug1HiiHandle, (UINT32) (Bar64 & 0xfffffffffffffff0ULL));\r
3248 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r
3249 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_64_BITS), gShellDebug1HiiHandle);\r
3250 IsBar32 = FALSE;\r
3251 *Index += 1;\r
3252\r
3253 } else {\r
3254 //\r
3255 // Reserved\r
3256 //\r
3257 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r
3258 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM_2), gShellDebug1HiiHandle);\r
3259 }\r
3260\r
3261 if ((*Bar & PCI_BIT_3) == 0) {\r
3262 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO), gShellDebug1HiiHandle);\r
3263\r
3264 } else {\r
3265 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_YES), gShellDebug1HiiHandle);\r
3266 }\r
3267\r
3268 } else {\r
3269 //\r
3270 // This bar is of io type\r
3271 //\r
3272 IsMem = FALSE;\r
3273 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_4), gShellDebug1HiiHandle, *Bar & 0xfffffffc);\r
3274 ShellPrintEx (-1, -1, L"I/O ");\r
3275 }\r
3276\r
3277 //\r
3278 // Get BAR length(or the amount of resource this bar demands for). To get\r
3279 // Bar length, first we should temporarily disable I/O and memory access\r
3280 // of this function(by set bits in the register Command), then write all\r
3281 // "1"s to this bar. The bar value read back is the amount of resource\r
3282 // this bar demands for.\r
3283 //\r
3284 //\r
3285 // Disable io & mem access\r
3286 //\r
3287 OldCommand = *Command;\r
3288 NewCommand = (UINT16) (OldCommand & 0xfffc);\r
3289 RegAddress = Address | INDEX_OF (Command);\r
3290 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &NewCommand);\r
3291\r
3292 RegAddress = Address | INDEX_OF (Bar);\r
3293\r
3294 //\r
3295 // Read after write the BAR to get the size\r
3296 //\r
3297 if (IsBar32) {\r
3298 OldBar32 = *Bar;\r
3299 NewBar32 = 0xffffffff;\r
3300\r
3301 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);\r
3302 IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);\r
3303 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &OldBar32);\r
3304\r
3305 if (IsMem) {\r
3306 NewBar32 = NewBar32 & 0xfffffff0;\r
3307 NewBar32 = (~NewBar32) + 1;\r
3308\r
3309 } else {\r
3310 NewBar32 = NewBar32 & 0xfffffffc;\r
3311 NewBar32 = (~NewBar32) + 1;\r
3312 NewBar32 = NewBar32 & 0x0000ffff;\r
3313 }\r
3314 } else {\r
3315\r
3316 OldBar64 = 0x0;\r
3317 CopyMem (&OldBar64, Bar, sizeof (UINT64));\r
3318 NewBar64 = 0xffffffffffffffffULL;\r
3319\r
3320 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r
3321 IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r
3322 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &OldBar64);\r
3323\r
3324 if (IsMem) {\r
3325 NewBar64 = NewBar64 & 0xfffffffffffffff0ULL;\r
3326 NewBar64 = (~NewBar64) + 1;\r
3327\r
3328 } else {\r
3329 NewBar64 = NewBar64 & 0xfffffffffffffffcULL;\r
3330 NewBar64 = (~NewBar64) + 1;\r
3331 NewBar64 = NewBar64 & 0x000000000000ffff;\r
3332 }\r
3333 }\r
3334 //\r
3335 // Enable io & mem access\r
3336 //\r
3337 RegAddress = Address | INDEX_OF (Command);\r
3338 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &OldCommand);\r
3339\r
3340 if (IsMem) {\r
3341 if (IsBar32) {\r
3342 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32), gShellDebug1HiiHandle, NewBar32);\r
3343 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_2), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffff0) - 1);\r
3344\r
3345 } else {\r
3346 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) RShiftU64 (NewBar64, 32));\r
3347 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) NewBar64);\r
3348 ShellPrintEx (-1, -1, L" ");\r
3349 ShellPrintHiiEx(-1, -1, NULL,\r
3350 STRING_TOKEN (STR_PCI2_RSHIFT),\r
3351 gShellDebug1HiiHandle,\r
3352 (UINT32) RShiftU64 ((NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1), 32)\r
3353 );\r
3354 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) (NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1));\r
3355\r
3356 }\r
3357 } else {\r
3358 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_3), gShellDebug1HiiHandle, NewBar32);\r
3359 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_4), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffffc) - 1);\r
3360 }\r
3361\r
3362 return EFI_SUCCESS;\r
3363}\r
3364\r
3365/**\r
3366 Explain the cardbus specific part of data in PCI configuration space.\r
3367\r
3368 @param[in] CardBus CardBus specific region of PCI configuration space.\r
3369 @param[in] Address Address used to access configuration space of this PCI device.\r
3370 @param[in] IoDev Handle used to access configuration space of PCI device.\r
3371\r
3372 @retval EFI_SUCCESS The command completed successfully.\r
3373**/\r
3374EFI_STATUS\r
3375PciExplainCardBusData (\r
3376 IN PCI_CARDBUS_HEADER *CardBus,\r
3377 IN UINT64 Address,\r
3378 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
3379 )\r
3380{\r
3381 BOOLEAN Io32Bit;\r
3382 PCI_CARDBUS_DATA *CardBusData;\r
3383\r
3384 ShellPrintHiiEx(-1, -1, NULL,\r
3385 STRING_TOKEN (STR_PCI2_CARDBUS_SOCKET),\r
3386 gShellDebug1HiiHandle,\r
3387 INDEX_OF (&(CardBus->CardBusSocketReg)),\r
3388 CardBus->CardBusSocketReg\r
3389 );\r
3390\r
3391 //\r
3392 // Print Secondary Status\r
3393 //\r
3394 PciExplainStatus (&(CardBus->SecondaryStatus), FALSE, PciCardBusBridge);\r
3395\r
3396 //\r
3397 // Print Bus Numbers(Primary bus number, CardBus bus number, and\r
3398 // Subordinate bus number\r
3399 //\r
3400 ShellPrintHiiEx(-1, -1, NULL,\r
3401 STRING_TOKEN (STR_PCI2_BUS_NUMBERS_2),\r
3402 gShellDebug1HiiHandle,\r
3403 INDEX_OF (&(CardBus->PciBusNumber)),\r
3404 INDEX_OF (&(CardBus->CardBusBusNumber)),\r
3405 INDEX_OF (&(CardBus->SubordinateBusNumber))\r
3406 );\r
3407\r
3408 ShellPrintEx (-1, -1, L" ------------------------------------------------------\r\n");\r
3409\r
3410 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS), gShellDebug1HiiHandle, CardBus->PciBusNumber);\r
3411 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_2), gShellDebug1HiiHandle, CardBus->CardBusBusNumber);\r
3412 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_3), gShellDebug1HiiHandle, CardBus->SubordinateBusNumber);\r
3413\r
3414 //\r
3415 // Print CardBus Latency Timer\r
3416 //\r
3417 ShellPrintHiiEx(-1, -1, NULL,\r
3418 STRING_TOKEN (STR_PCI2_CARDBUS_LATENCY),\r
3419 gShellDebug1HiiHandle,\r
3420 INDEX_OF (&(CardBus->CardBusLatencyTimer)),\r
3421 CardBus->CardBusLatencyTimer\r
3422 );\r
3423\r
3424 //\r
3425 // Print Memory/Io ranges this cardbus bridge forwards\r
3426 //\r
3427 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2), gShellDebug1HiiHandle);\r
3428 ShellPrintEx (-1, -1, L"----------------------------------------------------------------------\r\n");\r
3429\r
3430 ShellPrintHiiEx(-1, -1, NULL,\r
3431 STRING_TOKEN (STR_PCI2_MEM_3),\r
3432 gShellDebug1HiiHandle,\r
3433 INDEX_OF (&(CardBus->MemoryBase0)),\r
3434 CardBus->BridgeControl & PCI_BIT_8 ? L" Prefetchable" : L"Non-Prefetchable",\r
3435 CardBus->MemoryBase0 & 0xfffff000,\r
3436 CardBus->MemoryLimit0 | 0x00000fff\r
3437 );\r
3438\r
3439 ShellPrintHiiEx(-1, -1, NULL,\r
3440 STRING_TOKEN (STR_PCI2_MEM_3),\r
3441 gShellDebug1HiiHandle,\r
3442 INDEX_OF (&(CardBus->MemoryBase1)),\r
3443 CardBus->BridgeControl & PCI_BIT_9 ? L" Prefetchable" : L"Non-Prefetchable",\r
3444 CardBus->MemoryBase1 & 0xfffff000,\r
3445 CardBus->MemoryLimit1 | 0x00000fff\r
3446 );\r
3447\r
3448 Io32Bit = (BOOLEAN) (CardBus->IoBase0 & PCI_BIT_0);\r
3449 ShellPrintHiiEx(-1, -1, NULL,\r
3450 STRING_TOKEN (STR_PCI2_IO_2),\r
3451 gShellDebug1HiiHandle,\r
3452 INDEX_OF (&(CardBus->IoBase0)),\r
3453 Io32Bit ? L" 32 bit" : L" 16 bit",\r
3454 CardBus->IoBase0 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r
3455 (CardBus->IoLimit0 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r
3456 );\r
3457\r
3458 Io32Bit = (BOOLEAN) (CardBus->IoBase1 & PCI_BIT_0);\r
3459 ShellPrintHiiEx(-1, -1, NULL,\r
3460 STRING_TOKEN (STR_PCI2_IO_2),\r
3461 gShellDebug1HiiHandle,\r
3462 INDEX_OF (&(CardBus->IoBase1)),\r
3463 Io32Bit ? L" 32 bit" : L" 16 bit",\r
3464 CardBus->IoBase1 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r
3465 (CardBus->IoLimit1 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r
3466 );\r
3467\r
3468 //\r
3469 // Print register Interrupt Line & PIN\r
3470 //\r
3471 ShellPrintHiiEx(-1, -1, NULL,\r
3472 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_3),\r
3473 gShellDebug1HiiHandle,\r
3474 INDEX_OF (&(CardBus->InterruptLine)),\r
3475 CardBus->InterruptLine,\r
3476 INDEX_OF (&(CardBus->InterruptPin)),\r
3477 CardBus->InterruptPin\r
3478 );\r
3479\r
3480 //\r
3481 // Print register Bridge Control\r
3482 //\r
3483 PciExplainBridgeControl (&(CardBus->BridgeControl), PciCardBusBridge);\r
3484\r
3485 //\r
3486 // Print some registers in data region of PCI configuration space for cardbus\r
3487 // bridge. Fields include: Sub VendorId, Subsystem ID, and Legacy Mode Base\r
3488 // Address.\r
3489 //\r
3490 CardBusData = (PCI_CARDBUS_DATA *) ((UINT8 *) CardBus + sizeof (PCI_CARDBUS_HEADER));\r
3491\r
3492 ShellPrintHiiEx(-1, -1, NULL,\r
3493 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID_2),\r
3494 gShellDebug1HiiHandle,\r
3495 INDEX_OF (&(CardBusData->SubVendorId)),\r
3496 CardBusData->SubVendorId,\r
3497 INDEX_OF (&(CardBusData->SubSystemId)),\r
3498 CardBusData->SubSystemId\r
3499 );\r
3500\r
3501 ShellPrintHiiEx(-1, -1, NULL,\r
3502 STRING_TOKEN (STR_PCI2_OPTIONAL),\r
3503 gShellDebug1HiiHandle,\r
3504 INDEX_OF (&(CardBusData->LegacyBase)),\r
3505 CardBusData->LegacyBase\r
3506 );\r
3507\r
3508 return EFI_SUCCESS;\r
3509}\r
3510\r
3511/**\r
3512 Explain each meaningful bit of register Status. The definition of Status is\r
3513 slightly different depending on the PCI header type.\r
3514\r
3515 @param[in] Status Points to the content of register Status.\r
3516 @param[in] MainStatus Indicates if this register is main status(not secondary\r
3517 status).\r
3518 @param[in] HeaderType Header type of this PCI device.\r
3519\r
3520 @retval EFI_SUCCESS The command completed successfully.\r
3521**/\r
3522EFI_STATUS\r
3523PciExplainStatus (\r
3524 IN UINT16 *Status,\r
3525 IN BOOLEAN MainStatus,\r
3526 IN PCI_HEADER_TYPE HeaderType\r
3527 )\r
3528{\r
3529 if (MainStatus) {\r
3530 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r
3531\r
3532 } else {\r
3533 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SECONDARY_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r
3534 }\r
3535\r
3536 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES), gShellDebug1HiiHandle, (*Status & PCI_BIT_4) != 0);\r
3537\r
3538 //\r
3539 // Bit 5 is meaningless for CardBus Bridge\r
3540 //\r
3541 if (HeaderType == PciCardBusBridge) {\r
3542 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);\r
3543\r
3544 } else {\r
3545 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE_2), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);\r
3546 }\r
3547\r
3548 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST_BACK), gShellDebug1HiiHandle, (*Status & PCI_BIT_7) != 0);\r
3549\r
3550 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MASTER_DATA), gShellDebug1HiiHandle, (*Status & PCI_BIT_8) != 0);\r
3551 //\r
3552 // Bit 9 and bit 10 together decides the DEVSEL timing\r
3553 //\r
3554 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_DEVSEL_TIMING), gShellDebug1HiiHandle);\r
3555 if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) == 0) {\r
3556 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST), gShellDebug1HiiHandle);\r
3557\r
3558 } else if ((*Status & PCI_BIT_9) != 0 && (*Status & PCI_BIT_10) == 0) {\r
3559 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEDIUM), gShellDebug1HiiHandle);\r
3560\r
3561 } else if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) != 0) {\r
3562 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SLOW), gShellDebug1HiiHandle);\r
3563\r
3564 } else {\r
3565 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED_2), gShellDebug1HiiHandle);\r
3566 }\r
3567\r
3568 ShellPrintHiiEx(-1, -1, NULL,\r
3569 STRING_TOKEN (STR_PCI2_SIGNALED_TARGET),\r
3570 gShellDebug1HiiHandle,\r
3571 (*Status & PCI_BIT_11) != 0\r
3572 );\r
3573\r
3574 ShellPrintHiiEx(-1, -1, NULL,\r
3575 STRING_TOKEN (STR_PCI2_RECEIVED_TARGET),\r
3576 gShellDebug1HiiHandle,\r
3577 (*Status & PCI_BIT_12) != 0\r
3578 );\r
3579\r
3580 ShellPrintHiiEx(-1, -1, NULL,\r
3581 STRING_TOKEN (STR_PCI2_RECEIVED_MASTER),\r
3582 gShellDebug1HiiHandle,\r
3583 (*Status & PCI_BIT_13) != 0\r
3584 );\r
3585\r
3586 if (MainStatus) {\r
3587 ShellPrintHiiEx(-1, -1, NULL,\r
3588 STRING_TOKEN (STR_PCI2_SIGNALED_ERROR),\r
3589 gShellDebug1HiiHandle,\r
3590 (*Status & PCI_BIT_14) != 0\r
3591 );\r
3592\r
3593 } else {\r
3594 ShellPrintHiiEx(-1, -1, NULL,\r
3595 STRING_TOKEN (STR_PCI2_RECEIVED_ERROR),\r
3596 gShellDebug1HiiHandle,\r
3597 (*Status & PCI_BIT_14) != 0\r
3598 );\r
3599 }\r
3600\r
3601 ShellPrintHiiEx(-1, -1, NULL,\r
3602 STRING_TOKEN (STR_PCI2_DETECTED_ERROR),\r
3603 gShellDebug1HiiHandle,\r
3604 (*Status & PCI_BIT_15) != 0\r
3605 );\r
3606\r
3607 return EFI_SUCCESS;\r
3608}\r
3609\r
3610/**\r
3611 Explain each meaningful bit of register Command.\r
3612\r
3613 @param[in] Command Points to the content of register Command.\r
3614\r
3615 @retval EFI_SUCCESS The command completed successfully.\r
3616**/\r
3617EFI_STATUS\r
3618PciExplainCommand (\r
3619 IN UINT16 *Command\r
3620 )\r
3621{\r
3622 //\r
3623 // Print the binary value of register Command\r
3624 //\r
3625 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_COMMAND), gShellDebug1HiiHandle, INDEX_OF (Command), *Command);\r
3626\r
3627 //\r
3628 // Explain register Command bit by bit\r
3629 //\r
3630 ShellPrintHiiEx(-1, -1, NULL,\r
3631 STRING_TOKEN (STR_PCI2_SPACE_ACCESS_DENIED),\r
3632 gShellDebug1HiiHandle,\r
3633 (*Command & PCI_BIT_0) != 0\r
3634 );\r
3635\r
3636 ShellPrintHiiEx(-1, -1, NULL,\r
3637 STRING_TOKEN (STR_PCI2_MEMORY_SPACE),\r
3638 gShellDebug1HiiHandle,\r
3639 (*Command & PCI_BIT_1) != 0\r
3640 );\r
3641\r
3642 ShellPrintHiiEx(-1, -1, NULL,\r
3643 STRING_TOKEN (STR_PCI2_BEHAVE_BUS_MASTER),\r
3644 gShellDebug1HiiHandle,\r
3645 (*Command & PCI_BIT_2) != 0\r
3646 );\r
3647\r
3648 ShellPrintHiiEx(-1, -1, NULL,\r
3649 STRING_TOKEN (STR_PCI2_MONITOR_SPECIAL_CYCLE),\r
3650 gShellDebug1HiiHandle,\r
3651 (*Command & PCI_BIT_3) != 0\r
3652 );\r
3653\r
3654 ShellPrintHiiEx(-1, -1, NULL,\r
3655 STRING_TOKEN (STR_PCI2_MEM_WRITE_INVALIDATE),\r
3656 gShellDebug1HiiHandle,\r
3657 (*Command & PCI_BIT_4) != 0\r
3658 );\r
3659\r
3660 ShellPrintHiiEx(-1, -1, NULL,\r
3661 STRING_TOKEN (STR_PCI2_PALETTE_SNOOPING),\r
3662 gShellDebug1HiiHandle,\r
3663 (*Command & PCI_BIT_5) != 0\r
3664 );\r
3665\r
3666 ShellPrintHiiEx(-1, -1, NULL,\r
3667 STRING_TOKEN (STR_PCI2_ASSERT_PERR),\r
3668 gShellDebug1HiiHandle,\r
3669 (*Command & PCI_BIT_6) != 0\r
3670 );\r
3671\r
3672 ShellPrintHiiEx(-1, -1, NULL,\r
3673 STRING_TOKEN (STR_PCI2_DO_ADDR_STEPPING),\r
3674 gShellDebug1HiiHandle,\r
3675 (*Command & PCI_BIT_7) != 0\r
3676 );\r
3677\r
3678 ShellPrintHiiEx(-1, -1, NULL,\r
3679 STRING_TOKEN (STR_PCI2_SERR_DRIVER),\r
3680 gShellDebug1HiiHandle,\r
3681 (*Command & PCI_BIT_8) != 0\r
3682 );\r
3683\r
3684 ShellPrintHiiEx(-1, -1, NULL,\r
3685 STRING_TOKEN (STR_PCI2_FAST_BACK_2),\r
3686 gShellDebug1HiiHandle,\r
3687 (*Command & PCI_BIT_9) != 0\r
3688 );\r
3689\r
3690 return EFI_SUCCESS;\r
3691}\r
3692\r
3693/**\r
3694 Explain each meaningful bit of register Bridge Control.\r
3695\r
3696 @param[in] BridgeControl Points to the content of register Bridge Control.\r
3697 @param[in] HeaderType The headertype.\r
3698\r
3699 @retval EFI_SUCCESS The command completed successfully.\r
3700**/\r
3701EFI_STATUS\r
3702PciExplainBridgeControl (\r
3703 IN UINT16 *BridgeControl,\r
3704 IN PCI_HEADER_TYPE HeaderType\r
3705 )\r
3706{\r
3707 ShellPrintHiiEx(-1, -1, NULL,\r
3708 STRING_TOKEN (STR_PCI2_BRIDGE_CONTROL),\r
3709 gShellDebug1HiiHandle,\r
3710 INDEX_OF (BridgeControl),\r
3711 *BridgeControl\r
3712 );\r
3713\r
3714 ShellPrintHiiEx(-1, -1, NULL,\r
3715 STRING_TOKEN (STR_PCI2_PARITY_ERROR),\r
3716 gShellDebug1HiiHandle,\r
3717 (*BridgeControl & PCI_BIT_0) != 0\r
3718 );\r
3719 ShellPrintHiiEx(-1, -1, NULL,\r
3720 STRING_TOKEN (STR_PCI2_SERR_ENABLE),\r
3721 gShellDebug1HiiHandle,\r
3722 (*BridgeControl & PCI_BIT_1) != 0\r
3723 );\r
3724 ShellPrintHiiEx(-1, -1, NULL,\r
3725 STRING_TOKEN (STR_PCI2_ISA_ENABLE),\r
3726 gShellDebug1HiiHandle,\r
3727 (*BridgeControl & PCI_BIT_2) != 0\r
3728 );\r
3729 ShellPrintHiiEx(-1, -1, NULL,\r
3730 STRING_TOKEN (STR_PCI2_VGA_ENABLE),\r
3731 gShellDebug1HiiHandle,\r
3732 (*BridgeControl & PCI_BIT_3) != 0\r
3733 );\r
3734 ShellPrintHiiEx(-1, -1, NULL,\r
3735 STRING_TOKEN (STR_PCI2_MASTER_ABORT),\r
3736 gShellDebug1HiiHandle,\r
3737 (*BridgeControl & PCI_BIT_5) != 0\r
3738 );\r
3739\r
3740 //\r
3741 // Register Bridge Control has some slight differences between P2P bridge\r
3742 // and Cardbus bridge from bit 6 to bit 11.\r
3743 //\r
3744 if (HeaderType == PciP2pBridge) {\r
3745 ShellPrintHiiEx(-1, -1, NULL,\r
3746 STRING_TOKEN (STR_PCI2_SECONDARY_BUS_RESET),\r
3747 gShellDebug1HiiHandle,\r
3748 (*BridgeControl & PCI_BIT_6) != 0\r
3749 );\r
3750 ShellPrintHiiEx(-1, -1, NULL,\r
3751 STRING_TOKEN (STR_PCI2_FAST_ENABLE),\r
3752 gShellDebug1HiiHandle,\r
3753 (*BridgeControl & PCI_BIT_7) != 0\r
3754 );\r
3755 ShellPrintHiiEx(-1, -1, NULL,\r
3756 STRING_TOKEN (STR_PCI2_PRIMARY_DISCARD_TIMER),\r
3757 gShellDebug1HiiHandle,\r
3758 (*BridgeControl & PCI_BIT_8)!=0 ? L"2^10" : L"2^15"\r
3759 );\r
3760 ShellPrintHiiEx(-1, -1, NULL,\r
3761 STRING_TOKEN (STR_PCI2_SECONDARY_DISCARD_TIMER),\r
3762 gShellDebug1HiiHandle,\r
3763 (*BridgeControl & PCI_BIT_9)!=0 ? L"2^10" : L"2^15"\r
3764 );\r
3765 ShellPrintHiiEx(-1, -1, NULL,\r
3766 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_STATUS),\r
3767 gShellDebug1HiiHandle,\r
3768 (*BridgeControl & PCI_BIT_10) != 0\r
3769 );\r
3770 ShellPrintHiiEx(-1, -1, NULL,\r
3771 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_SERR),\r
3772 gShellDebug1HiiHandle,\r
3773 (*BridgeControl & PCI_BIT_11) != 0\r
3774 );\r
3775\r
3776 } else {\r
3777 ShellPrintHiiEx(-1, -1, NULL,\r
3778 STRING_TOKEN (STR_PCI2_CARDBUS_RESET),\r
3779 gShellDebug1HiiHandle,\r
3780 (*BridgeControl & PCI_BIT_6) != 0\r
3781 );\r
3782 ShellPrintHiiEx(-1, -1, NULL,\r
3783 STRING_TOKEN (STR_PCI2_IREQ_ENABLE),\r
3784 gShellDebug1HiiHandle,\r
3785 (*BridgeControl & PCI_BIT_7) != 0\r
3786 );\r
3787 ShellPrintHiiEx(-1, -1, NULL,\r
3788 STRING_TOKEN (STR_PCI2_WRITE_POSTING_ENABLE),\r
3789 gShellDebug1HiiHandle,\r
3790 (*BridgeControl & PCI_BIT_10) != 0\r
3791 );\r
3792 }\r
3793\r
3794 return EFI_SUCCESS;\r
3795}\r
3796\r
3797/**\r
3798 Print each capability structure.\r
3799\r
3800 @param[in] IoDev The pointer to the deivce.\r
3801 @param[in] Address The address to start at.\r
3802 @param[in] CapPtr The offset from the address.\r
3803 @param[in] EnhancedDump The print format for the dump data.\r
3804\r
3805 @retval EFI_SUCCESS The operation was successful.\r
3806**/\r
3807EFI_STATUS\r
3808PciExplainCapabilityStruct (\r
3809 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
3810 IN UINT64 Address,\r
3811 IN UINT8 CapPtr,\r
3812 IN CONST UINT16 EnhancedDump\r
3813 )\r
3814{\r
3815 UINT8 CapabilityPtr;\r
3816 UINT16 CapabilityEntry;\r
3817 UINT8 CapabilityID;\r
3818 UINT64 RegAddress;\r
3819\r
3820 CapabilityPtr = CapPtr;\r
3821\r
3822 //\r
3823 // Go through the Capability list\r
3824 //\r
3825 while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {\r
3826 RegAddress = Address + CapabilityPtr;\r
3827 IoDev->Pci.Read (IoDev, EfiPciWidthUint16, RegAddress, 1, &CapabilityEntry);\r
3828\r
3829 CapabilityID = (UINT8) CapabilityEntry;\r
3830\r
3831 //\r
3832 // Explain PciExpress data\r
3833 //\r
3834 if (EFI_PCI_CAPABILITY_ID_PCIEXP == CapabilityID) {\r
3835 PciExplainPciExpress (IoDev, Address, CapabilityPtr, EnhancedDump);\r
3836 return EFI_SUCCESS;\r
3837 }\r
3838 //\r
3839 // Explain other capabilities here\r
3840 //\r
3841 CapabilityPtr = (UINT8) (CapabilityEntry >> 8);\r
3842 }\r
3843\r
3844 return EFI_SUCCESS;\r
3845}\r
3846\r
3847/**\r
3848 Print out information of the capability information.\r
3849\r
3850 @param[in] PciExpressCap The pointer to the structure about the device.\r
3851\r
3852 @retval EFI_SUCCESS The operation was successful.\r
3853**/\r
3854EFI_STATUS\r
3855ExplainPcieCapReg (\r
3856 IN PCIE_CAP_STURCTURE *PciExpressCap\r
3857 )\r
3858{\r
3859 UINT16 PcieCapReg;\r
3860 CHAR16 *DevicePortType;\r
3861\r
3862 PcieCapReg = PciExpressCap->PcieCapReg;\r
3863 ShellPrintEx (-1, -1,\r
3864 L" Capability Version(3:0): %E0x%04x%N\r\n",\r
3865 PCIE_CAP_VERSION (PcieCapReg)\r
3866 );\r
3867 if ((UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) < PCIE_DEVICE_PORT_TYPE_MAX) {\r
3868 DevicePortType = DevicePortTypeTable[PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg)];\r
3869 } else {\r
3870 DevicePortType = L"Unknown Type";\r
3871 }\r
3872 ShellPrintEx (-1, -1,\r
3873 L" Device/PortType(7:4): %E%s%N\r\n",\r
3874 DevicePortType\r
3875 );\r
3876 //\r
3877 // 'Slot Implemented' is only valid for:\r
3878 // a) Root Port of PCI Express Root Complex, or\r
3879 // b) Downstream Port of PCI Express Switch\r
3880 //\r
3881 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_ROOT_COMPLEX_ROOT_PORT ||\r
3882 PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_SWITCH_DOWNSTREAM_PORT) {\r
3883 ShellPrintEx (-1, -1,\r
3884 L" Slot Implemented(8): %E%d%N\r\n",\r
3885 PCIE_CAP_SLOT_IMPLEMENTED (PcieCapReg)\r
3886 );\r
3887 }\r
3888 ShellPrintEx (-1, -1,\r
3889 L" Interrupt Message Number(13:9): %E0x%05x%N\r\n",\r
3890 PCIE_CAP_INT_MSG_NUM (PcieCapReg)\r
3891 );\r
3892 return EFI_SUCCESS;\r
3893}\r
3894\r
3895/**\r
3896 Print out information of the device capability information.\r
3897\r
3898 @param[in] PciExpressCap The pointer to the structure about the device.\r
3899\r
3900 @retval EFI_SUCCESS The operation was successful.\r
3901**/\r
3902EFI_STATUS\r
3903ExplainPcieDeviceCap (\r
3904 IN PCIE_CAP_STURCTURE *PciExpressCap\r
3905 )\r
3906{\r
3907 UINT16 PcieCapReg;\r
3908 UINT32 PcieDeviceCap;\r
3909 UINT8 DevicePortType;\r
3910 UINT8 L0sLatency;\r
3911 UINT8 L1Latency;\r
3912\r
3913 PcieCapReg = PciExpressCap->PcieCapReg;\r
3914 PcieDeviceCap = PciExpressCap->PcieDeviceCap;\r
3915 DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg);\r
3916 ShellPrintEx (-1, -1, L" Max_Payload_Size Supported(2:0): ");\r
3917 if (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) < 6) {\r
3918 ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) + 7));\r
3919 } else {\r
3920 ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r
3921 }\r
3922 ShellPrintEx (-1, -1,\r
3923 L" Phantom Functions Supported(4:3): %E%d%N\r\n",\r
3924 PCIE_CAP_PHANTOM_FUNC (PcieDeviceCap)\r
3925 );\r
3926 ShellPrintEx (-1, -1,\r
3927 L" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\r\n",\r
3928 PCIE_CAP_EXTENDED_TAG (PcieDeviceCap) ? 8 : 5\r
3929 );\r
3930 //\r
3931 // Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint\r
3932 //\r
3933 if (IS_PCIE_ENDPOINT (DevicePortType)) {\r
3934 L0sLatency = (UINT8) PCIE_CAP_L0SLATENCY (PcieDeviceCap);\r
3935 L1Latency = (UINT8) PCIE_CAP_L1LATENCY (PcieDeviceCap);\r
3936 ShellPrintEx (-1, -1, L" Endpoint L0s Acceptable Latency(8:6): ");\r
3937 if (L0sLatency < 4) {\r
3938 ShellPrintEx (-1, -1, L"%EMaximum of %d ns%N\r\n", 1 << (L0sLatency + 6));\r
3939 } else {\r
3940 if (L0sLatency < 7) {\r
3941 ShellPrintEx (-1, -1, L"%EMaximum of %d us%N\r\n", 1 << (L0sLatency - 3));\r
3942 } else {\r
3943 ShellPrintEx (-1, -1, L"%ENo limit%N\r\n");\r
3944 }\r
3945 }\r
3946 ShellPrintEx (-1, -1, L" Endpoint L1 Acceptable Latency(11:9): ");\r
3947 if (L1Latency < 7) {\r
3948 ShellPrintEx (-1, -1, L"%EMaximum of %d us%N\r\n", 1 << (L1Latency + 1));\r
3949 } else {\r
3950 ShellPrintEx (-1, -1, L"%ENo limit%N\r\n");\r
3951 }\r
3952 }\r
3953 ShellPrintEx (-1, -1,\r
3954 L" Role-based Error Reporting(15): %E%d%N\r\n",\r
3955 PCIE_CAP_ERR_REPORTING (PcieDeviceCap)\r
3956 );\r
3957 //\r
3958 // Only valid for Upstream Port:\r
3959 // a) Captured Slot Power Limit Value\r
3960 // b) Captured Slot Power Scale\r
3961 //\r
3962 if (DevicePortType == PCIE_SWITCH_UPSTREAM_PORT) {\r
3963 ShellPrintEx (-1, -1,\r
3964 L" Captured Slot Power Limit Value(25:18): %E0x%02x%N\r\n",\r
3965 PCIE_CAP_SLOT_POWER_VALUE (PcieDeviceCap)\r
3966 );\r
3967 ShellPrintEx (-1, -1,\r
3968 L" Captured Slot Power Limit Scale(27:26): %E%s%N\r\n",\r
3969 SlotPwrLmtScaleTable[PCIE_CAP_SLOT_POWER_SCALE (PcieDeviceCap)]\r
3970 );\r
3971 }\r
3972 //\r
3973 // Function Level Reset Capability is only valid for Endpoint\r
3974 //\r
3975 if (IS_PCIE_ENDPOINT (DevicePortType)) {\r
3976 ShellPrintEx (-1, -1,\r
3977 L" Function Level Reset Capability(28): %E%d%N\r\n",\r
3978 PCIE_CAP_FUNC_LEVEL_RESET (PcieDeviceCap)\r
3979 );\r
3980 }\r
3981 return EFI_SUCCESS;\r
3982}\r
3983\r
3984/**\r
3985 Print out information of the device control information.\r
3986\r
3987 @param[in] PciExpressCap The pointer to the structure about the device.\r
3988\r
3989 @retval EFI_SUCCESS The operation was successful.\r
3990**/\r
3991EFI_STATUS\r
3992ExplainPcieDeviceControl (\r
3993 IN PCIE_CAP_STURCTURE *PciExpressCap\r
3994 )\r
3995{\r
3996 UINT16 PcieCapReg;\r
3997 UINT16 PcieDeviceControl;\r
3998\r
3999 PcieCapReg = PciExpressCap->PcieCapReg;\r
4000 PcieDeviceControl = PciExpressCap->DeviceControl;\r
4001 ShellPrintEx (-1, -1,\r
4002 L" Correctable Error Reporting Enable(0): %E%d%N\r\n",\r
4003 PCIE_CAP_COR_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
4004 );\r
4005 ShellPrintEx (-1, -1,\r
4006 L" Non-Fatal Error Reporting Enable(1): %E%d%N\r\n",\r
4007 PCIE_CAP_NONFAT_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
4008 );\r
4009 ShellPrintEx (-1, -1,\r
4010 L" Fatal Error Reporting Enable(2): %E%d%N\r\n",\r
4011 PCIE_CAP_FATAL_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
4012 );\r
4013 ShellPrintEx (-1, -1,\r
4014 L" Unsupported Request Reporting Enable(3): %E%d%N\r\n",\r
4015 PCIE_CAP_UNSUP_REQ_REPORTING_ENABLE (PcieDeviceControl)\r
4016 );\r
4017 ShellPrintEx (-1, -1,\r
4018 L" Enable Relaxed Ordering(4): %E%d%N\r\n",\r
4019 PCIE_CAP_RELAXED_ORDERING_ENABLE (PcieDeviceControl)\r
4020 );\r
4021 ShellPrintEx (-1, -1, L" Max_Payload_Size(7:5): ");\r
4022 if (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) < 6) {\r
4023 ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) + 7));\r
4024 } else {\r
4025 ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r
4026 }\r
4027 ShellPrintEx (-1, -1,\r
4028 L" Extended Tag Field Enable(8): %E%d%N\r\n",\r
4029 PCIE_CAP_EXTENDED_TAG_ENABLE (PcieDeviceControl)\r
4030 );\r
4031 ShellPrintEx (-1, -1,\r
4032 L" Phantom Functions Enable(9): %E%d%N\r\n",\r
4033 PCIE_CAP_PHANTOM_FUNC_ENABLE (PcieDeviceControl)\r
4034 );\r
4035 ShellPrintEx (-1, -1,\r
4036 L" Auxiliary (AUX) Power PM Enable(10): %E%d%N\r\n",\r
4037 PCIE_CAP_AUX_PM_ENABLE (PcieDeviceControl)\r
4038 );\r
4039 ShellPrintEx (-1, -1,\r
4040 L" Enable No Snoop(11): %E%d%N\r\n",\r
4041 PCIE_CAP_NO_SNOOP_ENABLE (PcieDeviceControl)\r
4042 );\r
4043 ShellPrintEx (-1, -1, L" Max_Read_Request_Size(14:12): ");\r
4044 if (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) < 6) {\r
4045 ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) + 7));\r
4046 } else {\r
4047 ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r
4048 }\r
4049 //\r
4050 // Read operation is only valid for PCI Express to PCI/PCI-X Bridges\r
4051 //\r
4052 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_PCIE_TO_PCIX_BRIDGE) {\r
4053 ShellPrintEx (-1, -1,\r
4054 L" Bridge Configuration Retry Enable(15): %E%d%N\r\n",\r
4055 PCIE_CAP_BRG_CONF_RETRY (PcieDeviceControl)\r
4056 );\r
4057 }\r
4058 return EFI_SUCCESS;\r
4059}\r
4060\r
4061/**\r
4062 Print out information of the device status information.\r
4063\r
4064 @param[in] PciExpressCap The pointer to the structure about the device.\r
4065\r
4066 @retval EFI_SUCCESS The operation was successful.\r
4067**/\r
4068EFI_STATUS\r
4069ExplainPcieDeviceStatus (\r
4070 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4071 )\r
4072{\r
4073 UINT16 PcieDeviceStatus;\r
4074\r
4075 PcieDeviceStatus = PciExpressCap->DeviceStatus;\r
4076 ShellPrintEx (-1, -1,\r
4077 L" Correctable Error Detected(0): %E%d%N\r\n",\r
4078 PCIE_CAP_COR_ERR_DETECTED (PcieDeviceStatus)\r
4079 );\r
4080 ShellPrintEx (-1, -1,\r
4081 L" Non-Fatal Error Detected(1): %E%d%N\r\n",\r
4082 PCIE_CAP_NONFAT_ERR_DETECTED (PcieDeviceStatus)\r
4083 );\r
4084 ShellPrintEx (-1, -1,\r
4085 L" Fatal Error Detected(2): %E%d%N\r\n",\r
4086 PCIE_CAP_FATAL_ERR_DETECTED (PcieDeviceStatus)\r
4087 );\r
4088 ShellPrintEx (-1, -1,\r
4089 L" Unsupported Request Detected(3): %E%d%N\r\n",\r
4090 PCIE_CAP_UNSUP_REQ_DETECTED (PcieDeviceStatus)\r
4091 );\r
4092 ShellPrintEx (-1, -1,\r
4093 L" AUX Power Detected(4): %E%d%N\r\n",\r
4094 PCIE_CAP_AUX_POWER_DETECTED (PcieDeviceStatus)\r
4095 );\r
4096 ShellPrintEx (-1, -1,\r
4097 L" Transactions Pending(5): %E%d%N\r\n",\r
4098 PCIE_CAP_TRANSACTION_PENDING (PcieDeviceStatus)\r
4099 );\r
4100 return EFI_SUCCESS;\r
4101}\r
4102\r
4103/**\r
4104 Print out information of the device link information.\r
4105\r
4106 @param[in] PciExpressCap The pointer to the structure about the device.\r
4107\r
4108 @retval EFI_SUCCESS The operation was successful.\r
4109**/\r
4110EFI_STATUS\r
4111ExplainPcieLinkCap (\r
4112 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4113 )\r
4114{\r
4115 UINT32 PcieLinkCap;\r
4116 CHAR16 *MaxLinkSpeed;\r
4117 CHAR16 *AspmValue;\r
4118\r
4119 PcieLinkCap = PciExpressCap->LinkCap;\r
4120 switch (PCIE_CAP_MAX_LINK_SPEED (PcieLinkCap)) {\r
4121 case 1:\r
4122 MaxLinkSpeed = L"2.5 GT/s";\r
4123 break;\r
4124 case 2:\r
4125 MaxLinkSpeed = L"5.0 GT/s";\r
4126 break;\r
4127 case 3:\r
4128 MaxLinkSpeed = L"8.0 GT/s";\r
4129 break;\r
4130 default:\r
4131 MaxLinkSpeed = L"Unknown";\r
4132 break;\r
4133 }\r
4134 ShellPrintEx (-1, -1,\r
4135 L" Maximum Link Speed(3:0): %E%s%N\r\n",\r
4136 MaxLinkSpeed\r
4137 );\r
4138 ShellPrintEx (-1, -1,\r
4139 L" Maximum Link Width(9:4): %Ex%d%N\r\n",\r
4140 PCIE_CAP_MAX_LINK_WIDTH (PcieLinkCap)\r
4141 );\r
4142 switch (PCIE_CAP_ASPM_SUPPORT (PcieLinkCap)) {\r
4143 case 0:\r
4144 AspmValue = L"Not";\r
4145 break;\r
4146 case 1:\r
4147 AspmValue = L"L0s";\r
4148 break;\r
4149 case 2:\r
4150 AspmValue = L"L1";\r
4151 break;\r
4152 case 3:\r
4153 AspmValue = L"L0s and L1";\r
4154 break;\r
4155 default:\r
4156 AspmValue = L"Reserved";\r
4157 break;\r
4158 }\r
4159 ShellPrintEx (-1, -1,\r
4160 L" Active State Power Management Support(11:10): %E%s Supported%N\r\n",\r
4161 AspmValue\r
4162 );\r
4163 ShellPrintEx (-1, -1,\r
4164 L" L0s Exit Latency(14:12): %E%s%N\r\n",\r
4165 L0sLatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]\r
4166 );\r
4167 ShellPrintEx (-1, -1,\r
4168 L" L1 Exit Latency(17:15): %E%s%N\r\n",\r
4169 L1LatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]\r
4170 );\r
4171 ShellPrintEx (-1, -1,\r
4172 L" Clock Power Management(18): %E%d%N\r\n",\r
4173 PCIE_CAP_CLOCK_PM (PcieLinkCap)\r
4174 );\r
4175 ShellPrintEx (-1, -1,\r
4176 L" Surprise Down Error Reporting Capable(19): %E%d%N\r\n",\r
4177 PCIE_CAP_SUP_DOWN_ERR_REPORTING (PcieLinkCap)\r
4178 );\r
4179 ShellPrintEx (-1, -1,\r
4180 L" Data Link Layer Link Active Reporting Capable(20): %E%d%N\r\n",\r
4181 PCIE_CAP_LINK_ACTIVE_REPORTING (PcieLinkCap)\r
4182 );\r
4183 ShellPrintEx (-1, -1,\r
4184 L" Link Bandwidth Notification Capability(21): %E%d%N\r\n",\r
4185 PCIE_CAP_LINK_BWD_NOTIF_CAP (PcieLinkCap)\r
4186 );\r
4187 ShellPrintEx (-1, -1,\r
4188 L" Port Number(31:24): %E0x%02x%N\r\n",\r
4189 PCIE_CAP_PORT_NUMBER (PcieLinkCap)\r
4190 );\r
4191 return EFI_SUCCESS;\r
4192}\r
4193\r
4194/**\r
4195 Print out information of the device link control information.\r
4196\r
4197 @param[in] PciExpressCap The pointer to the structure about the device.\r
4198\r
4199 @retval EFI_SUCCESS The operation was successful.\r
4200**/\r
4201EFI_STATUS\r
4202ExplainPcieLinkControl (\r
4203 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4204 )\r
4205{\r
4206 UINT16 PcieLinkControl;\r
4207 UINT8 DevicePortType;\r
4208\r
4209 PcieLinkControl = PciExpressCap->LinkControl;\r
4210 DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap->PcieCapReg);\r
4211 ShellPrintEx (-1, -1,\r
4212 L" Active State Power Management Control(1:0): %E%s%N\r\n",\r
4213 ASPMCtrlStrTable[PCIE_CAP_ASPM_CONTROL (PcieLinkControl)]\r
4214 );\r
4215 //\r
4216 // RCB is not applicable to switches\r
4217 //\r
4218 if (!IS_PCIE_SWITCH(DevicePortType)) {\r
4219 ShellPrintEx (-1, -1,\r
4220 L" Read Completion Boundary (RCB)(3): %E%d byte%N\r\n",\r
4221 1 << (PCIE_CAP_RCB (PcieLinkControl) + 6)\r
4222 );\r
4223 }\r
4224 //\r
4225 // Link Disable is reserved on\r
4226 // a) Endpoints\r
4227 // b) PCI Express to PCI/PCI-X bridges\r
4228 // c) Upstream Ports of Switches\r
4229 //\r
4230 if (!IS_PCIE_ENDPOINT (DevicePortType) &&\r
4231 DevicePortType != PCIE_SWITCH_UPSTREAM_PORT &&\r
4232 DevicePortType != PCIE_PCIE_TO_PCIX_BRIDGE) {\r
4233 ShellPrintEx (-1, -1,\r
4234 L" Link Disable(4): %E%d%N\r\n",\r
4235 PCIE_CAP_LINK_DISABLE (PcieLinkControl)\r
4236 );\r
4237 }\r
4238 ShellPrintEx (-1, -1,\r
4239 L" Common Clock Configuration(6): %E%d%N\r\n",\r
4240 PCIE_CAP_COMMON_CLK_CONF (PcieLinkControl)\r
4241 );\r
4242 ShellPrintEx (-1, -1,\r
4243 L" Extended Synch(7): %E%d%N\r\n",\r
4244 PCIE_CAP_EXT_SYNC (PcieLinkControl)\r
4245 );\r
4246 ShellPrintEx (-1, -1,\r
4247 L" Enable Clock Power Management(8): %E%d%N\r\n",\r
4248 PCIE_CAP_CLK_PWR_MNG (PcieLinkControl)\r
4249 );\r
4250 ShellPrintEx (-1, -1,\r
4251 L" Hardware Autonomous Width Disable(9): %E%d%N\r\n",\r
4252 PCIE_CAP_HW_AUTO_WIDTH_DISABLE (PcieLinkControl)\r
4253 );\r
4254 ShellPrintEx (-1, -1,\r
4255 L" Link Bandwidth Management Interrupt Enable(10): %E%d%N\r\n",\r
4256 PCIE_CAP_LINK_BDW_MNG_INT_EN (PcieLinkControl)\r
4257 );\r
4258 ShellPrintEx (-1, -1,\r
4259 L" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\r\n",\r
4260 PCIE_CAP_LINK_AUTO_BDW_INT_EN (PcieLinkControl)\r
4261 );\r
4262 return EFI_SUCCESS;\r
4263}\r
4264\r
4265/**\r
4266 Print out information of the device link status information.\r
4267\r
4268 @param[in] PciExpressCap The pointer to the structure about the device.\r
4269\r
4270 @retval EFI_SUCCESS The operation was successful.\r
4271**/\r
4272EFI_STATUS\r
4273ExplainPcieLinkStatus (\r
4274 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4275 )\r
4276{\r
4277 UINT16 PcieLinkStatus;\r
4278 CHAR16 *CurLinkSpeed;\r
4279\r
4280 PcieLinkStatus = PciExpressCap->LinkStatus;\r
4281 switch (PCIE_CAP_CUR_LINK_SPEED (PcieLinkStatus)) {\r
4282 case 1:\r
4283 CurLinkSpeed = L"2.5 GT/s";\r
4284 break;\r
4285 case 2:\r
4286 CurLinkSpeed = L"5.0 GT/s";\r
4287 break;\r
4288 case 3:\r
4289 CurLinkSpeed = L"8.0 GT/s";\r
4290 break;\r
4291 default:\r
4292 CurLinkSpeed = L"Reserved";\r
4293 break;\r
4294 }\r
4295 ShellPrintEx (-1, -1,\r
4296 L" Current Link Speed(3:0): %E%s%N\r\n",\r
4297 CurLinkSpeed\r
4298 );\r
4299 ShellPrintEx (-1, -1,\r
4300 L" Negotiated Link Width(9:4): %Ex%d%N\r\n",\r
4301 PCIE_CAP_NEGO_LINK_WIDTH (PcieLinkStatus)\r
4302 );\r
4303 ShellPrintEx (-1, -1,\r
4304 L" Link Training(11): %E%d%N\r\n",\r
4305 PCIE_CAP_LINK_TRAINING (PcieLinkStatus)\r
4306 );\r
4307 ShellPrintEx (-1, -1,\r
4308 L" Slot Clock Configuration(12): %E%d%N\r\n",\r
4309 PCIE_CAP_SLOT_CLK_CONF (PcieLinkStatus)\r
4310 );\r
4311 ShellPrintEx (-1, -1,\r
4312 L" Data Link Layer Link Active(13): %E%d%N\r\n",\r
4313 PCIE_CAP_DATA_LINK_ACTIVE (PcieLinkStatus)\r
4314 );\r
4315 ShellPrintEx (-1, -1,\r
4316 L" Link Bandwidth Management Status(14): %E%d%N\r\n",\r
4317 PCIE_CAP_LINK_BDW_MNG_STAT (PcieLinkStatus)\r
4318 );\r
4319 ShellPrintEx (-1, -1,\r
4320 L" Link Autonomous Bandwidth Status(15): %E%d%N\r\n",\r
4321 PCIE_CAP_LINK_AUTO_BDW_STAT (PcieLinkStatus)\r
4322 );\r
4323 return EFI_SUCCESS;\r
4324}\r
4325\r
4326/**\r
4327 Print out information of the device slot information.\r
4328\r
4329 @param[in] PciExpressCap The pointer to the structure about the device.\r
4330\r
4331 @retval EFI_SUCCESS The operation was successful.\r
4332**/\r
4333EFI_STATUS\r
4334ExplainPcieSlotCap (\r
4335 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4336 )\r
4337{\r
4338 UINT32 PcieSlotCap;\r
4339\r
4340 PcieSlotCap = PciExpressCap->SlotCap;\r
4341\r
4342 ShellPrintEx (-1, -1,\r
4343 L" Attention Button Present(0): %E%d%N\r\n",\r
4344 PCIE_CAP_ATT_BUT_PRESENT (PcieSlotCap)\r
4345 );\r
4346 ShellPrintEx (-1, -1,\r
4347 L" Power Controller Present(1): %E%d%N\r\n",\r
4348 PCIE_CAP_PWR_CTRLLER_PRESENT (PcieSlotCap)\r
4349 );\r
4350 ShellPrintEx (-1, -1,\r
4351 L" MRL Sensor Present(2): %E%d%N\r\n",\r
4352 PCIE_CAP_MRL_SENSOR_PRESENT (PcieSlotCap)\r
4353 );\r
4354 ShellPrintEx (-1, -1,\r
4355 L" Attention Indicator Present(3): %E%d%N\r\n",\r
4356 PCIE_CAP_ATT_IND_PRESENT (PcieSlotCap)\r
4357 );\r
4358 ShellPrintEx (-1, -1,\r
4359 L" Power Indicator Present(4): %E%d%N\r\n",\r
4360 PCIE_CAP_PWD_IND_PRESENT (PcieSlotCap)\r
4361 );\r
4362 ShellPrintEx (-1, -1,\r
4363 L" Hot-Plug Surprise(5): %E%d%N\r\n",\r
4364 PCIE_CAP_HOTPLUG_SUPPRISE (PcieSlotCap)\r
4365 );\r
4366 ShellPrintEx (-1, -1,\r
4367 L" Hot-Plug Capable(6): %E%d%N\r\n",\r
4368 PCIE_CAP_HOTPLUG_CAPABLE (PcieSlotCap)\r
4369 );\r
4370 ShellPrintEx (-1, -1,\r
4371 L" Slot Power Limit Value(14:7): %E0x%02x%N\r\n",\r
4372 PCIE_CAP_SLOT_PWR_LIMIT_VALUE (PcieSlotCap)\r
4373 );\r
4374 ShellPrintEx (-1, -1,\r
4375 L" Slot Power Limit Scale(16:15): %E%s%N\r\n",\r
4376 SlotPwrLmtScaleTable[PCIE_CAP_SLOT_PWR_LIMIT_SCALE (PcieSlotCap)]\r
4377 );\r
4378 ShellPrintEx (-1, -1,\r
4379 L" Electromechanical Interlock Present(17): %E%d%N\r\n",\r
4380 PCIE_CAP_ELEC_INTERLOCK_PRESENT (PcieSlotCap)\r
4381 );\r
4382 ShellPrintEx (-1, -1,\r
4383 L" No Command Completed Support(18): %E%d%N\r\n",\r
4384 PCIE_CAP_NO_COMM_COMPLETED_SUP (PcieSlotCap)\r
4385 );\r
4386 ShellPrintEx (-1, -1,\r
4387 L" Physical Slot Number(31:19): %E%d%N\r\n",\r
4388 PCIE_CAP_PHY_SLOT_NUM (PcieSlotCap)\r
4389 );\r
4390\r
4391 return EFI_SUCCESS;\r
4392}\r
4393\r
4394/**\r
4395 Print out information of the device slot control information.\r
4396\r
4397 @param[in] PciExpressCap The pointer to the structure about the device.\r
4398\r
4399 @retval EFI_SUCCESS The operation was successful.\r
4400**/\r
4401EFI_STATUS\r
4402ExplainPcieSlotControl (\r
4403 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4404 )\r
4405{\r
4406 UINT16 PcieSlotControl;\r
4407\r
4408 PcieSlotControl = PciExpressCap->SlotControl;\r
4409 ShellPrintEx (-1, -1,\r
4410 L" Attention Button Pressed Enable(0): %E%d%N\r\n",\r
4411 PCIE_CAP_ATT_BUT_ENABLE (PcieSlotControl)\r
4412 );\r
4413 ShellPrintEx (-1, -1,\r
4414 L" Power Fault Detected Enable(1): %E%d%N\r\n",\r
4415 PCIE_CAP_PWR_FLT_DETECT_ENABLE (PcieSlotControl)\r
4416 );\r
4417 ShellPrintEx (-1, -1,\r
4418 L" MRL Sensor Changed Enable(2): %E%d%N\r\n",\r
4419 PCIE_CAP_MRL_SENSOR_CHANGE_ENABLE (PcieSlotControl)\r
4420 );\r
4421 ShellPrintEx (-1, -1,\r
4422 L" Presence Detect Changed Enable(3): %E%d%N\r\n",\r
4423 PCIE_CAP_PRES_DETECT_CHANGE_ENABLE (PcieSlotControl)\r
4424 );\r
4425 ShellPrintEx (-1, -1,\r
4426 L" Command Completed Interrupt Enable(4): %E%d%N\r\n",\r
4427 PCIE_CAP_COMM_CMPL_INT_ENABLE (PcieSlotControl)\r
4428 );\r
4429 ShellPrintEx (-1, -1,\r
4430 L" Hot-Plug Interrupt Enable(5): %E%d%N\r\n",\r
4431 PCIE_CAP_HOTPLUG_INT_ENABLE (PcieSlotControl)\r
4432 );\r
4433 ShellPrintEx (-1, -1,\r
4434 L" Attention Indicator Control(7:6): %E%s%N\r\n",\r
4435 IndicatorTable[PCIE_CAP_ATT_IND_CTRL (PcieSlotControl)]\r
4436 );\r
4437 ShellPrintEx (-1, -1,\r
4438 L" Power Indicator Control(9:8): %E%s%N\r\n",\r
4439 IndicatorTable[PCIE_CAP_PWR_IND_CTRL (PcieSlotControl)]\r
4440 );\r
4441 ShellPrintEx (-1, -1, L" Power Controller Control(10): %EPower ");\r
4442 if (PCIE_CAP_PWR_CTRLLER_CTRL (PcieSlotControl)) {\r
4443 ShellPrintEx (-1, -1, L"Off%N\r\n");\r
4444 } else {\r
4445 ShellPrintEx (-1, -1, L"On%N\r\n");\r
4446 }\r
4447 ShellPrintEx (-1, -1,\r
4448 L" Electromechanical Interlock Control(11): %E%d%N\r\n",\r
4449 PCIE_CAP_ELEC_INTERLOCK_CTRL (PcieSlotControl)\r
4450 );\r
4451 ShellPrintEx (-1, -1,\r
4452 L" Data Link Layer State Changed Enable(12): %E%d%N\r\n",\r
4453 PCIE_CAP_DLINK_STAT_CHANGE_ENABLE (PcieSlotControl)\r
4454 );\r
4455 return EFI_SUCCESS;\r
4456}\r
4457\r
4458/**\r
4459 Print out information of the device slot status information.\r
4460\r
4461 @param[in] PciExpressCap The pointer to the structure about the device.\r
4462\r
4463 @retval EFI_SUCCESS The operation was successful.\r
4464**/\r
4465EFI_STATUS\r
4466ExplainPcieSlotStatus (\r
4467 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4468 )\r
4469{\r
4470 UINT16 PcieSlotStatus;\r
4471\r
4472 PcieSlotStatus = PciExpressCap->SlotStatus;\r
4473\r
4474 ShellPrintEx (-1, -1,\r
4475 L" Attention Button Pressed(0): %E%d%N\r\n",\r
4476 PCIE_CAP_ATT_BUT_PRESSED (PcieSlotStatus)\r
4477 );\r
4478 ShellPrintEx (-1, -1,\r
4479 L" Power Fault Detected(1): %E%d%N\r\n",\r
4480 PCIE_CAP_PWR_FLT_DETECTED (PcieSlotStatus)\r
4481 );\r
4482 ShellPrintEx (-1, -1,\r
4483 L" MRL Sensor Changed(2): %E%d%N\r\n",\r
4484 PCIE_CAP_MRL_SENSOR_CHANGED (PcieSlotStatus)\r
4485 );\r
4486 ShellPrintEx (-1, -1,\r
4487 L" Presence Detect Changed(3): %E%d%N\r\n",\r
4488 PCIE_CAP_PRES_DETECT_CHANGED (PcieSlotStatus)\r
4489 );\r
4490 ShellPrintEx (-1, -1,\r
4491 L" Command Completed(4): %E%d%N\r\n",\r
4492 PCIE_CAP_COMM_COMPLETED (PcieSlotStatus)\r
4493 );\r
4494 ShellPrintEx (-1, -1, L" MRL Sensor State(5): %EMRL ");\r
4495 if (PCIE_CAP_MRL_SENSOR_STATE (PcieSlotStatus)) {\r
4496 ShellPrintEx (-1, -1, L" Opened%N\r\n");\r
4497 } else {\r
4498 ShellPrintEx (-1, -1, L" Closed%N\r\n");\r
4499 }\r
4500 ShellPrintEx (-1, -1, L" Presence Detect State(6): ");\r
4501 if (PCIE_CAP_PRES_DETECT_STATE (PcieSlotStatus)) {\r
4502 ShellPrintEx (-1, -1, L"%ECard Present in slot%N\r\n");\r
4503 } else {\r
4504 ShellPrintEx (-1, -1, L"%ESlot Empty%N\r\n");\r
4505 }\r
4506 ShellPrintEx (-1, -1, L" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");\r
4507 if (PCIE_CAP_ELEC_INTERLOCK_STATE (PcieSlotStatus)) {\r
4508 ShellPrintEx (-1, -1, L"Engaged%N\r\n");\r
4509 } else {\r
4510 ShellPrintEx (-1, -1, L"Disengaged%N\r\n");\r
4511 }\r
4512 ShellPrintEx (-1, -1,\r
4513 L" Data Link Layer State Changed(8): %E%d%N\r\n",\r
4514 PCIE_CAP_DLINK_STAT_CHANGED (PcieSlotStatus)\r
4515 );\r
4516 return EFI_SUCCESS;\r
4517}\r
4518\r
4519/**\r
4520 Print out information of the device root information.\r
4521\r
4522 @param[in] PciExpressCap The pointer to the structure about the device.\r
4523\r
4524 @retval EFI_SUCCESS The operation was successful.\r
4525**/\r
4526EFI_STATUS\r
4527ExplainPcieRootControl (\r
4528 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4529 )\r
4530{\r
4531 UINT16 PcieRootControl;\r
4532\r
4533 PcieRootControl = PciExpressCap->RootControl;\r
4534\r
4535 ShellPrintEx (-1, -1,\r
4536 L" System Error on Correctable Error Enable(0): %E%d%N\r\n",\r
4537 PCIE_CAP_SYSERR_ON_CORERR_EN (PcieRootControl)\r
4538 );\r
4539 ShellPrintEx (-1, -1,\r
4540 L" System Error on Non-Fatal Error Enable(1): %E%d%N\r\n",\r
4541 PCIE_CAP_SYSERR_ON_NONFATERR_EN (PcieRootControl)\r
4542 );\r
4543 ShellPrintEx (-1, -1,\r
4544 L" System Error on Fatal Error Enable(2): %E%d%N\r\n",\r
4545 PCIE_CAP_SYSERR_ON_FATERR_EN (PcieRootControl)\r
4546 );\r
4547 ShellPrintEx (-1, -1,\r
4548 L" PME Interrupt Enable(3): %E%d%N\r\n",\r
4549 PCIE_CAP_PME_INT_ENABLE (PcieRootControl)\r
4550 );\r
4551 ShellPrintEx (-1, -1,\r
4552 L" CRS Software Visibility Enable(4): %E%d%N\r\n",\r
4553 PCIE_CAP_CRS_SW_VIS_ENABLE (PcieRootControl)\r
4554 );\r
4555\r
4556 return EFI_SUCCESS;\r
4557}\r
4558\r
4559/**\r
4560 Print out information of the device root capability information.\r
4561\r
4562 @param[in] PciExpressCap The pointer to the structure about the device.\r
4563\r
4564 @retval EFI_SUCCESS The operation was successful.\r
4565**/\r
4566EFI_STATUS\r
4567ExplainPcieRootCap (\r
4568 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4569 )\r
4570{\r
4571 UINT16 PcieRootCap;\r
4572\r
4573 PcieRootCap = PciExpressCap->RsvdP;\r
4574\r
4575 ShellPrintEx (-1, -1,\r
4576 L" CRS Software Visibility(0): %E%d%N\r\n",\r
4577 PCIE_CAP_CRS_SW_VIS (PcieRootCap)\r
4578 );\r
4579\r
4580 return EFI_SUCCESS;\r
4581}\r
4582\r
4583/**\r
4584 Print out information of the device root status information.\r
4585\r
4586 @param[in] PciExpressCap The pointer to the structure about the device.\r
4587\r
4588 @retval EFI_SUCCESS The operation was successful.\r
4589**/\r
4590EFI_STATUS\r
4591ExplainPcieRootStatus (\r
4592 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4593 )\r
4594{\r
4595 UINT32 PcieRootStatus;\r
4596\r
4597 PcieRootStatus = PciExpressCap->RootStatus;\r
4598\r
4599 ShellPrintEx (-1, -1,\r
4600 L" PME Requester ID(15:0): %E0x%04x%N\r\n",\r
4601 PCIE_CAP_PME_REQ_ID (PcieRootStatus)\r
4602 );\r
4603 ShellPrintEx (-1, -1,\r
4604 L" PME Status(16): %E%d%N\r\n",\r
4605 PCIE_CAP_PME_STATUS (PcieRootStatus)\r
4606 );\r
4607 ShellPrintEx (-1, -1,\r
4608 L" PME Pending(17): %E%d%N\r\n",\r
4609 PCIE_CAP_PME_PENDING (PcieRootStatus)\r
4610 );\r
4611 return EFI_SUCCESS;\r
4612}\r
4613\r
4614/**\r
4615 Function to interpret and print out the link control structure\r
4616\r
4617 @param[in] HeaderAddress The Address of this capability header.\r
4618 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
4619**/\r
4620EFI_STATUS\r
4621EFIAPI\r
4622PrintInterpretedExtendedCompatibilityLinkControl (\r
4623 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
4624 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
4625 )\r
4626{\r
4627 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL *Header;\r
4628 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL*)HeaderAddress;\r
4629\r
4630 ShellPrintHiiEx(\r
4631 -1, -1, NULL, \r
4632 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_CONTROL), \r
4633 gShellDebug1HiiHandle, \r
4634 Header->RootComplexLinkCapabilities,\r
4635 Header->RootComplexLinkControl,\r
4636 Header->RootComplexLinkStatus\r
4637 ); \r
4638 DumpHex (\r
4639 4,\r
4640 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
4641 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL),\r
4642 (VOID *) (HeaderAddress)\r
4643 );\r
4644 return (EFI_SUCCESS);\r
4645}\r
4646\r
4647/**\r
4648 Function to interpret and print out the power budgeting structure\r
4649\r
4650 @param[in] HeaderAddress The Address of this capability header.\r
4651 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
4652**/\r
4653EFI_STATUS\r
4654EFIAPI\r
4655PrintInterpretedExtendedCompatibilityPowerBudgeting (\r
4656 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
4657 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
4658 )\r
4659{\r
4660 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING *Header;\r
4661 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING*)HeaderAddress;\r
4662\r
4663 ShellPrintHiiEx(\r
4664 -1, -1, NULL, \r
4665 STRING_TOKEN (STR_PCI_EXT_CAP_POWER), \r
4666 gShellDebug1HiiHandle, \r
4667 Header->DataSelect,\r
4668 Header->Data,\r
4669 Header->PowerBudgetCapability\r
4670 ); \r
4671 DumpHex (\r
4672 4,\r
4673 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
4674 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING),\r
4675 (VOID *) (HeaderAddress)\r
4676 );\r
4677 return (EFI_SUCCESS);\r
4678}\r
4679\r
4680/**\r
4681 Function to interpret and print out the ACS structure\r
4682\r
4683 @param[in] HeaderAddress The Address of this capability header.\r
4684 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
4685**/\r
4686EFI_STATUS\r
4687EFIAPI\r
4688PrintInterpretedExtendedCompatibilityAcs (\r
4689 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
4690 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
4691 )\r
4692{\r
4693 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED *Header;\r
4694 UINT16 VectorSize;\r
4695 UINT16 LoopCounter;\r
4696\r
4697 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED*)HeaderAddress;\r
4698 VectorSize = 0;\r
4699\r
4700 ShellPrintHiiEx(\r
4701 -1, -1, NULL, \r
4702 STRING_TOKEN (STR_PCI_EXT_CAP_ACS), \r
4703 gShellDebug1HiiHandle, \r
4704 Header->AcsCapability,\r
4705 Header->AcsControl\r
4706 ); \r
4707 if (PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(Header)) {\r
4708 VectorSize = PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(Header);\r
4709 if (VectorSize == 0) {\r
4710 VectorSize = 256;\r
4711 }\r
4712 for (LoopCounter = 0 ; LoopCounter * 8 < VectorSize ; LoopCounter++) {\r
4713 ShellPrintHiiEx(\r
4714 -1, -1, NULL, \r
4715 STRING_TOKEN (STR_PCI_EXT_CAP_ACS2), \r
4716 gShellDebug1HiiHandle, \r
4717 LoopCounter + 1,\r
4718 Header->EgressControlVectorArray[LoopCounter]\r
4719 ); \r
4720 }\r
4721 }\r
4722 DumpHex (\r
4723 4,\r
4724 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
4725 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED) + (VectorSize / 8) - 1,\r
4726 (VOID *) (HeaderAddress)\r
4727 );\r
4728 return (EFI_SUCCESS);\r
4729}\r
4730\r
4731/**\r
4732 Function to interpret and print out the latency tolerance reporting structure\r
4733\r
4734 @param[in] HeaderAddress The Address of this capability header.\r
4735 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
4736**/\r
4737EFI_STATUS\r
4738EFIAPI\r
4739PrintInterpretedExtendedCompatibilityLatencyToleranceReporting (\r
4740 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
4741 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
4742 )\r
4743{\r
4744 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING *Header;\r
4745 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING*)HeaderAddress;\r
4746\r
4747 ShellPrintHiiEx(\r
4748 -1, -1, NULL, \r
4749 STRING_TOKEN (STR_PCI_EXT_CAP_LAT), \r
4750 gShellDebug1HiiHandle, \r
4751 Header->MaxSnoopLatency,\r
4752 Header->MaxNoSnoopLatency\r
4753 ); \r
4754 DumpHex (\r
4755 4,\r
4756 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
4757 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING),\r
4758 (VOID *) (HeaderAddress)\r
4759 );\r
4760 return (EFI_SUCCESS);\r
4761}\r
4762\r
4763/**\r
4764 Function to interpret and print out the serial number structure\r
4765\r
4766 @param[in] HeaderAddress The Address of this capability header.\r
4767 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
4768**/\r
4769EFI_STATUS\r
4770EFIAPI\r
4771PrintInterpretedExtendedCompatibilitySerialNumber (\r
4772 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
4773 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
4774 )\r
4775{\r
4776 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER *Header;\r
4777 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER*)HeaderAddress;\r
4778\r
4779 ShellPrintHiiEx(\r
4780 -1, -1, NULL, \r
4781 STRING_TOKEN (STR_PCI_EXT_CAP_SN), \r
4782 gShellDebug1HiiHandle, \r
4783 Header->SerialNumber\r
4784 ); \r
4785 DumpHex (\r
4786 4,\r
4787 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
4788 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER),\r
4789 (VOID *) (HeaderAddress)\r
4790 );\r
4791 return (EFI_SUCCESS);\r
4792}\r
4793\r
4794/**\r
4795 Function to interpret and print out the RCRB structure\r
4796\r
4797 @param[in] HeaderAddress The Address of this capability header.\r
4798 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
4799**/\r
4800EFI_STATUS\r
4801EFIAPI\r
4802PrintInterpretedExtendedCompatibilityRcrb (\r
4803 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
4804 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
4805 )\r
4806{\r
4807 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER *Header;\r
4808 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER*)HeaderAddress;\r
4809\r
4810 ShellPrintHiiEx(\r
4811 -1, -1, NULL, \r
4812 STRING_TOKEN (STR_PCI_EXT_CAP_RCRB), \r
4813 gShellDebug1HiiHandle, \r
4814 Header->VendorId,\r
4815 Header->DeviceId,\r
4816 Header->RcrbCapabilities,\r
4817 Header->RcrbControl\r
4818 ); \r
4819 DumpHex (\r
4820 4,\r
4821 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
4822 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER),\r
4823 (VOID *) (HeaderAddress)\r
4824 );\r
4825 return (EFI_SUCCESS);\r
4826}\r
4827\r
4828/**\r
4829 Function to interpret and print out the vendor specific structure\r
4830\r
4831 @param[in] HeaderAddress The Address of this capability header.\r
4832 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
4833**/\r
4834EFI_STATUS\r
4835EFIAPI\r
4836PrintInterpretedExtendedCompatibilityVendorSpecific (\r
4837 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
4838 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
4839 )\r
4840{\r
4841 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC *Header;\r
4842 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC*)HeaderAddress;\r
4843\r
4844 ShellPrintHiiEx(\r
4845 -1, -1, NULL, \r
4846 STRING_TOKEN (STR_PCI_EXT_CAP_VEN), \r
4847 gShellDebug1HiiHandle, \r
4848 Header->VendorSpecificHeader\r
4849 ); \r
4850 DumpHex (\r
4851 4,\r
4852 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
4853 PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(Header),\r
4854 (VOID *) (HeaderAddress)\r
4855 );\r
4856 return (EFI_SUCCESS);\r
4857}\r
4858\r
4859/**\r
4860 Function to interpret and print out the Event Collector Endpoint Association structure\r
4861\r
4862 @param[in] HeaderAddress The Address of this capability header.\r
4863 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
4864**/\r
4865EFI_STATUS\r
4866EFIAPI\r
4867PrintInterpretedExtendedCompatibilityECEA (\r
4868 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
4869 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
4870 )\r
4871{\r
4872 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION *Header;\r
4873 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION*)HeaderAddress;\r
4874\r
4875 ShellPrintHiiEx(\r
4876 -1, -1, NULL, \r
4877 STRING_TOKEN (STR_PCI_EXT_CAP_ECEA), \r
4878 gShellDebug1HiiHandle, \r
4879 Header->AssociationBitmap\r
4880 ); \r
4881 DumpHex (\r
4882 4,\r
4883 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
4884 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION),\r
4885 (VOID *) (HeaderAddress)\r
4886 );\r
4887 return (EFI_SUCCESS);\r
4888}\r
4889\r
4890/**\r
4891 Function to interpret and print out the ARI structure\r
4892\r
4893 @param[in] HeaderAddress The Address of this capability header.\r
4894 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
4895**/\r
4896EFI_STATUS\r
4897EFIAPI\r
4898PrintInterpretedExtendedCompatibilityAri (\r
4899 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
4900 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
4901 )\r
4902{\r
4903 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY *Header;\r
4904 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY*)HeaderAddress;\r
4905\r
4906 ShellPrintHiiEx(\r
4907 -1, -1, NULL, \r
4908 STRING_TOKEN (STR_PCI_EXT_CAP_ARI), \r
4909 gShellDebug1HiiHandle, \r
4910 Header->AriCapability,\r
4911 Header->AriControl\r
4912 ); \r
4913 DumpHex (\r
4914 4,\r
4915 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
4916 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY),\r
4917 (VOID *) (HeaderAddress)\r
4918 );\r
4919 return (EFI_SUCCESS);\r
4920}\r
4921\r
4922/**\r
4923 Function to interpret and print out the DPA structure\r
4924\r
4925 @param[in] HeaderAddress The Address of this capability header.\r
4926 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
4927**/\r
4928EFI_STATUS\r
4929EFIAPI\r
4930PrintInterpretedExtendedCompatibilityDynamicPowerAllocation (\r
4931 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
4932 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
4933 )\r
4934{\r
4935 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION *Header;\r
4936 UINT8 LinkCount;\r
4937 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION*)HeaderAddress;\r
4938\r
4939 ShellPrintHiiEx(\r
4940 -1, -1, NULL, \r
4941 STRING_TOKEN (STR_PCI_EXT_CAP_DPA), \r
4942 gShellDebug1HiiHandle, \r
4943 Header->DpaCapability,\r
4944 Header->DpaLatencyIndicator,\r
4945 Header->DpaStatus,\r
4946 Header->DpaControl\r
4947 ); \r
4948 for (LinkCount = 0 ; LinkCount < PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(Header) + 1 ; LinkCount++) {\r
4949 ShellPrintHiiEx(\r
4950 -1, -1, NULL, \r
4951 STRING_TOKEN (STR_PCI_EXT_CAP_DPA2), \r
4952 gShellDebug1HiiHandle, \r
4953 LinkCount+1,\r
4954 Header->DpaPowerAllocationArray[LinkCount]\r
4955 );\r
4956 }\r
4957 DumpHex (\r
4958 4,\r
4959 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
4960 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION) - 1 + PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(Header),\r
4961 (VOID *) (HeaderAddress)\r
4962 );\r
4963 return (EFI_SUCCESS);\r
4964}\r
4965\r
4966/**\r
4967 Function to interpret and print out the link declaration structure\r
4968\r
4969 @param[in] HeaderAddress The Address of this capability header.\r
4970 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
4971**/\r
4972EFI_STATUS\r
4973EFIAPI\r
4974PrintInterpretedExtendedCompatibilityLinkDeclaration (\r
4975 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
4976 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
4977 )\r
4978{\r
4979 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION *Header;\r
4980 UINT8 LinkCount;\r
4981 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION*)HeaderAddress;\r
4982\r
4983 ShellPrintHiiEx(\r
4984 -1, -1, NULL, \r
4985 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR), \r
4986 gShellDebug1HiiHandle, \r
4987 Header->ElementSelfDescription\r
4988 );\r
4989\r
4990 for (LinkCount = 0 ; LinkCount < PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(Header) ; LinkCount++) {\r
4991 ShellPrintHiiEx(\r
4992 -1, -1, NULL, \r
4993 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR2), \r
4994 gShellDebug1HiiHandle, \r
4995 LinkCount+1,\r
4996 Header->LinkEntry[LinkCount]\r
4997 );\r
4998 }\r
4999 DumpHex (\r
5000 4,\r
5001 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5002 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION) + (PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(Header)-1)*sizeof(UINT32),\r
5003 (VOID *) (HeaderAddress)\r
5004 );\r
5005 return (EFI_SUCCESS);\r
5006}\r
5007\r
5008/**\r
5009 Function to interpret and print out the Advanced Error Reporting structure\r
5010\r
5011 @param[in] HeaderAddress The Address of this capability header.\r
5012 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5013**/\r
5014EFI_STATUS\r
5015EFIAPI\r
5016PrintInterpretedExtendedCompatibilityAer (\r
5017 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5018 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5019 )\r
5020{\r
5021 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING *Header;\r
5022 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING*)HeaderAddress;\r
5023\r
5024 ShellPrintHiiEx(\r
5025 -1, -1, NULL, \r
5026 STRING_TOKEN (STR_PCI_EXT_CAP_AER), \r
5027 gShellDebug1HiiHandle, \r
5028 Header->UncorrectableErrorStatus,\r
5029 Header->UncorrectableErrorMask,\r
5030 Header->UncorrectableErrorSeverity,\r
5031 Header->CorrectableErrorStatus,\r
5032 Header->CorrectableErrorMask,\r
5033 Header->AdvancedErrorCapabilitiesAndControl,\r
5034 Header->HeaderLog,\r
5035 Header->RootErrorCommand,\r
5036 Header->RootErrorStatus,\r
5037 Header->ErrorSourceIdentification,\r
5038 Header->CorrectableErrorSourceIdentification,\r
5039 Header->TlpPrefixLog[0],\r
5040 Header->TlpPrefixLog[1],\r
5041 Header->TlpPrefixLog[2],\r
5042 Header->TlpPrefixLog[3]\r
5043 );\r
5044 DumpHex (\r
5045 4,\r
5046 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5047 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING),\r
5048 (VOID *) (HeaderAddress)\r
5049 );\r
5050 return (EFI_SUCCESS);\r
5051}\r
5052\r
5053/**\r
5054 Function to interpret and print out the multicast structure\r
5055\r
5056 @param[in] HeaderAddress The Address of this capability header.\r
5057 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5058 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r
5059**/\r
5060EFI_STATUS\r
5061EFIAPI\r
5062PrintInterpretedExtendedCompatibilityMulticast (\r
5063 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5064 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,\r
5065 IN CONST PCIE_CAP_STURCTURE *PciExpressCapPtr\r
5066 )\r
5067{\r
5068 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST *Header;\r
5069 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST*)HeaderAddress;\r
5070\r
5071 ShellPrintHiiEx(\r
5072 -1, -1, NULL, \r
5073 STRING_TOKEN (STR_PCI_EXT_CAP_MULTICAST), \r
5074 gShellDebug1HiiHandle, \r
5075 Header->MultiCastCapability,\r
5076 Header->MulticastControl,\r
5077 Header->McBaseAddress,\r
5078 Header->McReceiveAddress,\r
5079 Header->McBlockAll,\r
5080 Header->McBlockUntranslated,\r
5081 Header->McOverlayBar\r
5082 );\r
5083\r
5084 DumpHex (\r
5085 4,\r
5086 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5087 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST),\r
5088 (VOID *) (HeaderAddress)\r
5089 );\r
5090\r
5091 return (EFI_SUCCESS);\r
5092}\r
5093\r
5094/**\r
5095 Function to interpret and print out the virtual channel and multi virtual channel structure\r
5096\r
5097 @param[in] HeaderAddress The Address of this capability header.\r
5098 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5099**/\r
5100EFI_STATUS\r
5101EFIAPI\r
5102PrintInterpretedExtendedCompatibilityVirtualChannel (\r
5103 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5104 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5105 )\r
5106{\r
5107 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY *Header;\r
5108 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC *CapabilityItem;\r
5109 UINT32 ItemCount;\r
5110 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY*)HeaderAddress;\r
5111\r
5112 ShellPrintHiiEx(\r
5113 -1, -1, NULL, \r
5114 STRING_TOKEN (STR_PCI_EXT_CAP_VC_BASE), \r
5115 gShellDebug1HiiHandle, \r
5116 Header->ExtendedVcCount,\r
5117 Header->PortVcCapability1,\r
5118 Header->PortVcCapability2,\r
5119 Header->VcArbTableOffset,\r
5120 Header->PortVcControl,\r
5121 Header->PortVcStatus\r
5122 );\r
5123 for (ItemCount = 0 ; ItemCount < Header->ExtendedVcCount ; ItemCount++) {\r
5124 CapabilityItem = &Header->Capability[ItemCount];\r
5125 ShellPrintHiiEx(\r
5126 -1, -1, NULL, \r
5127 STRING_TOKEN (STR_PCI_EXT_CAP_VC_ITEM), \r
5128 gShellDebug1HiiHandle, \r
5129 ItemCount+1,\r
5130 CapabilityItem->VcResourceCapability,\r
5131 CapabilityItem->PortArbTableOffset,\r
5132 CapabilityItem->VcResourceControl,\r
5133 CapabilityItem->VcResourceStatus\r
5134 );\r
5135 }\r
5136\r
5137 DumpHex (\r
5138 4,\r
5139 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5140 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC) + (Header->ExtendedVcCount - 1) * sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY),\r
5141 (VOID *) (HeaderAddress)\r
5142 );\r
5143\r
5144 return (EFI_SUCCESS);\r
5145}\r
5146\r
5147/**\r
5148 Function to interpret and print out the resizeable bar structure\r
5149\r
5150 @param[in] HeaderAddress The Address of this capability header.\r
5151 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5152**/\r
5153EFI_STATUS\r
5154EFIAPI\r
5155PrintInterpretedExtendedCompatibilityResizeableBar (\r
5156 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5157 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5158 )\r
5159{\r
5160 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR *Header;\r
5161 UINT32 ItemCount;\r
5162 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR*)HeaderAddress;\r
5163\r
5164 for (ItemCount = 0 ; ItemCount < (UINT32)GET_NUMBER_RESIZABLE_BARS(Header) ; ItemCount++) {\r
5165 ShellPrintHiiEx(\r
5166 -1, -1, NULL, \r
5167 STRING_TOKEN (STR_PCI_EXT_CAP_RESIZE_BAR), \r
5168 gShellDebug1HiiHandle, \r
5169 ItemCount+1,\r
5170 Header->Capability[ItemCount].ResizableBarCapability,\r
5171 Header->Capability[ItemCount].ResizableBarControl\r
5172 );\r
5173 }\r
5174\r
5175 DumpHex (\r
5176 4,\r
5177 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5178 (UINT32)GET_NUMBER_RESIZABLE_BARS(Header) * sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY),\r
5179 (VOID *) (HeaderAddress)\r
5180 );\r
5181\r
5182 return (EFI_SUCCESS);\r
5183}\r
5184\r
5185/**\r
5186 Function to interpret and print out the TPH structure\r
5187\r
5188 @param[in] HeaderAddress The Address of this capability header.\r
5189 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5190**/\r
5191EFI_STATUS\r
5192EFIAPI\r
5193PrintInterpretedExtendedCompatibilityTph (\r
5194 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5195 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5196 )\r
5197{\r
5198 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH *Header;\r
5199 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH*)HeaderAddress;\r
5200\r
5201 ShellPrintHiiEx(\r
5202 -1, -1, NULL, \r
5203 STRING_TOKEN (STR_PCI_EXT_CAP_TPH), \r
5204 gShellDebug1HiiHandle, \r
5205 Header->TphRequesterCapability,\r
5206 Header->TphRequesterControl\r
5207 );\r
5208 DumpHex (\r
5209 8,\r
5210 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)Header->TphStTable - (UINT8*)HeadersBaseAddress),\r
5211 GET_TPH_TABLE_SIZE(Header),\r
5212 (VOID *)Header->TphStTable\r
5213 );\r
5214\r
5215 DumpHex (\r
5216 4,\r
5217 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5218 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH) + GET_TPH_TABLE_SIZE(Header) - sizeof(UINT16),\r
5219 (VOID *) (HeaderAddress)\r
5220 );\r
5221\r
5222 return (EFI_SUCCESS);\r
5223}\r
5224\r
5225/**\r
5226 Function to interpret and print out the secondary PCIe capability structure\r
5227\r
5228 @param[in] HeaderAddress The Address of this capability header.\r
5229 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5230 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r
5231**/\r
5232EFI_STATUS\r
5233EFIAPI\r
5234PrintInterpretedExtendedCompatibilitySecondary (\r
5235 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5236 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,\r
5237 IN CONST PCIE_CAP_STURCTURE *PciExpressCapPtr\r
5238 )\r
5239{\r
5240 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE *Header;\r
5241 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE*)HeaderAddress;\r
5242\r
5243 ShellPrintHiiEx(\r
5244 -1, -1, NULL, \r
5245 STRING_TOKEN (STR_PCI_EXT_CAP_SECONDARY), \r
5246 gShellDebug1HiiHandle, \r
5247 Header->LinkControl3,\r
5248 Header->LaneErrorStatus\r
5249 );\r
5250 DumpHex (\r
5251 8,\r
5252 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)Header->EqualizationControl - (UINT8*)HeadersBaseAddress),\r
5253 PCIE_CAP_MAX_LINK_WIDTH(PciExpressCapPtr->LinkCap),\r
5254 (VOID *)Header->EqualizationControl\r
5255 );\r
5256\r
5257 DumpHex (\r
5258 4,\r
5259 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5260 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH) - sizeof(Header->EqualizationControl) + PCIE_CAP_MAX_LINK_WIDTH(PciExpressCapPtr->LinkCap),\r
5261 (VOID *) (HeaderAddress)\r
5262 );\r
5263\r
5264 return (EFI_SUCCESS);\r
5265}\r
5266\r
5267/**\r
5268 Display Pcie extended capability details\r
5269\r
5270 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5271 @param[in] HeaderAddress The address of this capability header.\r
5272 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r
5273**/\r
5274EFI_STATUS\r
5275EFIAPI\r
5276PrintPciExtendedCapabilityDetails(\r
5277 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress, \r
5278 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5279 IN CONST PCIE_CAP_STURCTURE *PciExpressCapPtr\r
5280 )\r
5281{\r
5282 switch (HeaderAddress->CapabilityId){\r
5283 case PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID:\r
5284 return PrintInterpretedExtendedCompatibilityAer(HeaderAddress, HeadersBaseAddress);\r
5285 case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID:\r
5286 return PrintInterpretedExtendedCompatibilityLinkControl(HeaderAddress, HeadersBaseAddress);\r
5287 case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID:\r
5288 return PrintInterpretedExtendedCompatibilityLinkDeclaration(HeaderAddress, HeadersBaseAddress);\r
5289 case PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID:\r
5290 return PrintInterpretedExtendedCompatibilitySerialNumber(HeaderAddress, HeadersBaseAddress);\r
5291 case PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID:\r
5292 return PrintInterpretedExtendedCompatibilityPowerBudgeting(HeaderAddress, HeadersBaseAddress);\r
5293 case PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID:\r
5294 return PrintInterpretedExtendedCompatibilityAcs(HeaderAddress, HeadersBaseAddress);\r
5295 case PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID:\r
5296 return PrintInterpretedExtendedCompatibilityLatencyToleranceReporting(HeaderAddress, HeadersBaseAddress);\r
5297 case PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID:\r
5298 return PrintInterpretedExtendedCompatibilityAri(HeaderAddress, HeadersBaseAddress);\r
5299 case PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID:\r
5300 return PrintInterpretedExtendedCompatibilityRcrb(HeaderAddress, HeadersBaseAddress);\r
5301 case PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID:\r
5302 return PrintInterpretedExtendedCompatibilityVendorSpecific(HeaderAddress, HeadersBaseAddress);\r
5303 case PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID:\r
5304 return PrintInterpretedExtendedCompatibilityDynamicPowerAllocation(HeaderAddress, HeadersBaseAddress);\r
5305 case PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID:\r
5306 return PrintInterpretedExtendedCompatibilityECEA(HeaderAddress, HeadersBaseAddress);\r
5307 case PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID:\r
5308 case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID:\r
5309 return PrintInterpretedExtendedCompatibilityVirtualChannel(HeaderAddress, HeadersBaseAddress);\r
5310 case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID: \r
5311 //\r
5312 // should only be present if PCIE_CAP_DEVICEPORT_TYPE(PciExpressCapPtr->PcieCapReg) == 0100b, 0101b, or 0110b\r
5313 //\r
5314 return PrintInterpretedExtendedCompatibilityMulticast(HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);\r
5315 case PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID:\r
5316 return PrintInterpretedExtendedCompatibilityResizeableBar(HeaderAddress, HeadersBaseAddress);\r
5317 case PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID:\r
5318 return PrintInterpretedExtendedCompatibilityTph(HeaderAddress, HeadersBaseAddress);\r
5319 case PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID:\r
5320 return PrintInterpretedExtendedCompatibilitySecondary(HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);\r
5321 default:\r
5322 ShellPrintEx (-1, -1,\r
5323 L"Unknown PCIe extended capability ID (%04xh). No interpretation available.\r\n",\r
5324 HeaderAddress->CapabilityId\r
5325 );\r
5326 return EFI_SUCCESS;\r
5327 };\r
5328\r
5329}\r
5330\r
5331/**\r
5332 Display Pcie device structure.\r
5333\r
5334 @param[in] IoDev The pointer to the root pci protocol.\r
5335 @param[in] Address The Address to start at.\r
5336 @param[in] CapabilityPtr The offset from the address to start.\r
5337 @param[in] EnhancedDump The print format for the dump data.\r
5338 \r
5339**/\r
5340EFI_STATUS\r
5341PciExplainPciExpress (\r
5342 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
5343 IN UINT64 Address,\r
5344 IN UINT8 CapabilityPtr,\r
5345 IN CONST UINT16 EnhancedDump\r
5346 )\r
5347{\r
5348\r
5349 PCIE_CAP_STURCTURE PciExpressCap;\r
5350 EFI_STATUS Status;\r
5351 UINT64 CapRegAddress;\r
5352 UINT8 Bus;\r
5353 UINT8 Dev;\r
5354 UINT8 Func;\r
5355 UINT8 *ExRegBuffer;\r
5356 UINTN ExtendRegSize;\r
5357 UINT64 Pciex_Address;\r
5358 UINT8 DevicePortType;\r
5359 UINTN Index;\r
5360 UINT8 *RegAddr;\r
5361 UINTN RegValue;\r
5362 PCI_EXP_EXT_HDR *ExtHdr;\r
5363\r
5364 CapRegAddress = Address + CapabilityPtr;\r
5365 IoDev->Pci.Read (\r
5366 IoDev,\r
5367 EfiPciWidthUint32,\r
5368 CapRegAddress,\r
5369 sizeof (PciExpressCap) / sizeof (UINT32),\r
5370 &PciExpressCap\r
5371 );\r
5372\r
5373 DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap.PcieCapReg);\r
5374\r
5375 ShellPrintEx (-1, -1, L"\r\nPci Express device capability structure:\r\n");\r
5376\r
5377 for (Index = 0; PcieExplainList[Index].Type < PcieExplainTypeMax; Index++) {\r
5378 if (ShellGetExecutionBreakFlag()) {\r
5379 goto Done;\r
5380 }\r
5381 RegAddr = ((UINT8 *) &PciExpressCap) + PcieExplainList[Index].Offset;\r
5382 switch (PcieExplainList[Index].Width) {\r
5383 case FieldWidthUINT8:\r
5384 RegValue = *(UINT8 *) RegAddr;\r
5385 break;\r
5386 case FieldWidthUINT16:\r
5387 RegValue = *(UINT16 *) RegAddr;\r
5388 break;\r
5389 case FieldWidthUINT32:\r
5390 RegValue = *(UINT32 *) RegAddr;\r
5391 break;\r
5392 default:\r
5393 RegValue = 0;\r
5394 break;\r
5395 }\r
5396 ShellPrintHiiEx(-1, -1, NULL,\r
5397 PcieExplainList[Index].Token,\r
5398 gShellDebug1HiiHandle,\r
5399 PcieExplainList[Index].Offset,\r
5400 RegValue\r
5401 );\r
5402 if (PcieExplainList[Index].Func == NULL) {\r
5403 continue;\r
5404 }\r
5405 switch (PcieExplainList[Index].Type) {\r
5406 case PcieExplainTypeLink:\r
5407 //\r
5408 // Link registers should not be used by\r
5409 // a) Root Complex Integrated Endpoint\r
5410 // b) Root Complex Event Collector\r
5411 //\r
5412 if (DevicePortType == PCIE_ROOT_COMPLEX_INTEGRATED_PORT ||\r
5413 DevicePortType == PCIE_ROOT_COMPLEX_EVENT_COLLECTOR) {\r
5414 continue;\r
5415 }\r
5416 break;\r
5417 case PcieExplainTypeSlot:\r
5418 //\r
5419 // Slot registers are only valid for\r
5420 // a) Root Port of PCI Express Root Complex\r
5421 // b) Downstream Port of PCI Express Switch\r
5422 // and when SlotImplemented bit is set in PCIE cap register.\r
5423 //\r
5424 if ((DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT &&\r
5425 DevicePortType != PCIE_SWITCH_DOWNSTREAM_PORT) ||\r
5426 !PCIE_CAP_SLOT_IMPLEMENTED (PciExpressCap.PcieCapReg)) {\r
5427 continue;\r
5428 }\r
5429 break;\r
5430 case PcieExplainTypeRoot:\r
5431 //\r
5432 // Root registers are only valid for\r
5433 // Root Port of PCI Express Root Complex\r
5434 //\r
5435 if (DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT) {\r
5436 continue;\r
5437 }\r
5438 break;\r
5439 default:\r
5440 break;\r
5441 }\r
5442 PcieExplainList[Index].Func (&PciExpressCap);\r
5443 }\r
5444\r
5445 Bus = (UINT8) (RShiftU64 (Address, 24));\r
5446 Dev = (UINT8) (RShiftU64 (Address, 16));\r
5447 Func = (UINT8) (RShiftU64 (Address, 8));\r
5448\r
5449 Pciex_Address = CALC_EFI_PCIEX_ADDRESS (Bus, Dev, Func, EFI_PCIE_CAPABILITY_BASE_OFFSET);\r
5450\r
5451 ExtendRegSize = 0x1000 - EFI_PCIE_CAPABILITY_BASE_OFFSET;\r
5452\r
5453 ExRegBuffer = (UINT8 *) AllocateZeroPool (ExtendRegSize);\r
5454\r
5455 //\r
5456 // PciRootBridgeIo protocol should support pci express extend space IO\r
5457 // (Begins at offset EFI_PCIE_CAPABILITY_BASE_OFFSET)\r
5458 //\r
5459 Status = IoDev->Pci.Read (\r
5460 IoDev,\r
5461 EfiPciWidthUint32,\r
5462 Pciex_Address,\r
5463 (ExtendRegSize) / sizeof (UINT32),\r
5464 (VOID *) (ExRegBuffer)\r
5465 );\r
5466 if (EFI_ERROR (Status) || ExRegBuffer == NULL) {\r
5467 SHELL_FREE_NON_NULL(ExRegBuffer);\r
5468 return EFI_UNSUPPORTED;\r
5469 }\r
5470\r
5471 if (EnhancedDump == 0) {\r
5472 //\r
5473 // Print the PciEx extend space in raw bytes ( 0xFF-0xFFF)\r
5474 //\r
5475 ShellPrintEx (-1, -1, L"\r\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\r\n\r\n");\r
5476\r
5477 DumpHex (\r
5478 2,\r
5479 EFI_PCIE_CAPABILITY_BASE_OFFSET,\r
5480 ExtendRegSize,\r
5481 (VOID *) (ExRegBuffer)\r
5482 );\r
5483 } else {\r
5484 ExtHdr = (PCI_EXP_EXT_HDR*)ExRegBuffer;\r
5485 while (ExtHdr->CapabilityId != 0 && ExtHdr->CapabilityVersion != 0) {\r
5486 //\r
5487 // Process this item\r
5488 //\r
5489 if (EnhancedDump == 0xFFFF || EnhancedDump == ExtHdr->CapabilityId) {\r
5490 //\r
5491 // Print this item\r
5492 //\r
5493 PrintPciExtendedCapabilityDetails((PCI_EXP_EXT_HDR*)ExRegBuffer, ExtHdr, &PciExpressCap);\r
5494 }\r
5495\r
5496 //\r
5497 // Advance to the next item if it exists\r
5498 //\r
5499 if (ExtHdr->NextCapabilityOffset != 0) {\r
5500 ExtHdr = (PCI_EXP_EXT_HDR*)((UINT8*)ExRegBuffer + ExtHdr->NextCapabilityOffset);\r
5501 } else {\r
5502 break;\r
5503 }\r
5504 }\r
5505 }\r
5506 SHELL_FREE_NON_NULL(ExRegBuffer);\r
5507\r
5508Done:\r
5509 return EFI_SUCCESS;\r
5510}\r
EFI Development Kit II mirror for PVE