[mirror_edk2.git] / UefiCpuPkg / Include / Library / LocalApicLib.h

/** @file\r
  Public include file for Local APIC library.\r
\r
  Local APIC library assumes local APIC is enabled. It does not\r
  handles cases where local APIC is disabled.\r
\r
  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef __LOCAL_APIC_LIB_H__\r
#define __LOCAL_APIC_LIB_H__\r
\r
#define LOCAL_APIC_MODE_XAPIC   0x1  ///< xAPIC mode.\r
#define LOCAL_APIC_MODE_X2APIC  0x2  ///< x2APIC mode.\r
\r
/**\r
  Retrieve the base address of local APIC.\r
\r
  @return The base address of local APIC.\r
\r
**/\r
UINTN\r
EFIAPI\r
GetLocalApicBaseAddress (\r
  VOID\r
  );\r
\r
/**\r
  Set the base address of local APIC.\r
\r
  If BaseAddress is not aligned on a 4KB boundary, then ASSERT().\r
\r
  @param[in] BaseAddress   Local APIC base address to be set.\r
\r
**/\r
VOID\r
EFIAPI\r
SetLocalApicBaseAddress (\r
  IN UINTN                BaseAddress\r
  );\r
\r
/**\r
  Get the current local APIC mode.\r
\r
  If local APIC is disabled, then ASSERT.\r
\r
  @retval LOCAL_APIC_MODE_XAPIC  current APIC mode is xAPIC.\r
  @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.\r
**/\r
UINTN\r
EFIAPI\r
GetApicMode (\r
  VOID\r
  );\r
\r
/**\r
  Set the current local APIC mode.\r
\r
  If the specified local APIC mode is not valid, then ASSERT.\r
  If the specified local APIC mode can't be set as current, then ASSERT.\r
\r
  @param ApicMode APIC mode to be set.\r
\r
  @note  This API must not be called from an interrupt handler or SMI handler.\r
         It may result in unpredictable behavior.\r
**/\r
VOID\r
EFIAPI\r
SetApicMode (\r
  IN UINTN  ApicMode\r
  );\r
\r
/**\r
  Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.\r
\r
  In xAPIC mode, the initial local APIC ID may be different from current APIC ID.\r
  In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case, \r
  the 32-bit local APIC ID is returned as initial APIC ID.\r
\r
  @return  32-bit initial local APIC ID of the executing processor.\r
**/\r
UINT32\r
EFIAPI\r
GetInitialApicId (\r
  VOID\r
  );\r
\r
/**\r
  Get the local APIC ID of the executing processor.\r
\r
  @return  32-bit local APIC ID of the executing processor.\r
**/\r
UINT32\r
EFIAPI\r
GetApicId (\r
  VOID\r
  );\r
\r
/**\r
  Get the value of the local APIC version register.\r
\r
  @return  the value of the local APIC version register.\r
**/\r
UINT32\r
EFIAPI\r
GetApicVersion (\r
  VOID\r
  );\r
\r
/**\r
  Send a Fixed IPI to a specified target processor.\r
\r
  This function returns after the IPI has been accepted by the target processor. \r
\r
  @param  ApicId   The local APIC ID of the target processor.\r
  @param  Vector   The vector number of the interrupt being sent.\r
**/\r
VOID\r
EFIAPI\r
SendFixedIpi (\r
  IN UINT32          ApicId,\r
  IN UINT8           Vector\r
  );\r
\r
/**\r
  Send a Fixed IPI to all processors excluding self.\r
\r
  This function returns after the IPI has been accepted by the target processors. \r
\r
  @param  Vector   The vector number of the interrupt being sent.\r
**/\r
VOID\r
EFIAPI\r
SendFixedIpiAllExcludingSelf (\r
  IN UINT8           Vector\r
  );\r
\r
/**\r
  Send a SMI IPI to a specified target processor.\r
\r
  This function returns after the IPI has been accepted by the target processor. \r
\r
  @param  ApicId   Specify the local APIC ID of the target processor.\r
**/\r
VOID\r
EFIAPI\r
SendSmiIpi (\r
  IN UINT32          ApicId\r
  );\r
\r
/**\r
  Send a SMI IPI to all processors excluding self.\r
\r
  This function returns after the IPI has been accepted by the target processors. \r
**/\r
VOID\r
EFIAPI\r
SendSmiIpiAllExcludingSelf (\r
  VOID\r
  );\r
\r
/**\r
  Send an INIT IPI to a specified target processor.\r
\r
  This function returns after the IPI has been accepted by the target processor. \r
\r
  @param  ApicId   Specify the local APIC ID of the target processor.\r
**/\r
VOID\r
EFIAPI\r
SendInitIpi (\r
  IN UINT32          ApicId\r
  );\r
\r
/**\r
  Send an INIT IPI to all processors excluding self.\r
\r
  This function returns after the IPI has been accepted by the target processors. \r
**/\r
VOID\r
EFIAPI\r
SendInitIpiAllExcludingSelf (\r
  VOID\r
  );\r
\r
/**\r
  Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.\r
\r
  This function returns after the IPI has been accepted by the target processor. \r
\r
  if StartupRoutine >= 1M, then ASSERT.\r
  if StartupRoutine is not multiple of 4K, then ASSERT.\r
\r
  @param  ApicId          Specify the local APIC ID of the target processor.\r
  @param  StartupRoutine  Points to a start-up routine which is below 1M physical\r
                          address and 4K aligned.\r
**/\r
VOID\r
EFIAPI\r
SendInitSipiSipi (\r
  IN UINT32          ApicId,\r
  IN UINT32          StartupRoutine\r
  );\r
\r
/**\r
  Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.\r
\r
  This function returns after the IPI has been accepted by the target processors. \r
\r
  if StartupRoutine >= 1M, then ASSERT.\r
  if StartupRoutine is not multiple of 4K, then ASSERT.\r
\r
  @param  StartupRoutine    Points to a start-up routine which is below 1M physical\r
                            address and 4K aligned.\r
**/\r
VOID\r
EFIAPI\r
SendInitSipiSipiAllExcludingSelf (\r
  IN UINT32          StartupRoutine\r
  );\r
\r
/**\r
  Initialize the state of the SoftwareEnable bit in the Local APIC\r
  Spurious Interrupt Vector register.\r
\r
  @param  Enable  If TRUE, then set SoftwareEnable to 1\r
                  If FALSE, then set SoftwareEnable to 0.\r
\r
**/\r
VOID\r
EFIAPI\r
InitializeLocalApicSoftwareEnable (\r
  IN BOOLEAN  Enable\r
  );\r
\r
/**\r
  Programming Virtual Wire Mode.\r
\r
  This function programs the local APIC for virtual wire mode following\r
  the example described in chapter A.3 of the MP 1.4 spec.\r
\r
  IOxAPIC is not involved in this type of virtual wire mode.\r
**/\r
VOID\r
EFIAPI\r
ProgramVirtualWireMode (\r
  VOID\r
  );\r
\r
/**\r
  Disable LINT0 & LINT1 interrupts.\r
\r
  This function sets the mask flag in the LVT LINT0 & LINT1 registers.\r
**/\r
VOID\r
EFIAPI\r
DisableLvtInterrupts (\r
  VOID\r
  );\r
\r
/**\r
  Read the initial count value from the init-count register.\r
\r
  @return The initial count value read from the init-count register.\r
**/\r
UINT32\r
EFIAPI\r
GetApicTimerInitCount (\r
  VOID\r
  );\r
\r
/**\r
  Read the current count value from the current-count register.\r
\r
  @return The current count value read from the current-count register.\r
**/\r
UINT32\r
EFIAPI\r
GetApicTimerCurrentCount (\r
  VOID\r
  );\r
\r
/**\r
  Initialize the local APIC timer.\r
\r
  The local APIC timer is initialized and enabled.\r
\r
  @param DivideValue   The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r
                       If it is 0, then use the current divide value in the DCR.\r
  @param InitCount     The initial count value.\r
  @param PeriodicMode  If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r
  @param Vector        The timer interrupt vector number.\r
**/\r
VOID\r
EFIAPI\r
InitializeApicTimer (\r
  IN UINTN   DivideValue,\r
  IN UINT32  InitCount,\r
  IN BOOLEAN PeriodicMode,\r
  IN UINT8   Vector\r
  );\r
\r
/**\r
  Get the state of the local APIC timer.\r
\r
  @param DivideValue   Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r
  @param PeriodicMode  Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r
  @param Vector        Return the timer interrupt vector number.\r
**/\r
VOID\r
EFIAPI\r
GetApicTimerState (\r
  OUT UINTN    *DivideValue  OPTIONAL,\r
  OUT BOOLEAN  *PeriodicMode  OPTIONAL,\r
  OUT UINT8    *Vector  OPTIONAL\r
  );\r
\r
/**\r
  Enable the local APIC timer interrupt.\r
**/\r
VOID\r
EFIAPI\r
EnableApicTimerInterrupt (\r
  VOID\r
  );\r
\r
/**\r
  Disable the local APIC timer interrupt.\r
**/\r
VOID\r
EFIAPI\r
DisableApicTimerInterrupt (\r
  VOID\r
  );\r
\r
/**\r
  Get the local APIC timer interrupt state.\r
\r
  @retval TRUE  The local APIC timer interrupt is enabled.\r
  @retval FALSE The local APIC timer interrupt is disabled.\r
**/\r
BOOLEAN\r
EFIAPI\r
GetApicTimerInterruptState (\r
  VOID\r
  );\r
\r
/**\r
  Send EOI to the local APIC.\r
**/\r
VOID\r
EFIAPI\r
SendApicEoi (\r
  VOID\r
  );\r
\r
/**\r
  Get the 32-bit address that a device should use to send a Message Signaled \r
  Interrupt (MSI) to the Local APIC of the currently executing processor.\r
\r
  @return 32-bit address used to send an MSI to the Local APIC.\r
**/\r
UINT32\r
EFIAPI    \r
GetApicMsiAddress (\r
  VOID\r
  );\r
    \r
/**\r
  Get the 64-bit data value that a device should use to send a Message Signaled \r
  Interrupt (MSI) to the Local APIC of the currently executing processor.\r
\r
  If Vector is not in range 0x10..0xFE, then ASSERT().\r
  If DeliveryMode is not supported, then ASSERT().\r
  \r
  @param  Vector          The 8-bit interrupt vector associated with the MSI.  \r
                          Must be in the range 0x10..0xFE\r
  @param  DeliveryMode    A 3-bit value that specifies how the recept of the MSI \r
                          is handled.  The only supported values are:\r
                            0: LOCAL_APIC_DELIVERY_MODE_FIXED\r
                            1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r
                            2: LOCAL_APIC_DELIVERY_MODE_SMI\r
                            4: LOCAL_APIC_DELIVERY_MODE_NMI\r
                            5: LOCAL_APIC_DELIVERY_MODE_INIT\r
                            7: LOCAL_APIC_DELIVERY_MODE_EXTINT\r
                          \r
  @param  LevelTriggered  TRUE specifies a level triggered interrupt.  \r
                          FALSE specifies an edge triggered interrupt.\r
  @param  AssertionLevel  Ignored if LevelTriggered is FALSE.\r
                          TRUE specifies a level triggered interrupt that active \r
                          when the interrupt line is asserted.\r
                          FALSE specifies a level triggered interrupt that active \r
                          when the interrupt line is deasserted.\r
\r
  @return 64-bit data value used to send an MSI to the Local APIC.\r
**/\r
UINT64\r
EFIAPI    \r
GetApicMsiValue (\r
  IN UINT8    Vector,\r
  IN UINTN    DeliveryMode,\r
  IN BOOLEAN  LevelTriggered,\r
  IN BOOLEAN  AssertionLevel\r
  );\r
\r
/**\r
  Get Package ID/Core ID/Thread ID of a processor.\r
\r
  The algorithm assumes the target system has symmetry across physical\r
  package  boundaries with respect to the number of logical processors\r
  per package,  number of cores per package.\r
\r
  @param[in]  InitialApicId  Initial APIC ID of the target logical processor.\r
  @param[out]  Package       Returns the processor package ID.\r
  @param[out]  Core          Returns the processor core ID.\r
  @param[out]  Thread        Returns the processor thread ID.\r
**/\r
VOID\r
GetProcessorLocation(\r
  IN  UINT32  InitialApicId,\r
  OUT UINT32  *Package  OPTIONAL,\r
  OUT UINT32  *Core    OPTIONAL,\r
  OUT UINT32  *Thread  OPTIONAL\r
  );\r
  \r
#endif\r
\r
Commit	Line	Data
	1	/** @file\r
	2	Public include file for Local APIC library.\r
	3	\r
	4	Local APIC library assumes local APIC is enabled. It does not\r
	5	handles cases where local APIC is disabled.\r
	6	\r
	7	Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
	8	This program and the accompanying materials\r
	9	are licensed and made available under the terms and conditions of the BSD License\r
	10	which accompanies this distribution. The full text of the license may be found at\r
	11	http://opensource.org/licenses/bsd-license.php\r
	12	\r
	13	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	14	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	15	\r
	16	**/\r
	17	\r
	18	#ifndef __LOCAL_APIC_LIB_H__\r
	19	#define __LOCAL_APIC_LIB_H__\r
	20	\r
	21	#define LOCAL_APIC_MODE_XAPIC 0x1 ///< xAPIC mode.\r
	22	#define LOCAL_APIC_MODE_X2APIC 0x2 ///< x2APIC mode.\r
	23	\r
	24	/**\r
	25	Retrieve the base address of local APIC.\r
	26	\r
	27	@return The base address of local APIC.\r
	28	\r
	29	**/\r
	30	UINTN\r
	31	EFIAPI\r
	32	GetLocalApicBaseAddress (\r
	33	VOID\r
	34	);\r
	35	\r
	36	/**\r
	37	Set the base address of local APIC.\r
	38	\r
	39	If BaseAddress is not aligned on a 4KB boundary, then ASSERT().\r
	40	\r
	41	@param[in] BaseAddress Local APIC base address to be set.\r
	42	\r
	43	**/\r
	44	VOID\r
	45	EFIAPI\r
	46	SetLocalApicBaseAddress (\r
	47	IN UINTN BaseAddress\r
	48	);\r
	49	\r
	50	/**\r
	51	Get the current local APIC mode.\r
	52	\r
	53	If local APIC is disabled, then ASSERT.\r
	54	\r
	55	@retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.\r
	56	@retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.\r
	57	**/\r
	58	UINTN\r
	59	EFIAPI\r
	60	GetApicMode (\r
	61	VOID\r
	62	);\r
	63	\r
	64	/**\r
	65	Set the current local APIC mode.\r
	66	\r
	67	If the specified local APIC mode is not valid, then ASSERT.\r
	68	If the specified local APIC mode can't be set as current, then ASSERT.\r
	69	\r
	70	@param ApicMode APIC mode to be set.\r
	71	\r
	72	@note This API must not be called from an interrupt handler or SMI handler.\r
	73	It may result in unpredictable behavior.\r
	74	**/\r
	75	VOID\r
	76	EFIAPI\r
	77	SetApicMode (\r
	78	IN UINTN ApicMode\r
	79	);\r
	80	\r
	81	/**\r
	82	Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.\r
	83	\r
	84	In xAPIC mode, the initial local APIC ID may be different from current APIC ID.\r
	85	In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case, \r
	86	the 32-bit local APIC ID is returned as initial APIC ID.\r
	87	\r
	88	@return 32-bit initial local APIC ID of the executing processor.\r
	89	**/\r
	90	UINT32\r
	91	EFIAPI\r
	92	GetInitialApicId (\r
	93	VOID\r
	94	);\r
	95	\r
	96	/**\r
	97	Get the local APIC ID of the executing processor.\r
	98	\r
	99	@return 32-bit local APIC ID of the executing processor.\r
	100	**/\r
	101	UINT32\r
	102	EFIAPI\r
	103	GetApicId (\r
	104	VOID\r
	105	);\r
	106	\r
	107	/**\r
	108	Get the value of the local APIC version register.\r
	109	\r
	110	@return the value of the local APIC version register.\r
	111	**/\r
	112	UINT32\r
	113	EFIAPI\r
	114	GetApicVersion (\r
	115	VOID\r
	116	);\r
	117	\r
	118	/**\r
	119	Send a Fixed IPI to a specified target processor.\r
	120	\r
	121	This function returns after the IPI has been accepted by the target processor. \r
	122	\r
	123	@param ApicId The local APIC ID of the target processor.\r
	124	@param Vector The vector number of the interrupt being sent.\r
	125	**/\r
	126	VOID\r
	127	EFIAPI\r
	128	SendFixedIpi (\r
	129	IN UINT32 ApicId,\r
	130	IN UINT8 Vector\r
	131	);\r
	132	\r
	133	/**\r
	134	Send a Fixed IPI to all processors excluding self.\r
	135	\r
	136	This function returns after the IPI has been accepted by the target processors. \r
	137	\r
	138	@param Vector The vector number of the interrupt being sent.\r
	139	**/\r
	140	VOID\r
	141	EFIAPI\r
	142	SendFixedIpiAllExcludingSelf (\r
	143	IN UINT8 Vector\r
	144	);\r
	145	\r
	146	/**\r
	147	Send a SMI IPI to a specified target processor.\r
	148	\r
	149	This function returns after the IPI has been accepted by the target processor. \r
	150	\r
	151	@param ApicId Specify the local APIC ID of the target processor.\r
	152	**/\r
	153	VOID\r
	154	EFIAPI\r
	155	SendSmiIpi (\r
	156	IN UINT32 ApicId\r
	157	);\r
	158	\r
	159	/**\r
	160	Send a SMI IPI to all processors excluding self.\r
	161	\r
	162	This function returns after the IPI has been accepted by the target processors. \r
	163	**/\r
	164	VOID\r
	165	EFIAPI\r
	166	SendSmiIpiAllExcludingSelf (\r
	167	VOID\r
	168	);\r
	169	\r
	170	/**\r
	171	Send an INIT IPI to a specified target processor.\r
	172	\r
	173	This function returns after the IPI has been accepted by the target processor. \r
	174	\r
	175	@param ApicId Specify the local APIC ID of the target processor.\r
	176	**/\r
	177	VOID\r
	178	EFIAPI\r
	179	SendInitIpi (\r
	180	IN UINT32 ApicId\r
	181	);\r
	182	\r
	183	/**\r
	184	Send an INIT IPI to all processors excluding self.\r
	185	\r
	186	This function returns after the IPI has been accepted by the target processors. \r
	187	**/\r
	188	VOID\r
	189	EFIAPI\r
	190	SendInitIpiAllExcludingSelf (\r
	191	VOID\r
	192	);\r
	193	\r
	194	/**\r
	195	Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.\r
	196	\r
	197	This function returns after the IPI has been accepted by the target processor. \r
	198	\r
	199	if StartupRoutine >= 1M, then ASSERT.\r
	200	if StartupRoutine is not multiple of 4K, then ASSERT.\r
	201	\r
	202	@param ApicId Specify the local APIC ID of the target processor.\r
	203	@param StartupRoutine Points to a start-up routine which is below 1M physical\r
	204	address and 4K aligned.\r
	205	**/\r
	206	VOID\r
	207	EFIAPI\r
	208	SendInitSipiSipi (\r
	209	IN UINT32 ApicId,\r
	210	IN UINT32 StartupRoutine\r
	211	);\r
	212	\r
	213	/**\r
	214	Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.\r
	215	\r
	216	This function returns after the IPI has been accepted by the target processors. \r
	217	\r
	218	if StartupRoutine >= 1M, then ASSERT.\r
	219	if StartupRoutine is not multiple of 4K, then ASSERT.\r
	220	\r
	221	@param StartupRoutine Points to a start-up routine which is below 1M physical\r
	222	address and 4K aligned.\r
	223	**/\r
	224	VOID\r
	225	EFIAPI\r
	226	SendInitSipiSipiAllExcludingSelf (\r
	227	IN UINT32 StartupRoutine\r
	228	);\r
	229	\r
	230	/**\r
	231	Initialize the state of the SoftwareEnable bit in the Local APIC\r
	232	Spurious Interrupt Vector register.\r
	233	\r
	234	@param Enable If TRUE, then set SoftwareEnable to 1\r
	235	If FALSE, then set SoftwareEnable to 0.\r
	236	\r
	237	**/\r
	238	VOID\r
	239	EFIAPI\r
	240	InitializeLocalApicSoftwareEnable (\r
	241	IN BOOLEAN Enable\r
	242	);\r
	243	\r
	244	/**\r
	245	Programming Virtual Wire Mode.\r
	246	\r
	247	This function programs the local APIC for virtual wire mode following\r
	248	the example described in chapter A.3 of the MP 1.4 spec.\r
	249	\r
	250	IOxAPIC is not involved in this type of virtual wire mode.\r
	251	**/\r
	252	VOID\r
	253	EFIAPI\r
	254	ProgramVirtualWireMode (\r
	255	VOID\r
	256	);\r
	257	\r
	258	/**\r
	259	Disable LINT0 & LINT1 interrupts.\r
	260	\r
	261	This function sets the mask flag in the LVT LINT0 & LINT1 registers.\r
	262	**/\r
	263	VOID\r
	264	EFIAPI\r
	265	DisableLvtInterrupts (\r
	266	VOID\r
	267	);\r
	268	\r
	269	/**\r
	270	Read the initial count value from the init-count register.\r
	271	\r
	272	@return The initial count value read from the init-count register.\r
	273	**/\r
	274	UINT32\r
	275	EFIAPI\r
	276	GetApicTimerInitCount (\r
	277	VOID\r
	278	);\r
	279	\r
	280	/**\r
	281	Read the current count value from the current-count register.\r
	282	\r
	283	@return The current count value read from the current-count register.\r
	284	**/\r
	285	UINT32\r
	286	EFIAPI\r
	287	GetApicTimerCurrentCount (\r
	288	VOID\r
	289	);\r
	290	\r
	291	/**\r
	292	Initialize the local APIC timer.\r
	293	\r
	294	The local APIC timer is initialized and enabled.\r
	295	\r
	296	@param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r
	297	If it is 0, then use the current divide value in the DCR.\r
	298	@param InitCount The initial count value.\r
	299	@param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r
	300	@param Vector The timer interrupt vector number.\r
	301	**/\r
	302	VOID\r
	303	EFIAPI\r
	304	InitializeApicTimer (\r
	305	IN UINTN DivideValue,\r
	306	IN UINT32 InitCount,\r
	307	IN BOOLEAN PeriodicMode,\r
	308	IN UINT8 Vector\r
	309	);\r
	310	\r
	311	/**\r
	312	Get the state of the local APIC timer.\r
	313	\r
	314	@param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r
	315	@param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r
	316	@param Vector Return the timer interrupt vector number.\r
	317	**/\r
	318	VOID\r
	319	EFIAPI\r
	320	GetApicTimerState (\r
	321	OUT UINTN *DivideValue OPTIONAL,\r
	322	OUT BOOLEAN *PeriodicMode OPTIONAL,\r
	323	OUT UINT8 *Vector OPTIONAL\r
	324	);\r
	325	\r
	326	/**\r
	327	Enable the local APIC timer interrupt.\r
	328	**/\r
	329	VOID\r
	330	EFIAPI\r
	331	EnableApicTimerInterrupt (\r
	332	VOID\r
	333	);\r
	334	\r
	335	/**\r
	336	Disable the local APIC timer interrupt.\r
	337	**/\r
	338	VOID\r
	339	EFIAPI\r
	340	DisableApicTimerInterrupt (\r
	341	VOID\r
	342	);\r
	343	\r
	344	/**\r
	345	Get the local APIC timer interrupt state.\r
	346	\r
	347	@retval TRUE The local APIC timer interrupt is enabled.\r
	348	@retval FALSE The local APIC timer interrupt is disabled.\r
	349	**/\r
	350	BOOLEAN\r
	351	EFIAPI\r
	352	GetApicTimerInterruptState (\r
	353	VOID\r
	354	);\r
	355	\r
	356	/**\r
	357	Send EOI to the local APIC.\r
	358	**/\r
	359	VOID\r
	360	EFIAPI\r
	361	SendApicEoi (\r
	362	VOID\r
	363	);\r
	364	\r
	365	/**\r
	366	Get the 32-bit address that a device should use to send a Message Signaled \r
	367	Interrupt (MSI) to the Local APIC of the currently executing processor.\r
	368	\r
	369	@return 32-bit address used to send an MSI to the Local APIC.\r
	370	**/\r
	371	UINT32\r
	372	EFIAPI \r
	373	GetApicMsiAddress (\r
	374	VOID\r
	375	);\r
	376	\r
	377	/**\r
	378	Get the 64-bit data value that a device should use to send a Message Signaled \r
	379	Interrupt (MSI) to the Local APIC of the currently executing processor.\r
	380	\r
	381	If Vector is not in range 0x10..0xFE, then ASSERT().\r
	382	If DeliveryMode is not supported, then ASSERT().\r
	383	\r
	384	@param Vector The 8-bit interrupt vector associated with the MSI. \r
	385	Must be in the range 0x10..0xFE\r
	386	@param DeliveryMode A 3-bit value that specifies how the recept of the MSI \r
	387	is handled. The only supported values are:\r
	388	0: LOCAL_APIC_DELIVERY_MODE_FIXED\r
	389	1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r
	390	2: LOCAL_APIC_DELIVERY_MODE_SMI\r
	391	4: LOCAL_APIC_DELIVERY_MODE_NMI\r
	392	5: LOCAL_APIC_DELIVERY_MODE_INIT\r
	393	7: LOCAL_APIC_DELIVERY_MODE_EXTINT\r
	394	\r
	395	@param LevelTriggered TRUE specifies a level triggered interrupt. \r
	396	FALSE specifies an edge triggered interrupt.\r
	397	@param AssertionLevel Ignored if LevelTriggered is FALSE.\r
	398	TRUE specifies a level triggered interrupt that active \r
	399	when the interrupt line is asserted.\r
	400	FALSE specifies a level triggered interrupt that active \r
	401	when the interrupt line is deasserted.\r
	402	\r
	403	@return 64-bit data value used to send an MSI to the Local APIC.\r
	404	**/\r
	405	UINT64\r
	406	EFIAPI \r
	407	GetApicMsiValue (\r
	408	IN UINT8 Vector,\r
	409	IN UINTN DeliveryMode,\r
	410	IN BOOLEAN LevelTriggered,\r
	411	IN BOOLEAN AssertionLevel\r
	412	);\r
	413	\r
	414	/**\r
	415	Get Package ID/Core ID/Thread ID of a processor.\r
	416	\r
	417	The algorithm assumes the target system has symmetry across physical\r
	418	package boundaries with respect to the number of logical processors\r
	419	per package, number of cores per package.\r
	420	\r
	421	@param[in] InitialApicId Initial APIC ID of the target logical processor.\r
	422	@param[out] Package Returns the processor package ID.\r
	423	@param[out] Core Returns the processor core ID.\r
	424	@param[out] Thread Returns the processor thread ID.\r
	425	**/\r
	426	VOID\r
	427	GetProcessorLocation(\r
	428	IN UINT32 InitialApicId,\r
	429	OUT UINT32 *Package OPTIONAL,\r
	430	OUT UINT32 *Core OPTIONAL,\r
	431	OUT UINT32 *Thread OPTIONAL\r
	432	);\r
	433	\r
	434	#endif\r
	435	\r