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1 | \r | |
2 | /*++\r | |
3 | \r | |
4 | Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r | |
5 | \r | |
6 | This program and the accompanying materials are licensed and made available under\r | |
7 | the terms and conditions of the BSD License that accompanies this distribution.\r | |
8 | The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php.\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | \r | |
15 | \r | |
16 | Module Name:\r | |
17 | \r | |
18 | vlvAccess.h\r | |
19 | \r | |
20 | Abstract:\r | |
21 | \r | |
22 | Macros to simplify and abstract the interface to PCI configuration.\r | |
23 | \r | |
24 | --*/\r | |
25 | \r | |
26 | #ifndef _VLVACCESS_H_INCLUDED_\r | |
27 | #define _VLVACCESS_H_INCLUDED_\r | |
28 | \r | |
29 | #include "Valleyview.h"\r | |
30 | #include "VlvCommonDefinitions.h"\r | |
31 | #include <Library/IoLib.h>\r | |
32 | \r | |
33 | //\r | |
34 | // Memory Mapped IO access macros used by MSG BUS LIBRARY\r | |
35 | //\r | |
36 | #define MmioAddress( BaseAddr, Register ) \\r | |
37 | ( (UINTN)BaseAddr + \\r | |
38 | (UINTN)(Register) \\r | |
39 | )\r | |
40 | \r | |
41 | \r | |
42 | //\r | |
43 | // UINT32\r | |
44 | //\r | |
45 | \r | |
46 | #define Mmio32Ptr( BaseAddr, Register ) \\r | |
47 | ( (volatile UINT32 *)MmioAddress( BaseAddr, Register ) )\r | |
48 | \r | |
49 | #define Mmio32( BaseAddr, Register ) \\r | |
50 | *Mmio32Ptr( BaseAddr, Register )\r | |
51 | \r | |
52 | #define Mmio32Or( BaseAddr, Register, OrData ) \\r | |
53 | Mmio32( BaseAddr, Register ) = \\r | |
54 | (UINT32) ( \\r | |
55 | Mmio32( BaseAddr, Register ) | \\r | |
56 | (UINT32)(OrData) \\r | |
57 | )\r | |
58 | \r | |
59 | #define Mmio32And( BaseAddr, Register, AndData ) \\r | |
60 | Mmio32( BaseAddr, Register ) = \\r | |
61 | (UINT32) ( \\r | |
62 | Mmio32( BaseAddr, Register ) & \\r | |
63 | (UINT32)(AndData) \\r | |
64 | )\r | |
65 | \r | |
66 | #define Mmio32AndThenOr( BaseAddr, Register, AndData, OrData ) \\r | |
67 | Mmio32( BaseAddr, Register ) = \\r | |
68 | (UINT32) ( \\r | |
69 | ( Mmio32( BaseAddr, Register ) & \\r | |
70 | (UINT32)(AndData) \\r | |
71 | ) | \\r | |
72 | (UINT32)(OrData) \\r | |
73 | )\r | |
74 | \r | |
75 | //\r | |
76 | // UINT16\r | |
77 | //\r | |
78 | \r | |
79 | #define Mmio16Ptr( BaseAddr, Register ) \\r | |
80 | ( (volatile UINT16 *)MmioAddress( BaseAddr, Register ) )\r | |
81 | \r | |
82 | #define Mmio16( BaseAddr, Register ) \\r | |
83 | *Mmio16Ptr( BaseAddr, Register )\r | |
84 | \r | |
85 | #define Mmio16Or( BaseAddr, Register, OrData ) \\r | |
86 | Mmio16( BaseAddr, Register ) = \\r | |
87 | (UINT16) ( \\r | |
88 | Mmio16( BaseAddr, Register ) | \\r | |
89 | (UINT16)(OrData) \\r | |
90 | )\r | |
91 | \r | |
92 | #define Mmio16And( BaseAddr, Register, AndData ) \\r | |
93 | Mmio16( BaseAddr, Register ) = \\r | |
94 | (UINT16) ( \\r | |
95 | Mmio16( BaseAddr, Register ) & \\r | |
96 | (UINT16)(AndData) \\r | |
97 | )\r | |
98 | \r | |
99 | #define Mmio16AndThenOr( BaseAddr, Register, AndData, OrData ) \\r | |
100 | Mmio16( BaseAddr, Register ) = \\r | |
101 | (UINT16) ( \\r | |
102 | ( Mmio16( BaseAddr, Register ) & \\r | |
103 | (UINT16)(AndData) \\r | |
104 | ) | \\r | |
105 | (UINT16)(OrData) \\r | |
106 | )\r | |
107 | \r | |
108 | //\r | |
109 | // UINT8\r | |
110 | //\r | |
111 | \r | |
112 | #define Mmio8Ptr( BaseAddr, Register ) \\r | |
113 | ( (volatile UINT8 *)MmioAddress( BaseAddr, Register ) )\r | |
114 | \r | |
115 | #define Mmio8( BaseAddr, Register ) \\r | |
116 | *Mmio8Ptr( BaseAddr, Register )\r | |
117 | \r | |
118 | #define Mmio8Or( BaseAddr, Register, OrData ) \\r | |
119 | Mmio8( BaseAddr, Register ) = \\r | |
120 | (UINT8) ( \\r | |
121 | Mmio8( BaseAddr, Register ) | \\r | |
122 | (UINT8)(OrData) \\r | |
123 | )\r | |
124 | \r | |
125 | #define Mmio8And( BaseAddr, Register, AndData ) \\r | |
126 | Mmio8( BaseAddr, Register ) = \\r | |
127 | (UINT8) ( \\r | |
128 | Mmio8( BaseAddr, Register ) & \\r | |
129 | (UINT8)(AndData) \\r | |
130 | )\r | |
131 | \r | |
132 | #define Mmio8AndThenOr( BaseAddr, Register, AndData, OrData ) \\r | |
133 | Mmio8( BaseAddr, Register ) = \\r | |
134 | (UINT8) ( \\r | |
135 | ( Mmio8( BaseAddr, Register ) & \\r | |
136 | (UINT8)(AndData) \\r | |
137 | ) | \\r | |
138 | (UINT8)(OrData) \\r | |
139 | )\r | |
140 | \r | |
141 | //\r | |
142 | // MSG BUS API\r | |
143 | //\r | |
144 | \r | |
145 | #define MSG_BUS_ENABLED 0x000000F0\r | |
146 | #define MSGBUS_MASKHI 0xFFFFFF00\r | |
147 | #define MSGBUS_MASKLO 0x000000FF\r | |
148 | \r | |
149 | #define MESSAGE_BYTE_EN BIT4\r | |
150 | #define MESSAGE_WORD_EN BIT4 | BIT5\r | |
151 | #define MESSAGE_DWORD_EN BIT4 | BIT5 | BIT6 | BIT7\r | |
152 | \r | |
153 | #define SIDEBAND_OPCODE 0x78\r | |
154 | #define MEMREAD_OPCODE 0x00000000\r | |
155 | #define MEMWRITE_OPCODE 0x01000000\r | |
156 | \r | |
157 | \r | |
158 | \r | |
159 | /***************************/\r | |
160 | //\r | |
161 | // Memory mapped PCI IO\r | |
162 | //\r | |
163 | \r | |
164 | #define PciCfgPtr(Bus, Device, Function, Register )\\r | |
165 | (UINTN)(Bus << 20) + \\r | |
166 | (UINTN)(Device << 15) + \\r | |
167 | (UINTN)(Function << 12) + \\r | |
168 | (UINTN)(Register)\r | |
169 | \r | |
170 | #define PciCfg32Read_CF8CFC(B,D,F,R) \\r | |
171 | (UINT32)(IoOut32(0xCF8,(0x80000000|(B<<16)|(D<<11)|(F<<8)|(R))),IoIn32(0xCFC))\r | |
172 | \r | |
173 | #define PciCfg32Write_CF8CFC(B,D,F,R,Data) \\r | |
174 | (IoOut32(0xCF8,(0x80000000|(B<<16)|(D<<11)|(F<<8)|(R))),IoOut32(0xCFC,Data))\r | |
175 | \r | |
176 | #define PciCfg32Or_CF8CFC(B,D,F,R,O) \\r | |
177 | PciCfg32Write_CF8CFC(B,D,F,R, \\r | |
178 | (PciCfg32Read_CF8CFC(B,D,F,R) | (O)))\r | |
179 | \r | |
180 | #define PciCfg32And_CF8CFC(B,D,F,R,A) \\r | |
181 | PciCfg32Write_CF8CFC(B,D,F,R, \\r | |
182 | (PciCfg32Read_CF8CFC(B,D,F,R) & (A)))\r | |
183 | \r | |
184 | #define PciCfg32AndThenOr_CF8CFC(B,D,F,R,A,O) \\r | |
185 | PciCfg32Write_CF8CFC(B,D,F,R, \\r | |
186 | (PciCfg32Read_CF8CFC(B,D,F,R) & (A)) | (O))\r | |
187 | \r | |
188 | //\r | |
189 | // Device 0, Function 0\r | |
190 | //\r | |
191 | #define McD0PciCfg64(Register) MmPci64 (0, MC_BUS, 0, 0, Register)\r | |
192 | #define McD0PciCfg64Or(Register, OrData) MmPci64Or (0, MC_BUS, 0, 0, Register, OrData)\r | |
193 | #define McD0PciCfg64And(Register, AndData) MmPci64And (0, MC_BUS, 0, 0, Register, AndData)\r | |
194 | #define McD0PciCfg64AndThenOr(Register, AndData, OrData) MmPci64AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)\r | |
195 | \r | |
196 | #define McD0PciCfg32(Register) MmPci32 (0, MC_BUS, 0, 0, Register)\r | |
197 | #define McD0PciCfg32Or(Register, OrData) MmPci32Or (0, MC_BUS, 0, 0, Register, OrData)\r | |
198 | #define McD0PciCfg32And(Register, AndData) MmPci32And (0, MC_BUS, 0, 0, Register, AndData)\r | |
199 | #define McD0PciCfg32AndThenOr(Register, AndData, OrData) MmPci32AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)\r | |
200 | \r | |
201 | #define McD0PciCfg16(Register) MmPci16 (0, MC_BUS, 0, 0, Register)\r | |
202 | #define McD0PciCfg16Or(Register, OrData) MmPci16Or (0, MC_BUS, 0, 0, Register, OrData)\r | |
203 | #define McD0PciCfg16And(Register, AndData) MmPci16And (0, MC_BUS, 0, 0, Register, AndData)\r | |
204 | #define McD0PciCfg16AndThenOr(Register, AndData, OrData) MmPci16AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)\r | |
205 | \r | |
206 | #define McD0PciCfg8(Register) MmPci8 (0, MC_BUS, 0, 0, Register)\r | |
207 | #define McD0PciCfg8Or(Register, OrData) MmPci8Or (0, MC_BUS, 0, 0, Register, OrData)\r | |
208 | #define McD0PciCfg8And(Register, AndData) MmPci8And (0, MC_BUS, 0, 0, Register, AndData)\r | |
209 | #define McD0PciCfg8AndThenOr( Register, AndData, OrData ) MmPci8AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)\r | |
210 | \r | |
211 | \r | |
212 | //\r | |
213 | // Device 2, Function 0\r | |
214 | //\r | |
215 | #define McD2PciCfg64(Register) MmPci64 (0, MC_BUS, 2, 0, Register)\r | |
216 | #define McD2PciCfg64Or(Register, OrData) MmPci64Or (0, MC_BUS, 2, 0, Register, OrData)\r | |
217 | #define McD2PciCfg64And(Register, AndData) MmPci64And (0, MC_BUS, 2, 0, Register, AndData)\r | |
218 | #define McD2PciCfg64AndThenOr(Register, AndData, OrData) MmPci64AndThenOr (0, MC_BUS, 2, 0, Register, AndData, OrData)\r | |
219 | \r | |
220 | #define McD2PciCfg32(Register) MmPci32 (0, MC_BUS, 2, 0, Register)\r | |
221 | #define McD2PciCfg32Or(Register, OrData) MmPci32Or (0, MC_BUS, 2, 0, Register, OrData)\r | |
222 | #define McD2PciCfg32And(Register, AndData) MmPci32And (0, MC_BUS, 2, 0, Register, AndData)\r | |
223 | #define McD2PciCfg32AndThenOr(Register, AndData, OrData) MmPci32AndThenOr (0, MC_BUS, 2, 0, Register, AndData, OrData)\r | |
224 | \r | |
225 | #define McD2PciCfg16(Register) MmPci16 (0, MC_BUS, 2, 0, Register)\r | |
226 | #define McD2PciCfg16Or(Register, OrData) MmPci16Or (0, MC_BUS, 2, 0, Register, OrData)\r | |
227 | #define McD2PciCfg16And(Register, AndData) MmPci16And (0, MC_BUS, 2, 0, Register, AndData)\r | |
228 | #define McD2PciCfg16AndThenOr(Register, AndData, OrData) MmPci16AndThenOr (0, MC_BUS, 2, 0, Register, AndData, OrData)\r | |
229 | \r | |
230 | #define McD2PciCfg8(Register) MmPci8 (0, MC_BUS, 2, 0, Register)\r | |
231 | #define McD2PciCfg8Or(Register, OrData) MmPci8Or (0, MC_BUS, 2, 0, Register, OrData)\r | |
232 | #define McD2PciCfg8And(Register, AndData) MmPci8And (0, MC_BUS, 2, 0, Register, AndData)\r | |
233 | \r | |
234 | //\r | |
235 | // IO\r | |
236 | //\r | |
237 | \r | |
238 | #ifndef IoIn8\r | |
239 | \r | |
240 | #define IoIn8(Port) \\r | |
241 | IoRead8(Port)\r | |
242 | \r | |
243 | #define IoIn16(Port) \\r | |
244 | IoRead16(Port)\r | |
245 | \r | |
246 | #define IoIn32(Port) \\r | |
247 | IoRead32(Port)\r | |
248 | \r | |
249 | #define IoOut8(Port, Data) \\r | |
250 | IoWrite8(Port, Data)\r | |
251 | \r | |
252 | #define IoOut16(Port, Data) \\r | |
253 | IoWrite16(Port, Data)\r | |
254 | \r | |
255 | #define IoOut32(Port, Data) \\r | |
256 | IoWrite32(Port, Data)\r | |
257 | \r | |
258 | #endif\r | |
259 | \r | |
260 | #endif\r |