ArmEbPkg/Include/ArmEb/ArmEb.h

   1 /*++
   2
   3 Copyright (c) 2010, Apple Inc. All rights reserved.<BR>
   4 This program and the accompanying materials
   5 are licensed and made available under the terms and conditions of the BSD License
   6 which accompanies this distribution.  The full text of the license may be found at
   7 http://opensource.org/licenses/bsd-license.php
   8
   9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11
  12 --*/
  13
  14 #ifndef __ARM_EB_H__
  15 #define __ARM_EB_H__
  16
  17 #include <ArmEb/ArmEbUart.h>
  18 #include <ArmEb/ArmEbTimer.h>
  19
  20 ///
  21 /// ARM EB Memory Map
  22 ///
  23 // 0x00000000 - 0x0FFFFFFF SDRAM 256MB
  24 // 0x10000000 - 0x100FFFFF System FPGA (config registers) 1MB
  25 //   0x10000000\960x10000FFF  4KB    System registers
  26 //   0x10001000\960x10001FFF  4KB    System controller
  27 //   0x10002000\960x10002FFF  4KB    Two-Wire Serial Bus Interface
  28 //   0x10003000\960x10003FFF  4KB    Reserved
  29 //   0x10004000\960x10004FFF  4KB    Advanced Audio CODEC Interface
  30 //   0x10005000\960x10005FFF  4KB    MultiMedia Card Interface (MCI)
  31 //   0x10006000\960x10006FFF  4KB    Keyboard/Mouse Interface 0
  32 //   0x10007000\960x10007FFF  4KB    Keyboard/Mouse Interface 1
  33 //   0x10008000\960x10008FFF  4KB    Character LCD Interface
  34 //   0x10009000\960x10009FFF  4KB    UART 0 Interface
  35 //   0x1000A000\960x1000AFFF  4KB    UART 1 Interface
  36 //   0x1000B000\960x1000BFFF  4KB    UART 2 Interface
  37 //   0x1000C000\960x1000CFFF  4KB    UART 3 Interface
  38 //   0x1000D000\960x1000DFFF  4KB    Synchronous Serial Port Interface
  39 //   0x1000E000\960x1000EFFF  4KB    Smart Card Interface
  40 //   0x1000F000\960x1000FFFF  4KB    Reserved
  41 //   0x10010000\960x10010FFF  4KB    Watchdog Interface
  42 //   0x10011000\960x10011FFF  4KB    Timer modules 0 and 1 interface (Timer 1 starts at 0x10011020)
  43 //   0x10012000\960x10012FFF  4KB    Timer modules 2 and 3 interface (Timer 3 starts at 0x10012020)
  44 //   0x10013000\960x10013FFF  4KB    GPIO Interface 0
  45 //   0x10014000\960x10014FFF  4KB    GPIO Interface 1
  46 //   0x10015000\960x10015FFF  4KB    GPIO Interface 2 (miscellaneous onboard I/O)
  47 //   0x10016000\960x10016FFF  4KB    Reserved
  48 //   0x10017000\960x10017FFF  4KB    Real Time Clock Interface
  49 //   0x10018000\960x10018FFF  4KB    Dynamic Memory Controller configuration
  50 //   0x10019000\960x10019FFF  4KB    PCI controller configuration registers
  51 //   0x1001A000\960x1001FFFF  24KB   Reserved
  52 //   0x10020000\960x1002FFFF  64KB   Color LCD Controller
  53 //   0x10030000\960x1003FFFF  64KB   DMA Controller configuration registers
  54 //   0x10040000\960x1004FFFF  64KB   Generic Interrupt Controller 1 (nIRQ for tile 1)
  55 //   0x10050000\960x1005FFFF  64KB   Generic Interrupt Controller 2 (nFIQ for tile 1)
  56 //   0x10060000\960x1006FFFF  64KB   Generic Interrupt Controller 3 (nIRQ for tile 2)
  57 //   0x10070000\960x1007FFFF  64KB   Generic Interrupt Controller 4 (nFIQ for tile 2)
  58 //   0x10080000\960x1008FFFF  64KB   Static Memory Controller configuration registers
  59 //   0x100A0000\960x100EFFFF  448MB  Reserved
  60 //   0x10090000\960x100FFFFF  64KB   Debug Access Port (DAP)
  61 // 0x10100000 - 0x100FFFFF Reserved 3MB
  62 // 0x10400000 - 0x17FFFFFF System FPGA 124MB
  63 // 0x18000000 - 0x1FFFFFFF Logic Tile 1 128MB
  64 // 0x20000000 - 0x3FFFFFFF Reserved 512MB
  65 // 0x40000000 - 0x7FFFFFFF System FPGA 1GB
  66 //   0x40000000\960x43FFFFFF   CS0 NOR flash (nNOR_CS1)
  67 //   0x44000000\960x47FFFFFF   CS1 NOR flash (nNOR_CS2)
  68 //   0x48000000\960x4BFFFFFF   CS2 SRAM (nSRAMCS)
  69 //   0x4C000000\960x4DFFFFFF   CS3 Config flash
  70 //   0x4E000000\960x4EFFFFFF   Ethernet
  71 //   0x4F000000\960x4FFFFFFF   USB
  72 //   0x50000000\960x53FFFFFF   CS4 (nEXPCS) PISMO (nCS0)
  73 //   0x54000000\960x57FFFFFF   CS5 (nSTATICCS4) PISMO (nCS1)
  74 //   0x58000000\960x5BFFFFFF   CS6 (nSTATICCS5) PISMO (nCS2)
  75 //   0x5C000000\960x5FFFFFFF   CS7 (nSTATICCS6) PISMO (nCS3)
  76 //   0x61000000\960x61FFFFFF   PCI SelfCfg window
  77 //   0x62000000\960x62FFFFFF   PCI Cfg window
  78 //   0x63000000\960x63FFFFFF   PCI I/O window
  79 //   0x64000000\960x67FFFFFF   PCI memory window 0
  80 //   0x68000000\960x6BFFFFFF   PCI memory window 1
  81 //   0x6C000000\960x6FFFFFFF   PCI memory window 2
  82 //   0x70000000 - 0x7FFFFFFF   DRAM Mirror
  83 // 0x80000000 - 0xFFFFFFFF Logic Tile site 2 2GB
  84
  85 //
  86 // At reset EB_DRAM_BASE is alaised to EB_CS0_NOR_BASE
  87 //
  88 #define EB_DRAM_BASE          0x00000000   // 256 MB DRAM
  89 #define EB_CONFIG_BASE        0x10000000
  90
  91 #define EB_CSO_NOR_BASE       0x40000000   // 64 MB NOR FLASH
  92 #define EB_CS1_NOR_BASE       0x44000000   // 64 MB NOR FLASH
  93 #define EB_CS2_SRAM           0x48000000   //  2 MB of SRAM
  94 #define EB_CS3_CONFIG_FLASH   0x4c000000   //  8 MB Config FLASH for FPGA. Not to be used by application code
  95 #define EB_CS3_ETHERNET       0x4e000000   // 16 MB Ethernet controller
  96 #define EB_CS4_PISMO_CS0      0x50000000   // Expansion  CS0
  97 #define EB_CS5_PISMO_CS0      0x54000000   // Expansion  CS0
  98 #define EB_CS6_PISMO_CS0      0x58000000   // Expansion  CS0
  99
 100 #define EB_DRAM_REMAP_BASE    0x70000000   // if REMAPSTAT is HIGH alais of EB_DRAM_BASE
 101
 102 #endif