ArmPkg/ArmPkg.dec

   1 #/** @file
   2 # ARM processor package.
   3 #
   4 # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
   5 # Copyright (c) 2011 - 2018, ARM Limited. All rights reserved.
   6 #
   7 #    This program and the accompanying materials
   8 #    are licensed and made available under the terms and conditions of the BSD License
   9 #    which accompanies this distribution. The full text of the license may be found at
  10 #    http://opensource.org/licenses/bsd-license.php
  11 #
  12 #    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13 #    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14 #
  15 #**/
  16
  17 [Defines]
  18   DEC_SPECIFICATION              = 0x00010005
  19   PACKAGE_NAME                   = ArmPkg
  20   PACKAGE_GUID                   = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F
  21   PACKAGE_VERSION                = 0.1
  22
  23 ################################################################################
  24 #
  25 # Include Section - list of Include Paths that are provided by this package.
  26 #                   Comments are used for Keywords and Module Types.
  27 #
  28 # Supported Module Types:
  29 #  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
  30 #
  31 ################################################################################
  32 [Includes.common]
  33   Include                        # Root include for the package
  34
  35 [LibraryClasses.common]
  36   ArmLib|Include/Library/ArmLib.h
  37   ArmMmuLib|Include/Library/ArmMmuLib.h
  38   SemihostLib|Include/Library/Semihosting.h
  39   DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h
  40   ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h
  41   ArmGicArchLib|Include/Library/ArmGicArchLib.h
  42   ArmMtlLib|ArmPlatformPkg/Include/Library/ArmMtlLib.h
  43   ArmSvcLib|Include/Library/ArmSvcLib.h
  44   OpteeLib|Include/Library/OpteeLib.h
  45   StandaloneMmMmuLib|Include/Library/StandaloneMmMmuLib.h
  46
  47 [Guids.common]
  48   gArmTokenSpaceGuid       = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }
  49
  50   ## ARM MPCore table
  51   # Include/Guid/ArmMpCoreInfo.h
  52   gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5,  {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }
  53
  54 [Protocols.common]
  55   ## Arm System Control and Management Interface(SCMI) Base protocol
  56   ## ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h
  57   gArmScmiBaseProtocolGuid = { 0xd7e5abe9, 0x33ab, 0x418e, { 0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f } }
  58
  59   ## Arm System Control and Management Interface(SCMI) Clock management protocol
  60   ## ArmPkg/Include/Protocol/ArmScmiClockProtocol.h
  61   gArmScmiClockProtocolGuid = { 0x91ce67a8, 0xe0aa, 0x4012, { 0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa } }
  62
  63   ## Arm System Control and Management Interface(SCMI) Clock management protocol
  64   ## ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h
  65   gArmScmiPerformanceProtocolGuid = { 0x9b8ba84, 0x3dd3, 0x49a6, { 0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad } }
  66
  67 [Ppis]
  68   ## Include/Ppi/ArmMpCoreInfo.h
  69   gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }
  70
  71 [PcdsFeatureFlag.common]
  72   gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001
  73
  74   # On ARM Architecture with the Security Extension, the address for the
  75   # Vector Table can be mapped anywhere in the memory map. It means we can
  76   # point the Exception Vector Table to its location in CpuDxe.
  77   # By default we copy the Vector Table at  PcdGet64(PcdCpuVectorBaseAddress)
  78   gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022
  79   # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before
  80   # it has been configured by the CPU DXE
  81   gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032
  82
  83   # Define if the GICv3 controller should use the GICv2 legacy
  84   gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042
  85
  86   # Whether to implement warm reboot for capsule update using a jump back to the
  87   # PEI entry point with caches and interrupts disabled.
  88   gArmTokenSpaceGuid.PcdArmReenterPeiForCapsuleWarmReboot|FALSE|BOOLEAN|0x0000001F
  89
  90 [PcdsFeatureFlag.ARM]
  91   # Whether to map normal memory as non-shareable. FALSE is the safe choice, but
  92   # TRUE may be appropriate to fix performance problems if you don't care about
  93   # hardware coherency (i.e., no virtualization or cache coherent DMA)
  94   gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043
  95
  96 [PcdsFixedAtBuild.common]
  97   gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006
  98
  99   # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.
 100   # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
 101   gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024
 102
 103   gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004
 104   gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005
 105
 106   #
 107   # ARM Secure Firmware PCDs
 108   #
 109   gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015
 110   gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016
 111   gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F
 112   gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030
 113
 114   #
 115   # ARM Hypervisor Firmware PCDs
 116   #
 117   gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A
 118   gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B
 119   gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C
 120   gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D
 121
 122   # Use ClusterId + CoreId to identify the PrimaryCore
 123   gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031
 124   # The Primary Core is ClusterId[0] & CoreId[0]
 125   gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037
 126
 127   #
 128   # ARM L2x0 PCDs
 129   #
 130   gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B
 131
 132   #
 133   # ARM Normal (or Non Secure) Firmware PCDs
 134   #
 135   gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C
 136   gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E
 137
 138   #
 139   # Value to add to a host address to obtain a device address, using
 140   # unsigned 64-bit integer arithmetic on both ARM and AArch64. This
 141   # means we can rely on truncation on overflow to specify negative
 142   # offsets.
 143   #
 144   gArmTokenSpaceGuid.PcdArmDmaDeviceOffset|0x0|UINT64|0x0000044
 145
 146 [PcdsFixedAtBuild.common, PcdsPatchableInModule.common]
 147   gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B
 148   gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D
 149
 150 [PcdsFixedAtBuild.ARM]
 151   #
 152   # ARM Security Extension
 153   #
 154
 155   # Secure Configuration Register
 156   # - BIT0 : NS - Non Secure bit
 157   # - BIT1 : IRQ Handler
 158   # - BIT2 : FIQ Handler
 159   # - BIT3 : EA - External Abort
 160   # - BIT4 : FW - F bit writable
 161   # - BIT5 : AW - A bit writable
 162   # - BIT6 : nET - Not Early Termination
 163   # - BIT7 : SCD - Secure Monitor Call Disable
 164   # - BIT8 : HCE - Hyp Call enable
 165   # - BIT9 : SIF - Secure Instruction Fetch
 166   # 0x31 = NS | EA | FW
 167   gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038
 168
 169   # By default we do not do a transition to non-secure mode
 170   gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E
 171
 172   # Non Secure Access Control Register
 173   # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality
 174   # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31
 175   # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable
 176   # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable
 177   # 0xC00 = cp10 | cp11
 178   gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039
 179
 180 [PcdsFixedAtBuild.AARCH64]
 181   #
 182   # AArch64 Security Extension
 183   #
 184
 185   # Secure Configuration Register
 186   # - BIT0 : NS - Non Secure bit
 187   # - BIT1 : IRQ Handler
 188   # - BIT2 : FIQ Handler
 189   # - BIT3 : EA - External Abort
 190   # - BIT4 : FW - F bit writable
 191   # - BIT5 : AW - A bit writable
 192   # - BIT6 : nET - Not Early Termination
 193   # - BIT7 : SCD - Secure Monitor Call Disable
 194   # - BIT8 : HCE - Hyp Call enable
 195   # - BIT9 : SIF - Secure Instruction Fetch
 196   # - BIT10: RW -  Register width control for lower exception levels
 197   # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer
 198   # - BIT12: TWI - Trap WFI
 199   # - BIT13: TWE - Trap WFE
 200   # 0x501 = NS | HCE | RW
 201   gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038
 202
 203   # By default we do transition to EL2 non-secure mode with Stack for EL2.
 204   #        Mode Description              Bits
 205   # NS EL2 SP2 all interrupts disabled =  0x3c9
 206   # NS EL1 SP1 all interrupts disabled =  0x3c5
 207   # Other modes include using SP0 or switching to Aarch32, but these are
 208   # not currently supported.
 209   gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E
 210
 211
 212 #
 213 # These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be
 214 # redefined when using UEFI in a context of virtual machine.
 215 #
 216 [PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]
 217
 218   # System Memory (DRAM): These PCDs define the region of in-built system memory
 219   # Some platforms can get DRAM extensions, these additional regions may be
 220   # declared to UEFI using separate resource descriptor HOBs
 221   gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029
 222   gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A
 223
 224   gArmTokenSpaceGuid.PcdMmBufferBase|0|UINT64|0x00000045
 225   gArmTokenSpaceGuid.PcdMmBufferSize|0|UINT64|0x00000046
 226
 227 [PcdsFixedAtBuild.common, PcdsDynamic.common]
 228   #
 229   # ARM Architectural Timer
 230   #
 231   gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034
 232
 233   # ARM Architectural Timer Interrupt(GIC PPI) numbers
 234   gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035
 235   gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036
 236   gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040
 237   gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041
 238
 239   #
 240   # ARM Generic Watchdog
 241   #
 242
 243   gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT64|0x00000007
 244   gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT64|0x00000008
 245   gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009
 246
 247   #
 248   # ARM Generic Interrupt Controller
 249   #
 250   gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C
 251   # Base address for the GIC Redistributor region that contains the boot CPU
 252   gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E
 253   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D
 254   gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025
 255
 256   #
 257   # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.
 258   # Note that "IO" is just another MMIO range that simulates IO space; there
 259   # are no special instructions to access it.
 260   #
 261   # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are
 262   # specific to their containing address spaces. In order to get the physical
 263   # address for the CPU, for a given access, the respective translation value
 264   # has to be added.
 265   #
 266   # The translations always have to be initialized like this, using UINT64:
 267   #
 268   #   UINT64 IoCpuBase;     // mapping target in 64-bit cpu-physical space
 269   #   UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space
 270   #   UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space
 271   #
 272   #   PcdPciIoTranslation     = IoCpuBase     - PcdPciIoBase;
 273   #   PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;
 274   #   PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;
 275   #
 276   # because (a) the target address space (ie. the cpu-physical space) is
 277   # 64-bit, and (b) the translation values are meant as offsets for *modular*
 278   # arithmetic.
 279   #
 280   # Accordingly, the translation itself needs to be implemented as:
 281   #
 282   #   UINT64 UntranslatedIoAddress;     // input parameter
 283   #   UINT32 UntranslatedMmio32Address; // input parameter
 284   #   UINT64 UntranslatedMmio64Address; // input parameter
 285   #
 286   #   UINT64 TranslatedIoAddress;       // output parameter
 287   #   UINT64 TranslatedMmio32Address;   // output parameter
 288   #   UINT64 TranslatedMmio64Address;   // output parameter
 289   #
 290   #   TranslatedIoAddress     = UntranslatedIoAddress +
 291   #                             PcdPciIoTranslation;
 292   #   TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +
 293   #                             PcdPciMmio32Translation;
 294   #   TranslatedMmio64Address = UntranslatedMmio64Address +
 295   #                             PcdPciMmio64Translation;
 296   #
 297   #  The modular arithmetic performed in UINT64 ensures that the translation
 298   #  works correctly regardless of the relation between IoCpuBase and
 299   #  PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and
 300   #  PcdPciMmio64Base.
 301   #
 302   gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050
 303   gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051
 304   gArmTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000052
 305   gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053
 306   gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054
 307   gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000055
 308   gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056
 309   gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057
 310   gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000058
 311
 312   #
 313   # Inclusive range of allowed PCI buses.
 314   #
 315   gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059
 316   gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A