ArmPkg/ArmSmcPsciResetSystemLib: implement fallback for warm reboot
[mirror_edk2.git] / ArmPkg / ArmPkg.dec
1 #/** @file
2 # ARM processor package.
3 #
4 # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
5 # Copyright (c) 2011 - 2018, ARM Limited. All rights reserved.
6 #
7 # This program and the accompanying materials
8 # are licensed and made available under the terms and conditions of the BSD License
9 # which accompanies this distribution. The full text of the license may be found at
10 # http://opensource.org/licenses/bsd-license.php
11 #
12 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14 #
15 #**/
16
17 [Defines]
18 DEC_SPECIFICATION = 0x00010005
19 PACKAGE_NAME = ArmPkg
20 PACKAGE_GUID = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F
21 PACKAGE_VERSION = 0.1
22
23 ################################################################################
24 #
25 # Include Section - list of Include Paths that are provided by this package.
26 # Comments are used for Keywords and Module Types.
27 #
28 # Supported Module Types:
29 # BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
30 #
31 ################################################################################
32 [Includes.common]
33 Include # Root include for the package
34
35 [LibraryClasses.common]
36 ArmLib|Include/Library/ArmLib.h
37 ArmMmuLib|Include/Library/ArmMmuLib.h
38 SemihostLib|Include/Library/Semihosting.h
39 DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h
40 ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h
41 ArmGicArchLib|Include/Library/ArmGicArchLib.h
42 ArmMtlLib|ArmPlatformPkg/Include/Library/ArmMtlLib.h
43 ArmSvcLib|Include/Library/ArmSvcLib.h
44
45 [Guids.common]
46 gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }
47
48 ## ARM MPCore table
49 # Include/Guid/ArmMpCoreInfo.h
50 gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }
51
52 [Protocols.common]
53 ## Arm System Control and Management Interface(SCMI) Base protocol
54 ## ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h
55 gArmScmiBaseProtocolGuid = { 0xd7e5abe9, 0x33ab, 0x418e, { 0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f } }
56
57 ## Arm System Control and Management Interface(SCMI) Clock management protocol
58 ## ArmPkg/Include/Protocol/ArmScmiClockProtocol.h
59 gArmScmiClockProtocolGuid = { 0x91ce67a8, 0xe0aa, 0x4012, { 0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa } }
60
61 ## Arm System Control and Management Interface(SCMI) Clock management protocol
62 ## ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h
63 gArmScmiPerformanceProtocolGuid = { 0x9b8ba84, 0x3dd3, 0x49a6, { 0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad } }
64
65 [Ppis]
66 ## Include/Ppi/ArmMpCoreInfo.h
67 gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }
68
69 [PcdsFeatureFlag.common]
70 gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001
71
72 # On ARM Architecture with the Security Extension, the address for the
73 # Vector Table can be mapped anywhere in the memory map. It means we can
74 # point the Exception Vector Table to its location in CpuDxe.
75 # By default we copy the Vector Table at PcdGet64(PcdCpuVectorBaseAddress)
76 gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022
77 # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before
78 # it has been configured by the CPU DXE
79 gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032
80
81 # Define if the spin-table mechanism is used by the secondary cores when booting
82 # Linux (instead of PSCI)
83 gArmTokenSpaceGuid.PcdArmLinuxSpinTable|FALSE|BOOLEAN|0x00000033
84
85 # Define if the GICv3 controller should use the GICv2 legacy
86 gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042
87
88 # Whether to implement warm reboot for capsule update using a jump back to the
89 # PEI entry point with caches and interrupts disabled.
90 gArmTokenSpaceGuid.PcdArmReenterPeiForCapsuleWarmReboot|FALSE|BOOLEAN|0x0000001F
91
92 [PcdsFeatureFlag.ARM]
93 # Whether to map normal memory as non-shareable. FALSE is the safe choice, but
94 # TRUE may be appropriate to fix performance problems if you don't care about
95 # hardware coherency (i.e., no virtualization or cache coherent DMA)
96 gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043
97
98 [PcdsFixedAtBuild.common]
99 gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006
100
101 # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.
102 # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
103 gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024
104
105 gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004
106 gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005
107
108 #
109 # ARM Secure Firmware PCDs
110 #
111 gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015
112 gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016
113 gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F
114 gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030
115
116 #
117 # ARM Hypervisor Firmware PCDs
118 #
119 gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A
120 gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B
121 gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C
122 gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D
123
124 # Use ClusterId + CoreId to identify the PrimaryCore
125 gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031
126 # The Primary Core is ClusterId[0] & CoreId[0]
127 gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037
128
129 #
130 # ARM L2x0 PCDs
131 #
132 gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B
133
134 #
135 # ARM Normal (or Non Secure) Firmware PCDs
136 #
137 gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C
138 gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E
139
140 #
141 # Value to add to a host address to obtain a device address, using
142 # unsigned 64-bit integer arithmetic on both ARM and AArch64. This
143 # means we can rely on truncation on overflow to specify negative
144 # offsets.
145 #
146 gArmTokenSpaceGuid.PcdArmDmaDeviceOffset|0x0|UINT64|0x0000044
147
148 [PcdsFixedAtBuild.common, PcdsPatchableInModule.common]
149 gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B
150 gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D
151
152 [PcdsFixedAtBuild.ARM]
153 #
154 # ARM Security Extension
155 #
156
157 # Secure Configuration Register
158 # - BIT0 : NS - Non Secure bit
159 # - BIT1 : IRQ Handler
160 # - BIT2 : FIQ Handler
161 # - BIT3 : EA - External Abort
162 # - BIT4 : FW - F bit writable
163 # - BIT5 : AW - A bit writable
164 # - BIT6 : nET - Not Early Termination
165 # - BIT7 : SCD - Secure Monitor Call Disable
166 # - BIT8 : HCE - Hyp Call enable
167 # - BIT9 : SIF - Secure Instruction Fetch
168 # 0x31 = NS | EA | FW
169 gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038
170
171 # By default we do not do a transition to non-secure mode
172 gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E
173
174 # The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory
175 gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset|0x4000|UINT32|0x00000020
176
177 # If the fixed FDT address is not available, then it should be loaded below the kernel.
178 # The recommendation from the Linux kernel is to have the FDT below 16KB.
179 # (see the kernel doc: Documentation/arm/Booting)
180 gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x4000|UINT32|0x00000023
181 # The FDT blob must be loaded at a 64bit aligned address.
182 gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x8|UINT32|0x00000026
183
184 # Non Secure Access Control Register
185 # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality
186 # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31
187 # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable
188 # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable
189 # 0xC00 = cp10 | cp11
190 gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039
191
192 [PcdsFixedAtBuild.AARCH64]
193 #
194 # AArch64 Security Extension
195 #
196
197 # Secure Configuration Register
198 # - BIT0 : NS - Non Secure bit
199 # - BIT1 : IRQ Handler
200 # - BIT2 : FIQ Handler
201 # - BIT3 : EA - External Abort
202 # - BIT4 : FW - F bit writable
203 # - BIT5 : AW - A bit writable
204 # - BIT6 : nET - Not Early Termination
205 # - BIT7 : SCD - Secure Monitor Call Disable
206 # - BIT8 : HCE - Hyp Call enable
207 # - BIT9 : SIF - Secure Instruction Fetch
208 # - BIT10: RW - Register width control for lower exception levels
209 # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer
210 # - BIT12: TWI - Trap WFI
211 # - BIT13: TWE - Trap WFE
212 # 0x501 = NS | HCE | RW
213 gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038
214
215 # By default we do transition to EL2 non-secure mode with Stack for EL2.
216 # Mode Description Bits
217 # NS EL2 SP2 all interrupts disabled = 0x3c9
218 # NS EL1 SP1 all interrupts disabled = 0x3c5
219 # Other modes include using SP0 or switching to Aarch32, but these are
220 # not currently supported.
221 gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E
222 # If the fixed FDT address is not available, then it should be loaded above the kernel.
223 # The recommendation from the AArch64 Linux kernel is to have the FDT below 512MB.
224 # (see the kernel doc: Documentation/arm64/booting.txt)
225 gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x20000000|UINT32|0x00000023
226 # The FDT blob must be loaded at a 2MB aligned address.
227 gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x00200000|UINT32|0x00000026
228
229
230 #
231 # These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be
232 # redefined when using UEFI in a context of virtual machine.
233 #
234 [PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]
235
236 # System Memory (DRAM): These PCDs define the region of in-built system memory
237 # Some platforms can get DRAM extensions, these additional regions may be
238 # declared to UEFI using separate resource descriptor HOBs
239 gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029
240 gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A
241
242 [PcdsFixedAtBuild.common, PcdsDynamic.common]
243 #
244 # ARM Architectural Timer
245 #
246 gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034
247
248 # ARM Architectural Timer Interrupt(GIC PPI) numbers
249 gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035
250 gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036
251 gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040
252 gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041
253
254 #
255 # ARM Generic Watchdog
256 #
257
258 gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT64|0x00000007
259 gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT64|0x00000008
260 gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009
261
262 #
263 # ARM Generic Interrupt Controller
264 #
265 gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C
266 # Base address for the GIC Redistributor region that contains the boot CPU
267 gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E
268 gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D
269 gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025
270
271 #
272 # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.
273 # Note that "IO" is just another MMIO range that simulates IO space; there
274 # are no special instructions to access it.
275 #
276 # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are
277 # specific to their containing address spaces. In order to get the physical
278 # address for the CPU, for a given access, the respective translation value
279 # has to be added.
280 #
281 # The translations always have to be initialized like this, using UINT64:
282 #
283 # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space
284 # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space
285 # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space
286 #
287 # PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;
288 # PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;
289 # PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;
290 #
291 # because (a) the target address space (ie. the cpu-physical space) is
292 # 64-bit, and (b) the translation values are meant as offsets for *modular*
293 # arithmetic.
294 #
295 # Accordingly, the translation itself needs to be implemented as:
296 #
297 # UINT64 UntranslatedIoAddress; // input parameter
298 # UINT32 UntranslatedMmio32Address; // input parameter
299 # UINT64 UntranslatedMmio64Address; // input parameter
300 #
301 # UINT64 TranslatedIoAddress; // output parameter
302 # UINT64 TranslatedMmio32Address; // output parameter
303 # UINT64 TranslatedMmio64Address; // output parameter
304 #
305 # TranslatedIoAddress = UntranslatedIoAddress +
306 # PcdPciIoTranslation;
307 # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +
308 # PcdPciMmio32Translation;
309 # TranslatedMmio64Address = UntranslatedMmio64Address +
310 # PcdPciMmio64Translation;
311 #
312 # The modular arithmetic performed in UINT64 ensures that the translation
313 # works correctly regardless of the relation between IoCpuBase and
314 # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and
315 # PcdPciMmio64Base.
316 #
317 gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050
318 gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051
319 gArmTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000052
320 gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053
321 gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054
322 gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000055
323 gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056
324 gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057
325 gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000058
326
327 #
328 # Inclusive range of allowed PCI buses.
329 #
330 gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059
331 gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A