ArmPkg/ArmPkg.dec

   1 #/** @file
   2 # ARM processor package.
   3 #
   4 # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
   5 # Copyright (c) 2011 - 2015, ARM Limited. All rights reserved.
   6 #
   7 #    This program and the accompanying materials
   8 #    are licensed and made available under the terms and conditions of the BSD License
   9 #    which accompanies this distribution. The full text of the license may be found at
  10 #    http://opensource.org/licenses/bsd-license.php
  11 #
  12 #    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13 #    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14 #
  15 #**/
  16
  17 [Defines]
  18   DEC_SPECIFICATION              = 0x00010005
  19   PACKAGE_NAME                   = ArmPkg
  20   PACKAGE_GUID                   = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F
  21   PACKAGE_VERSION                = 0.1
  22
  23 ################################################################################
  24 #
  25 # Include Section - list of Include Paths that are provided by this package.
  26 #                   Comments are used for Keywords and Module Types.
  27 #
  28 # Supported Module Types:
  29 #  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
  30 #
  31 ################################################################################
  32 [Includes.common]
  33   Include                        # Root include for the package
  34
  35 [LibraryClasses.common]
  36   ArmLib|Include/Library/ArmLib.h
  37   ArmMmuLib|Include/Library/ArmMmuLib.h
  38   SemihostLib|Include/Library/Semihosting.h
  39   UncachedMemoryAllocationLib|Include/Library/UncachedMemoryAllocationLib.h
  40   DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h
  41   ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h
  42   ArmGicArchLib|Include/Library/ArmGicArchLib.h
  43
  44 [Guids.common]
  45   gArmTokenSpaceGuid       = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }
  46
  47   ## ARM MPCore table
  48   # Include/Guid/ArmMpCoreInfo.h
  49   gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5,  {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }
  50
  51 [Ppis]
  52   ## Include/Ppi/ArmMpCoreInfo.h
  53   gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }
  54
  55 [Protocols.common]
  56   gVirtualUncachedPagesProtocolGuid = { 0xAD651C7D, 0x3C22, 0x4DBF, { 0x92, 0xe8, 0x38, 0xa7, 0xcd, 0xae, 0x87, 0xb2 } }
  57
  58 [PcdsFeatureFlag.common]
  59   gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001
  60
  61   # On ARM Architecture with the Security Extension, the address for the
  62   # Vector Table can be mapped anywhere in the memory map. It means we can
  63   # point the Exception Vector Table to its location in CpuDxe.
  64   # By default we copy the Vector Table at  PcdGet64(PcdCpuVectorBaseAddress)
  65   gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022
  66   # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before
  67   # it has been configured by the CPU DXE
  68   gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032
  69
  70   # Define if the spin-table mechanism is used by the secondary cores when booting
  71   # Linux (instead of PSCI)
  72   gArmTokenSpaceGuid.PcdArmLinuxSpinTable|FALSE|BOOLEAN|0x00000033
  73
  74   # Define if the GICv3 controller should use the GICv2 legacy
  75   gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042
  76
  77 [PcdsFeatureFlag.ARM]
  78   # Whether to map normal memory as non-shareable. FALSE is the safe choice, but
  79   # TRUE may be appropriate to fix performance problems if you don't care about
  80   # hardware coherency (i.e., no virtualization or cache coherent DMA)
  81   gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043
  82
  83 [PcdsFixedAtBuild.common]
  84   gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006
  85
  86   # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.
  87   # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
  88   gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024
  89
  90   gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000080000000|UINT64|0x00000002
  91   # This PCD will free the unallocated buffers if their size reach this threshold.
  92   # We set the default value to 512MB.
  93   gArmTokenSpaceGuid.PcdArmFreeUncachedMemorySizeThreshold|0x20000000|UINT64|0x00000003
  94   gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004
  95   gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005
  96
  97   #
  98   # ARM Secure Firmware PCDs
  99   #
 100   gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015
 101   gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016
 102   gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F
 103   gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030
 104
 105   #
 106   # ARM Hypervisor Firmware PCDs
 107   #
 108   gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A
 109   gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B
 110   gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C
 111   gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D
 112
 113   # Use ClusterId + CoreId to identify the PrimaryCore
 114   gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031
 115   # The Primary Core is ClusterId[0] & CoreId[0]
 116   gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037
 117
 118   #
 119   # ARM L2x0 PCDs
 120   #
 121   gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B
 122
 123   #
 124   # BdsLib
 125   #
 126   # The compressed Linux kernel is expected to be under 128MB from the beginning of the System Memory
 127   gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset|0x08000000|UINT32|0x0000001F
 128   # Maximum file size for TFTP servers that do not support 'tsize' extension
 129   gArmTokenSpaceGuid.PcdMaxTftpFileSize|0x01000000|UINT32|0x00000000
 130
 131   #
 132   # ARM Normal (or Non Secure) Firmware PCDs
 133   #
 134   gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C
 135   gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E
 136
 137 [PcdsFixedAtBuild.common, PcdsPatchableInModule.common]
 138   gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B
 139   gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D
 140
 141 [PcdsFixedAtBuild.ARM]
 142   #
 143   # ARM Security Extension
 144   #
 145
 146   # Secure Configuration Register
 147   # - BIT0 : NS - Non Secure bit
 148   # - BIT1 : IRQ Handler
 149   # - BIT2 : FIQ Handler
 150   # - BIT3 : EA - External Abort
 151   # - BIT4 : FW - F bit writable
 152   # - BIT5 : AW - A bit writable
 153   # - BIT6 : nET - Not Early Termination
 154   # - BIT7 : SCD - Secure Monitor Call Disable
 155   # - BIT8 : HCE - Hyp Call enable
 156   # - BIT9 : SIF - Secure Instruction Fetch
 157   # 0x31 = NS | EA | FW
 158   gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038
 159
 160   # By default we do not do a transition to non-secure mode
 161   gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E
 162
 163   # The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory
 164   gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset|0x4000|UINT32|0x00000020
 165
 166   # If the fixed FDT address is not available, then it should be loaded below the kernel.
 167   # The recommendation from the Linux kernel is to have the FDT below 16KB.
 168   # (see the kernel doc: Documentation/arm/Booting)
 169   gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x4000|UINT32|0x00000023
 170   # The FDT blob must be loaded at a 64bit aligned address.
 171   gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x8|UINT32|0x00000026
 172
 173   # Non Secure Access Control Register
 174   # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality
 175   # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31
 176   # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable
 177   # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable
 178   # 0xC00 = cp10 | cp11
 179   gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039
 180
 181 [PcdsFixedAtBuild.AARCH64]
 182   #
 183   # AArch64 Security Extension
 184   #
 185
 186   # Secure Configuration Register
 187   # - BIT0 : NS - Non Secure bit
 188   # - BIT1 : IRQ Handler
 189   # - BIT2 : FIQ Handler
 190   # - BIT3 : EA - External Abort
 191   # - BIT4 : FW - F bit writable
 192   # - BIT5 : AW - A bit writable
 193   # - BIT6 : nET - Not Early Termination
 194   # - BIT7 : SCD - Secure Monitor Call Disable
 195   # - BIT8 : HCE - Hyp Call enable
 196   # - BIT9 : SIF - Secure Instruction Fetch
 197   # - BIT10: RW -  Register width control for lower exception levels
 198   # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer
 199   # - BIT12: TWI - Trap WFI
 200   # - BIT13: TWE - Trap WFE
 201   # 0x501 = NS | HCE | RW
 202   gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038
 203
 204   # By default we do transition to EL2 non-secure mode with Stack for EL2.
 205   #        Mode Description              Bits
 206   # NS EL2 SP2 all interrupts disabled =  0x3c9
 207   # NS EL1 SP1 all interrupts disabled =  0x3c5
 208   # Other modes include using SP0 or switching to Aarch32, but these are
 209   # not currently supported.
 210   gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E
 211   # If the fixed FDT address is not available, then it should be loaded above the kernel.
 212   # The recommendation from the AArch64 Linux kernel is to have the FDT below 512MB.
 213   # (see the kernel doc: Documentation/arm64/booting.txt)
 214   gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x20000000|UINT32|0x00000023
 215   # The FDT blob must be loaded at a 2MB aligned address.
 216   gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x00200000|UINT32|0x00000026
 217
 218
 219 #
 220 # These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be
 221 # redefined when using UEFI in a context of virtual machine.
 222 #
 223 [PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]
 224
 225   # System Memory (DRAM): These PCDs define the region of in-built system memory
 226   # Some platforms can get DRAM extensions, these additional regions will be declared
 227   # to UEFI by ArmPlatformLib
 228   gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029
 229   gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A
 230
 231 [PcdsFixedAtBuild.common, PcdsDynamic.common]
 232   #
 233   # ARM Architectural Timer
 234   #
 235   gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034
 236
 237   # ARM Architectural Timer Interrupt(GIC PPI) numbers
 238   gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035
 239   gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036
 240   gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040
 241   gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041
 242
 243   #
 244   # ARM Generic Watchdog
 245   #
 246
 247   gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT32|0x00000007
 248   gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT32|0x00000008
 249   gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009
 250
 251   #
 252   # ARM Generic Interrupt Controller
 253   #
 254   gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C
 255   # Base address for the GIC Redistributor region that contains the boot CPU
 256   gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E
 257   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D
 258   gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025
 259
 260   #
 261   # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.
 262   # Note that "IO" is just another MMIO range that simulates IO space; there
 263   # are no special instructions to access it.
 264   #
 265   # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are
 266   # specific to their containing address spaces. In order to get the physical
 267   # address for the CPU, for a given access, the respective translation value
 268   # has to be added.
 269   #
 270   # The translations always have to be initialized like this, using UINT64:
 271   #
 272   #   UINT64 IoCpuBase;     // mapping target in 64-bit cpu-physical space
 273   #   UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space
 274   #   UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space
 275   #
 276   #   PcdPciIoTranslation     = IoCpuBase     - PcdPciIoBase;
 277   #   PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;
 278   #   PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;
 279   #
 280   # because (a) the target address space (ie. the cpu-physical space) is
 281   # 64-bit, and (b) the translation values are meant as offsets for *modular*
 282   # arithmetic.
 283   #
 284   # Accordingly, the translation itself needs to be implemented as:
 285   #
 286   #   UINT64 UntranslatedIoAddress;     // input parameter
 287   #   UINT32 UntranslatedMmio32Address; // input parameter
 288   #   UINT64 UntranslatedMmio64Address; // input parameter
 289   #
 290   #   UINT64 TranslatedIoAddress;       // output parameter
 291   #   UINT64 TranslatedMmio32Address;   // output parameter
 292   #   UINT64 TranslatedMmio64Address;   // output parameter
 293   #
 294   #   TranslatedIoAddress     = UntranslatedIoAddress +
 295   #                             PcdPciIoTranslation;
 296   #   TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +
 297   #                             PcdPciMmio32Translation;
 298   #   TranslatedMmio64Address = UntranslatedMmio64Address +
 299   #                             PcdPciMmio64Translation;
 300   #
 301   #  The modular arithmetic performed in UINT64 ensures that the translation
 302   #  works correctly regardless of the relation between IoCpuBase and
 303   #  PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and
 304   #  PcdPciMmio64Base.
 305   #
 306   gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050
 307   gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051
 308   gArmTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000052
 309   gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053
 310   gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054
 311   gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000055
 312   gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056
 313   gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057
 314   gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000058
 315
 316   #
 317   # Inclusive range of allowed PCI buses.
 318   #
 319   gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059
 320   gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A