ArmPkg/ArmPkg.dec

   1 #/** @file
   2 # ARM processor package.
   3 #
   4 # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
   5 # Copyright (c) 2011 - 2018, ARM Limited. All rights reserved.
   6 #
   7 #    This program and the accompanying materials
   8 #    are licensed and made available under the terms and conditions of the BSD License
   9 #    which accompanies this distribution. The full text of the license may be found at
  10 #    http://opensource.org/licenses/bsd-license.php
  11 #
  12 #    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13 #    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14 #
  15 #**/
  16
  17 [Defines]
  18   DEC_SPECIFICATION              = 0x00010005
  19   PACKAGE_NAME                   = ArmPkg
  20   PACKAGE_GUID                   = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F
  21   PACKAGE_VERSION                = 0.1
  22
  23 ################################################################################
  24 #
  25 # Include Section - list of Include Paths that are provided by this package.
  26 #                   Comments are used for Keywords and Module Types.
  27 #
  28 # Supported Module Types:
  29 #  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
  30 #
  31 ################################################################################
  32 [Includes.common]
  33   Include                        # Root include for the package
  34
  35 [LibraryClasses.common]
  36   ArmLib|Include/Library/ArmLib.h
  37   ArmMmuLib|Include/Library/ArmMmuLib.h
  38   SemihostLib|Include/Library/Semihosting.h
  39   DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h
  40   ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h
  41   ArmGicArchLib|Include/Library/ArmGicArchLib.h
  42   ArmMtlLib|ArmPlatformPkg/Include/Library/ArmMtlLib.h
  43   ArmSvcLib|Include/Library/ArmSvcLib.h
  44   OpteeLib|Include/Library/OpteeLib.h
  45   StandaloneMmMmuLib|Include/Library/StandaloneMmMmuLib.h
  46
  47 [Guids.common]
  48   gArmTokenSpaceGuid       = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }
  49
  50   ## ARM MPCore table
  51   # Include/Guid/ArmMpCoreInfo.h
  52   gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5,  {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }
  53
  54 [Protocols.common]
  55   ## Arm System Control and Management Interface(SCMI) Base protocol
  56   ## ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h
  57   gArmScmiBaseProtocolGuid = { 0xd7e5abe9, 0x33ab, 0x418e, { 0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f } }
  58
  59   ## Arm System Control and Management Interface(SCMI) Clock management protocol
  60   ## ArmPkg/Include/Protocol/ArmScmiClockProtocol.h
  61   gArmScmiClockProtocolGuid = { 0x91ce67a8, 0xe0aa, 0x4012, { 0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa } }
  62   gArmScmiClock2ProtocolGuid = { 0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } }
  63
  64   ## Arm System Control and Management Interface(SCMI) Clock management protocol
  65   ## ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h
  66   gArmScmiPerformanceProtocolGuid = { 0x9b8ba84, 0x3dd3, 0x49a6, { 0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad } }
  67
  68 [Ppis]
  69   ## Include/Ppi/ArmMpCoreInfo.h
  70   gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }
  71
  72 [PcdsFeatureFlag.common]
  73   gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001
  74
  75   # On ARM Architecture with the Security Extension, the address for the
  76   # Vector Table can be mapped anywhere in the memory map. It means we can
  77   # point the Exception Vector Table to its location in CpuDxe.
  78   # By default we copy the Vector Table at  PcdGet64(PcdCpuVectorBaseAddress)
  79   gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022
  80   # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before
  81   # it has been configured by the CPU DXE
  82   gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032
  83
  84   # Define if the GICv3 controller should use the GICv2 legacy
  85   gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042
  86
  87   # Whether to implement warm reboot for capsule update using a jump back to the
  88   # PEI entry point with caches and interrupts disabled.
  89   gArmTokenSpaceGuid.PcdArmReenterPeiForCapsuleWarmReboot|FALSE|BOOLEAN|0x0000001F
  90
  91 [PcdsFeatureFlag.ARM]
  92   # Whether to map normal memory as non-shareable. FALSE is the safe choice, but
  93   # TRUE may be appropriate to fix performance problems if you don't care about
  94   # hardware coherency (i.e., no virtualization or cache coherent DMA)
  95   gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043
  96
  97 [PcdsFixedAtBuild.common]
  98   gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006
  99
 100   # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.
 101   # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
 102   gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024
 103
 104   gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004
 105   gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005
 106
 107   #
 108   # ARM Secure Firmware PCDs
 109   #
 110   gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015
 111   gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016
 112   gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F
 113   gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030
 114
 115   #
 116   # ARM Hypervisor Firmware PCDs
 117   #
 118   gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A
 119   gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B
 120   gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C
 121   gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D
 122
 123   # Use ClusterId + CoreId to identify the PrimaryCore
 124   gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031
 125   # The Primary Core is ClusterId[0] & CoreId[0]
 126   gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037
 127
 128   #
 129   # ARM L2x0 PCDs
 130   #
 131   gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B
 132
 133   #
 134   # ARM Normal (or Non Secure) Firmware PCDs
 135   #
 136   gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C
 137   gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E
 138
 139   #
 140   # Value to add to a host address to obtain a device address, using
 141   # unsigned 64-bit integer arithmetic on both ARM and AArch64. This
 142   # means we can rely on truncation on overflow to specify negative
 143   # offsets.
 144   #
 145   gArmTokenSpaceGuid.PcdArmDmaDeviceOffset|0x0|UINT64|0x0000044
 146
 147 [PcdsFixedAtBuild.common, PcdsPatchableInModule.common]
 148   gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B
 149   gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D
 150
 151 [PcdsFixedAtBuild.ARM]
 152   #
 153   # ARM Security Extension
 154   #
 155
 156   # Secure Configuration Register
 157   # - BIT0 : NS - Non Secure bit
 158   # - BIT1 : IRQ Handler
 159   # - BIT2 : FIQ Handler
 160   # - BIT3 : EA - External Abort
 161   # - BIT4 : FW - F bit writable
 162   # - BIT5 : AW - A bit writable
 163   # - BIT6 : nET - Not Early Termination
 164   # - BIT7 : SCD - Secure Monitor Call Disable
 165   # - BIT8 : HCE - Hyp Call enable
 166   # - BIT9 : SIF - Secure Instruction Fetch
 167   # 0x31 = NS | EA | FW
 168   gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038
 169
 170   # By default we do not do a transition to non-secure mode
 171   gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E
 172
 173   # Non Secure Access Control Register
 174   # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality
 175   # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31
 176   # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable
 177   # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable
 178   # 0xC00 = cp10 | cp11
 179   gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039
 180
 181 [PcdsFixedAtBuild.AARCH64]
 182   #
 183   # AArch64 Security Extension
 184   #
 185
 186   # Secure Configuration Register
 187   # - BIT0 : NS - Non Secure bit
 188   # - BIT1 : IRQ Handler
 189   # - BIT2 : FIQ Handler
 190   # - BIT3 : EA - External Abort
 191   # - BIT4 : FW - F bit writable
 192   # - BIT5 : AW - A bit writable
 193   # - BIT6 : nET - Not Early Termination
 194   # - BIT7 : SCD - Secure Monitor Call Disable
 195   # - BIT8 : HCE - Hyp Call enable
 196   # - BIT9 : SIF - Secure Instruction Fetch
 197   # - BIT10: RW -  Register width control for lower exception levels
 198   # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer
 199   # - BIT12: TWI - Trap WFI
 200   # - BIT13: TWE - Trap WFE
 201   # 0x501 = NS | HCE | RW
 202   gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038
 203
 204   # By default we do transition to EL2 non-secure mode with Stack for EL2.
 205   #        Mode Description              Bits
 206   # NS EL2 SP2 all interrupts disabled =  0x3c9
 207   # NS EL1 SP1 all interrupts disabled =  0x3c5
 208   # Other modes include using SP0 or switching to Aarch32, but these are
 209   # not currently supported.
 210   gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E
 211
 212
 213 #
 214 # These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be
 215 # redefined when using UEFI in a context of virtual machine.
 216 #
 217 [PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]
 218
 219   # System Memory (DRAM): These PCDs define the region of in-built system memory
 220   # Some platforms can get DRAM extensions, these additional regions may be
 221   # declared to UEFI using separate resource descriptor HOBs
 222   gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029
 223   gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A
 224
 225   gArmTokenSpaceGuid.PcdMmBufferBase|0|UINT64|0x00000045
 226   gArmTokenSpaceGuid.PcdMmBufferSize|0|UINT64|0x00000046
 227
 228 [PcdsFixedAtBuild.common, PcdsDynamic.common]
 229   #
 230   # ARM Architectural Timer
 231   #
 232   gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034
 233
 234   # ARM Architectural Timer Interrupt(GIC PPI) numbers
 235   gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035
 236   gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036
 237   gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040
 238   gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041
 239
 240   #
 241   # ARM Generic Watchdog
 242   #
 243
 244   gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT64|0x00000007
 245   gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT64|0x00000008
 246   gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009
 247
 248   #
 249   # ARM Generic Interrupt Controller
 250   #
 251   gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C
 252   # Base address for the GIC Redistributor region that contains the boot CPU
 253   gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E
 254   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D
 255   gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025
 256
 257   #
 258   # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.
 259   # Note that "IO" is just another MMIO range that simulates IO space; there
 260   # are no special instructions to access it.
 261   #
 262   # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are
 263   # specific to their containing address spaces. In order to get the physical
 264   # address for the CPU, for a given access, the respective translation value
 265   # has to be added.
 266   #
 267   # The translations always have to be initialized like this, using UINT64:
 268   #
 269   #   UINT64 IoCpuBase;     // mapping target in 64-bit cpu-physical space
 270   #   UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space
 271   #   UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space
 272   #
 273   #   PcdPciIoTranslation     = IoCpuBase     - PcdPciIoBase;
 274   #   PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;
 275   #   PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;
 276   #
 277   # because (a) the target address space (ie. the cpu-physical space) is
 278   # 64-bit, and (b) the translation values are meant as offsets for *modular*
 279   # arithmetic.
 280   #
 281   # Accordingly, the translation itself needs to be implemented as:
 282   #
 283   #   UINT64 UntranslatedIoAddress;     // input parameter
 284   #   UINT32 UntranslatedMmio32Address; // input parameter
 285   #   UINT64 UntranslatedMmio64Address; // input parameter
 286   #
 287   #   UINT64 TranslatedIoAddress;       // output parameter
 288   #   UINT64 TranslatedMmio32Address;   // output parameter
 289   #   UINT64 TranslatedMmio64Address;   // output parameter
 290   #
 291   #   TranslatedIoAddress     = UntranslatedIoAddress +
 292   #                             PcdPciIoTranslation;
 293   #   TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +
 294   #                             PcdPciMmio32Translation;
 295   #   TranslatedMmio64Address = UntranslatedMmio64Address +
 296   #                             PcdPciMmio64Translation;
 297   #
 298   #  The modular arithmetic performed in UINT64 ensures that the translation
 299   #  works correctly regardless of the relation between IoCpuBase and
 300   #  PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and
 301   #  PcdPciMmio64Base.
 302   #
 303   gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050
 304   gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051
 305   gArmTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000052
 306   gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053
 307   gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054
 308   gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000055
 309   gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056
 310   gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057
 311   gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000058
 312
 313   #
 314   # Inclusive range of allowed PCI buses.
 315   #
 316   gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059
 317   gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A