2 # ARM processor package.
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4 # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
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5 # Copyright (c) 2011 - 2018, ARM Limited. All rights reserved.
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7 # This program and the accompanying materials
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8 # are licensed and made available under the terms and conditions of the BSD License
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9 # which accompanies this distribution. The full text of the license may be found at
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10 # http://opensource.org/licenses/bsd-license.php
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12 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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13 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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18 DEC_SPECIFICATION = 0x00010005
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19 PACKAGE_NAME = ArmPkg
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20 PACKAGE_GUID = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F
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21 PACKAGE_VERSION = 0.1
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23 ################################################################################
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25 # Include Section - list of Include Paths that are provided by this package.
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26 # Comments are used for Keywords and Module Types.
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28 # Supported Module Types:
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29 # BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
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31 ################################################################################
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33 Include # Root include for the package
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35 [LibraryClasses.common]
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36 ArmLib|Include/Library/ArmLib.h
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37 ArmMmuLib|Include/Library/ArmMmuLib.h
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38 SemihostLib|Include/Library/Semihosting.h
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39 DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h
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40 ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h
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41 ArmGicArchLib|Include/Library/ArmGicArchLib.h
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42 ArmMtlLib|ArmPlatformPkg/Include/Library/ArmMtlLib.h
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43 ArmSvcLib|Include/Library/ArmSvcLib.h
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44 OpteeLib|Include/Library/OpteeLib.h
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45 StandaloneMmMmuLib|Include/Library/StandaloneMmMmuLib.h
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48 gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }
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51 # Include/Guid/ArmMpCoreInfo.h
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52 gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }
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55 ## Arm System Control and Management Interface(SCMI) Base protocol
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56 ## ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h
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57 gArmScmiBaseProtocolGuid = { 0xd7e5abe9, 0x33ab, 0x418e, { 0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f } }
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59 ## Arm System Control and Management Interface(SCMI) Clock management protocol
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60 ## ArmPkg/Include/Protocol/ArmScmiClockProtocol.h
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61 gArmScmiClockProtocolGuid = { 0x91ce67a8, 0xe0aa, 0x4012, { 0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa } }
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62 gArmScmiClock2ProtocolGuid = { 0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } }
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64 ## Arm System Control and Management Interface(SCMI) Clock management protocol
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65 ## ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h
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66 gArmScmiPerformanceProtocolGuid = { 0x9b8ba84, 0x3dd3, 0x49a6, { 0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad } }
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69 ## Include/Ppi/ArmMpCoreInfo.h
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70 gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }
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72 [PcdsFeatureFlag.common]
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73 gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001
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75 # On ARM Architecture with the Security Extension, the address for the
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76 # Vector Table can be mapped anywhere in the memory map. It means we can
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77 # point the Exception Vector Table to its location in CpuDxe.
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78 # By default we copy the Vector Table at PcdGet64(PcdCpuVectorBaseAddress)
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79 gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022
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80 # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before
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81 # it has been configured by the CPU DXE
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82 gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032
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84 # Define if the GICv3 controller should use the GICv2 legacy
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85 gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042
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87 # Whether to implement warm reboot for capsule update using a jump back to the
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88 # PEI entry point with caches and interrupts disabled.
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89 gArmTokenSpaceGuid.PcdArmReenterPeiForCapsuleWarmReboot|FALSE|BOOLEAN|0x0000001F
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91 [PcdsFeatureFlag.ARM]
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92 # Whether to map normal memory as non-shareable. FALSE is the safe choice, but
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93 # TRUE may be appropriate to fix performance problems if you don't care about
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94 # hardware coherency (i.e., no virtualization or cache coherent DMA)
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95 gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043
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97 [PcdsFixedAtBuild.common]
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98 gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006
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100 # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.
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101 # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
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102 gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024
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104 gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004
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105 gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005
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108 # ARM Secure Firmware PCDs
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110 gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015
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111 gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016
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112 gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F
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113 gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030
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116 # ARM Hypervisor Firmware PCDs
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118 gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A
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119 gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B
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120 gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C
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121 gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D
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123 # Use ClusterId + CoreId to identify the PrimaryCore
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124 gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031
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125 # The Primary Core is ClusterId[0] & CoreId[0]
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126 gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037
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131 gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B
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134 # ARM Normal (or Non Secure) Firmware PCDs
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136 gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C
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137 gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E
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140 # Value to add to a host address to obtain a device address, using
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141 # unsigned 64-bit integer arithmetic on both ARM and AArch64. This
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142 # means we can rely on truncation on overflow to specify negative
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145 gArmTokenSpaceGuid.PcdArmDmaDeviceOffset|0x0|UINT64|0x0000044
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147 [PcdsFixedAtBuild.common, PcdsPatchableInModule.common]
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148 gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B
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149 gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D
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151 [PcdsFixedAtBuild.ARM]
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153 # ARM Security Extension
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156 # Secure Configuration Register
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157 # - BIT0 : NS - Non Secure bit
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158 # - BIT1 : IRQ Handler
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159 # - BIT2 : FIQ Handler
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160 # - BIT3 : EA - External Abort
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161 # - BIT4 : FW - F bit writable
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162 # - BIT5 : AW - A bit writable
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163 # - BIT6 : nET - Not Early Termination
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164 # - BIT7 : SCD - Secure Monitor Call Disable
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165 # - BIT8 : HCE - Hyp Call enable
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166 # - BIT9 : SIF - Secure Instruction Fetch
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167 # 0x31 = NS | EA | FW
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168 gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038
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170 # By default we do not do a transition to non-secure mode
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171 gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E
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173 # Non Secure Access Control Register
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174 # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality
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175 # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31
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176 # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable
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177 # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable
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178 # 0xC00 = cp10 | cp11
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179 gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039
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181 [PcdsFixedAtBuild.AARCH64]
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183 # AArch64 Security Extension
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186 # Secure Configuration Register
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187 # - BIT0 : NS - Non Secure bit
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188 # - BIT1 : IRQ Handler
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189 # - BIT2 : FIQ Handler
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190 # - BIT3 : EA - External Abort
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191 # - BIT4 : FW - F bit writable
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192 # - BIT5 : AW - A bit writable
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193 # - BIT6 : nET - Not Early Termination
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194 # - BIT7 : SCD - Secure Monitor Call Disable
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195 # - BIT8 : HCE - Hyp Call enable
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196 # - BIT9 : SIF - Secure Instruction Fetch
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197 # - BIT10: RW - Register width control for lower exception levels
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198 # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer
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199 # - BIT12: TWI - Trap WFI
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200 # - BIT13: TWE - Trap WFE
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201 # 0x501 = NS | HCE | RW
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202 gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038
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204 # By default we do transition to EL2 non-secure mode with Stack for EL2.
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205 # Mode Description Bits
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206 # NS EL2 SP2 all interrupts disabled = 0x3c9
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207 # NS EL1 SP1 all interrupts disabled = 0x3c5
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208 # Other modes include using SP0 or switching to Aarch32, but these are
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209 # not currently supported.
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210 gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E
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214 # These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be
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215 # redefined when using UEFI in a context of virtual machine.
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217 [PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]
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219 # System Memory (DRAM): These PCDs define the region of in-built system memory
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220 # Some platforms can get DRAM extensions, these additional regions may be
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221 # declared to UEFI using separate resource descriptor HOBs
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222 gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029
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223 gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A
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225 gArmTokenSpaceGuid.PcdMmBufferBase|0|UINT64|0x00000045
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226 gArmTokenSpaceGuid.PcdMmBufferSize|0|UINT64|0x00000046
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228 [PcdsFixedAtBuild.common, PcdsDynamic.common]
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230 # ARM Architectural Timer
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232 gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034
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234 # ARM Architectural Timer Interrupt(GIC PPI) numbers
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235 gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035
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236 gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036
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237 gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040
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238 gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041
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241 # ARM Generic Watchdog
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244 gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT64|0x00000007
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245 gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT64|0x00000008
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246 gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009
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249 # ARM Generic Interrupt Controller
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251 gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C
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252 # Base address for the GIC Redistributor region that contains the boot CPU
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253 gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E
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254 gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D
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255 gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025
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258 # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.
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259 # Note that "IO" is just another MMIO range that simulates IO space; there
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260 # are no special instructions to access it.
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262 # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are
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263 # specific to their containing address spaces. In order to get the physical
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264 # address for the CPU, for a given access, the respective translation value
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267 # The translations always have to be initialized like this, using UINT64:
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269 # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space
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270 # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space
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271 # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space
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273 # PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;
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274 # PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;
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275 # PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;
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277 # because (a) the target address space (ie. the cpu-physical space) is
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278 # 64-bit, and (b) the translation values are meant as offsets for *modular*
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281 # Accordingly, the translation itself needs to be implemented as:
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283 # UINT64 UntranslatedIoAddress; // input parameter
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284 # UINT32 UntranslatedMmio32Address; // input parameter
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285 # UINT64 UntranslatedMmio64Address; // input parameter
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287 # UINT64 TranslatedIoAddress; // output parameter
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288 # UINT64 TranslatedMmio32Address; // output parameter
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289 # UINT64 TranslatedMmio64Address; // output parameter
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291 # TranslatedIoAddress = UntranslatedIoAddress +
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292 # PcdPciIoTranslation;
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293 # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +
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294 # PcdPciMmio32Translation;
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295 # TranslatedMmio64Address = UntranslatedMmio64Address +
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296 # PcdPciMmio64Translation;
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298 # The modular arithmetic performed in UINT64 ensures that the translation
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299 # works correctly regardless of the relation between IoCpuBase and
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300 # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and
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301 # PcdPciMmio64Base.
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303 gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050
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304 gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051
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305 gArmTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000052
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306 gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053
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307 gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054
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308 gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000055
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309 gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056
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310 gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057
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311 gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000058
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314 # Inclusive range of allowed PCI buses.
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316 gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059
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317 gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A
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