BaseTools/Capsule: Do not support -o with --dump-info
[mirror_edk2.git] / ArmPkg / ArmPkg.dec
1 #/** @file
2 # ARM processor package.
3 #
4 # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
5 # Copyright (c) 2011 - 2018, ARM Limited. All rights reserved.
6 #
7 # This program and the accompanying materials
8 # are licensed and made available under the terms and conditions of the BSD License
9 # which accompanies this distribution. The full text of the license may be found at
10 # http://opensource.org/licenses/bsd-license.php
11 #
12 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14 #
15 #**/
16
17 [Defines]
18 DEC_SPECIFICATION = 0x00010005
19 PACKAGE_NAME = ArmPkg
20 PACKAGE_GUID = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F
21 PACKAGE_VERSION = 0.1
22
23 ################################################################################
24 #
25 # Include Section - list of Include Paths that are provided by this package.
26 # Comments are used for Keywords and Module Types.
27 #
28 # Supported Module Types:
29 # BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
30 #
31 ################################################################################
32 [Includes.common]
33 Include # Root include for the package
34
35 [LibraryClasses.common]
36 ArmLib|Include/Library/ArmLib.h
37 ArmMmuLib|Include/Library/ArmMmuLib.h
38 SemihostLib|Include/Library/Semihosting.h
39 DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h
40 ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h
41 ArmGicArchLib|Include/Library/ArmGicArchLib.h
42 ArmMtlLib|ArmPlatformPkg/Include/Library/ArmMtlLib.h
43 ArmSvcLib|Include/Library/ArmSvcLib.h
44 OpteeLib|Include/Library/OpteeLib.h
45
46 [Guids.common]
47 gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }
48
49 ## ARM MPCore table
50 # Include/Guid/ArmMpCoreInfo.h
51 gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }
52
53 [Protocols.common]
54 ## Arm System Control and Management Interface(SCMI) Base protocol
55 ## ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h
56 gArmScmiBaseProtocolGuid = { 0xd7e5abe9, 0x33ab, 0x418e, { 0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f } }
57
58 ## Arm System Control and Management Interface(SCMI) Clock management protocol
59 ## ArmPkg/Include/Protocol/ArmScmiClockProtocol.h
60 gArmScmiClockProtocolGuid = { 0x91ce67a8, 0xe0aa, 0x4012, { 0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa } }
61
62 ## Arm System Control and Management Interface(SCMI) Clock management protocol
63 ## ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h
64 gArmScmiPerformanceProtocolGuid = { 0x9b8ba84, 0x3dd3, 0x49a6, { 0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad } }
65
66 [Ppis]
67 ## Include/Ppi/ArmMpCoreInfo.h
68 gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }
69
70 [PcdsFeatureFlag.common]
71 gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001
72
73 # On ARM Architecture with the Security Extension, the address for the
74 # Vector Table can be mapped anywhere in the memory map. It means we can
75 # point the Exception Vector Table to its location in CpuDxe.
76 # By default we copy the Vector Table at PcdGet64(PcdCpuVectorBaseAddress)
77 gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022
78 # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before
79 # it has been configured by the CPU DXE
80 gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032
81
82 # Define if the spin-table mechanism is used by the secondary cores when booting
83 # Linux (instead of PSCI)
84 gArmTokenSpaceGuid.PcdArmLinuxSpinTable|FALSE|BOOLEAN|0x00000033
85
86 # Define if the GICv3 controller should use the GICv2 legacy
87 gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042
88
89 # Whether to implement warm reboot for capsule update using a jump back to the
90 # PEI entry point with caches and interrupts disabled.
91 gArmTokenSpaceGuid.PcdArmReenterPeiForCapsuleWarmReboot|FALSE|BOOLEAN|0x0000001F
92
93 [PcdsFeatureFlag.ARM]
94 # Whether to map normal memory as non-shareable. FALSE is the safe choice, but
95 # TRUE may be appropriate to fix performance problems if you don't care about
96 # hardware coherency (i.e., no virtualization or cache coherent DMA)
97 gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043
98
99 [PcdsFixedAtBuild.common]
100 gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006
101
102 # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.
103 # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
104 gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024
105
106 gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004
107 gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005
108
109 #
110 # ARM Secure Firmware PCDs
111 #
112 gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015
113 gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016
114 gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F
115 gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030
116
117 #
118 # ARM Hypervisor Firmware PCDs
119 #
120 gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A
121 gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B
122 gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C
123 gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D
124
125 # Use ClusterId + CoreId to identify the PrimaryCore
126 gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031
127 # The Primary Core is ClusterId[0] & CoreId[0]
128 gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037
129
130 #
131 # ARM L2x0 PCDs
132 #
133 gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B
134
135 #
136 # ARM Normal (or Non Secure) Firmware PCDs
137 #
138 gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C
139 gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E
140
141 #
142 # Value to add to a host address to obtain a device address, using
143 # unsigned 64-bit integer arithmetic on both ARM and AArch64. This
144 # means we can rely on truncation on overflow to specify negative
145 # offsets.
146 #
147 gArmTokenSpaceGuid.PcdArmDmaDeviceOffset|0x0|UINT64|0x0000044
148
149 [PcdsFixedAtBuild.common, PcdsPatchableInModule.common]
150 gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B
151 gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D
152
153 [PcdsFixedAtBuild.ARM]
154 #
155 # ARM Security Extension
156 #
157
158 # Secure Configuration Register
159 # - BIT0 : NS - Non Secure bit
160 # - BIT1 : IRQ Handler
161 # - BIT2 : FIQ Handler
162 # - BIT3 : EA - External Abort
163 # - BIT4 : FW - F bit writable
164 # - BIT5 : AW - A bit writable
165 # - BIT6 : nET - Not Early Termination
166 # - BIT7 : SCD - Secure Monitor Call Disable
167 # - BIT8 : HCE - Hyp Call enable
168 # - BIT9 : SIF - Secure Instruction Fetch
169 # 0x31 = NS | EA | FW
170 gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038
171
172 # By default we do not do a transition to non-secure mode
173 gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E
174
175 # The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory
176 gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset|0x4000|UINT32|0x00000020
177
178 # If the fixed FDT address is not available, then it should be loaded below the kernel.
179 # The recommendation from the Linux kernel is to have the FDT below 16KB.
180 # (see the kernel doc: Documentation/arm/Booting)
181 gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x4000|UINT32|0x00000023
182 # The FDT blob must be loaded at a 64bit aligned address.
183 gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x8|UINT32|0x00000026
184
185 # Non Secure Access Control Register
186 # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality
187 # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31
188 # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable
189 # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable
190 # 0xC00 = cp10 | cp11
191 gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039
192
193 [PcdsFixedAtBuild.AARCH64]
194 #
195 # AArch64 Security Extension
196 #
197
198 # Secure Configuration Register
199 # - BIT0 : NS - Non Secure bit
200 # - BIT1 : IRQ Handler
201 # - BIT2 : FIQ Handler
202 # - BIT3 : EA - External Abort
203 # - BIT4 : FW - F bit writable
204 # - BIT5 : AW - A bit writable
205 # - BIT6 : nET - Not Early Termination
206 # - BIT7 : SCD - Secure Monitor Call Disable
207 # - BIT8 : HCE - Hyp Call enable
208 # - BIT9 : SIF - Secure Instruction Fetch
209 # - BIT10: RW - Register width control for lower exception levels
210 # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer
211 # - BIT12: TWI - Trap WFI
212 # - BIT13: TWE - Trap WFE
213 # 0x501 = NS | HCE | RW
214 gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038
215
216 # By default we do transition to EL2 non-secure mode with Stack for EL2.
217 # Mode Description Bits
218 # NS EL2 SP2 all interrupts disabled = 0x3c9
219 # NS EL1 SP1 all interrupts disabled = 0x3c5
220 # Other modes include using SP0 or switching to Aarch32, but these are
221 # not currently supported.
222 gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E
223 # If the fixed FDT address is not available, then it should be loaded above the kernel.
224 # The recommendation from the AArch64 Linux kernel is to have the FDT below 512MB.
225 # (see the kernel doc: Documentation/arm64/booting.txt)
226 gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x20000000|UINT32|0x00000023
227 # The FDT blob must be loaded at a 2MB aligned address.
228 gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x00200000|UINT32|0x00000026
229
230
231 #
232 # These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be
233 # redefined when using UEFI in a context of virtual machine.
234 #
235 [PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]
236
237 # System Memory (DRAM): These PCDs define the region of in-built system memory
238 # Some platforms can get DRAM extensions, these additional regions may be
239 # declared to UEFI using separate resource descriptor HOBs
240 gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029
241 gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A
242
243 [PcdsFixedAtBuild.common, PcdsDynamic.common]
244 #
245 # ARM Architectural Timer
246 #
247 gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034
248
249 # ARM Architectural Timer Interrupt(GIC PPI) numbers
250 gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035
251 gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036
252 gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040
253 gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041
254
255 #
256 # ARM Generic Watchdog
257 #
258
259 gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT64|0x00000007
260 gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT64|0x00000008
261 gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009
262
263 #
264 # ARM Generic Interrupt Controller
265 #
266 gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C
267 # Base address for the GIC Redistributor region that contains the boot CPU
268 gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E
269 gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D
270 gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025
271
272 #
273 # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.
274 # Note that "IO" is just another MMIO range that simulates IO space; there
275 # are no special instructions to access it.
276 #
277 # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are
278 # specific to their containing address spaces. In order to get the physical
279 # address for the CPU, for a given access, the respective translation value
280 # has to be added.
281 #
282 # The translations always have to be initialized like this, using UINT64:
283 #
284 # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space
285 # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space
286 # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space
287 #
288 # PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;
289 # PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;
290 # PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;
291 #
292 # because (a) the target address space (ie. the cpu-physical space) is
293 # 64-bit, and (b) the translation values are meant as offsets for *modular*
294 # arithmetic.
295 #
296 # Accordingly, the translation itself needs to be implemented as:
297 #
298 # UINT64 UntranslatedIoAddress; // input parameter
299 # UINT32 UntranslatedMmio32Address; // input parameter
300 # UINT64 UntranslatedMmio64Address; // input parameter
301 #
302 # UINT64 TranslatedIoAddress; // output parameter
303 # UINT64 TranslatedMmio32Address; // output parameter
304 # UINT64 TranslatedMmio64Address; // output parameter
305 #
306 # TranslatedIoAddress = UntranslatedIoAddress +
307 # PcdPciIoTranslation;
308 # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +
309 # PcdPciMmio32Translation;
310 # TranslatedMmio64Address = UntranslatedMmio64Address +
311 # PcdPciMmio64Translation;
312 #
313 # The modular arithmetic performed in UINT64 ensures that the translation
314 # works correctly regardless of the relation between IoCpuBase and
315 # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and
316 # PcdPciMmio64Base.
317 #
318 gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050
319 gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051
320 gArmTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000052
321 gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053
322 gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054
323 gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000055
324 gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056
325 gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057
326 gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000058
327
328 #
329 # Inclusive range of allowed PCI buses.
330 #
331 gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059
332 gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A