ArmPkg/ArmPkg.dec

   1 #/** @file
   2 # ARM processor package.
   3 #
   4 # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
   5 # Copyright (c) 2011 - 2017, ARM Limited. All rights reserved.
   6 #
   7 #    This program and the accompanying materials
   8 #    are licensed and made available under the terms and conditions of the BSD License
   9 #    which accompanies this distribution. The full text of the license may be found at
  10 #    http://opensource.org/licenses/bsd-license.php
  11 #
  12 #    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13 #    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14 #
  15 #**/
  16
  17 [Defines]
  18   DEC_SPECIFICATION              = 0x00010005
  19   PACKAGE_NAME                   = ArmPkg
  20   PACKAGE_GUID                   = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F
  21   PACKAGE_VERSION                = 0.1
  22
  23 ################################################################################
  24 #
  25 # Include Section - list of Include Paths that are provided by this package.
  26 #                   Comments are used for Keywords and Module Types.
  27 #
  28 # Supported Module Types:
  29 #  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
  30 #
  31 ################################################################################
  32 [Includes.common]
  33   Include                        # Root include for the package
  34
  35 [LibraryClasses.common]
  36   ArmLib|Include/Library/ArmLib.h
  37   ArmMmuLib|Include/Library/ArmMmuLib.h
  38   SemihostLib|Include/Library/Semihosting.h
  39   DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h
  40   ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h
  41   ArmGicArchLib|Include/Library/ArmGicArchLib.h
  42   ArmSvcLib|Include/Library/ArmSvcLib.h
  43
  44 [Guids.common]
  45   gArmTokenSpaceGuid       = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }
  46
  47   ## ARM MPCore table
  48   # Include/Guid/ArmMpCoreInfo.h
  49   gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5,  {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }
  50
  51   gArmGicDxeFileGuid = { 0xde371f7c, 0xdec4, 0x4d21, { 0xad, 0xf1, 0x59, 0x3a, 0xbc, 0xc1, 0x58, 0x82 } }
  52
  53 [Ppis]
  54   ## Include/Ppi/ArmMpCoreInfo.h
  55   gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }
  56
  57 [PcdsFeatureFlag.common]
  58   gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001
  59
  60   # On ARM Architecture with the Security Extension, the address for the
  61   # Vector Table can be mapped anywhere in the memory map. It means we can
  62   # point the Exception Vector Table to its location in CpuDxe.
  63   # By default we copy the Vector Table at  PcdGet64(PcdCpuVectorBaseAddress)
  64   gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022
  65   # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before
  66   # it has been configured by the CPU DXE
  67   gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032
  68
  69   # Define if the spin-table mechanism is used by the secondary cores when booting
  70   # Linux (instead of PSCI)
  71   gArmTokenSpaceGuid.PcdArmLinuxSpinTable|FALSE|BOOLEAN|0x00000033
  72
  73   # Define if the GICv3 controller should use the GICv2 legacy
  74   gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042
  75
  76 [PcdsFeatureFlag.ARM]
  77   # Whether to map normal memory as non-shareable. FALSE is the safe choice, but
  78   # TRUE may be appropriate to fix performance problems if you don't care about
  79   # hardware coherency (i.e., no virtualization or cache coherent DMA)
  80   gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043
  81
  82 [PcdsFixedAtBuild.common]
  83   gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006
  84
  85   # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.
  86   # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
  87   gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024
  88
  89   gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004
  90   gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005
  91
  92   #
  93   # ARM Secure Firmware PCDs
  94   #
  95   gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015
  96   gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016
  97   gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F
  98   gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030
  99
 100   #
 101   # ARM Hypervisor Firmware PCDs
 102   #
 103   gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A
 104   gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B
 105   gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C
 106   gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D
 107
 108   # Use ClusterId + CoreId to identify the PrimaryCore
 109   gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031
 110   # The Primary Core is ClusterId[0] & CoreId[0]
 111   gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037
 112
 113   #
 114   # ARM L2x0 PCDs
 115   #
 116   gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B
 117
 118   #
 119   # ARM Normal (or Non Secure) Firmware PCDs
 120   #
 121   gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C
 122   gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E
 123
 124   #
 125   # Value to add to a host address to obtain a device address, using
 126   # unsigned 64-bit integer arithmetic on both ARM and AArch64. This
 127   # means we can rely on truncation on overflow to specify negative
 128   # offsets.
 129   #
 130   gArmTokenSpaceGuid.PcdArmDmaDeviceOffset|0x0|UINT64|0x0000044
 131
 132 [PcdsFixedAtBuild.common, PcdsPatchableInModule.common]
 133   gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B
 134   gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D
 135
 136 [PcdsFixedAtBuild.ARM]
 137   #
 138   # ARM Security Extension
 139   #
 140
 141   # Secure Configuration Register
 142   # - BIT0 : NS - Non Secure bit
 143   # - BIT1 : IRQ Handler
 144   # - BIT2 : FIQ Handler
 145   # - BIT3 : EA - External Abort
 146   # - BIT4 : FW - F bit writable
 147   # - BIT5 : AW - A bit writable
 148   # - BIT6 : nET - Not Early Termination
 149   # - BIT7 : SCD - Secure Monitor Call Disable
 150   # - BIT8 : HCE - Hyp Call enable
 151   # - BIT9 : SIF - Secure Instruction Fetch
 152   # 0x31 = NS | EA | FW
 153   gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038
 154
 155   # By default we do not do a transition to non-secure mode
 156   gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E
 157
 158   # The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory
 159   gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset|0x4000|UINT32|0x00000020
 160
 161   # If the fixed FDT address is not available, then it should be loaded below the kernel.
 162   # The recommendation from the Linux kernel is to have the FDT below 16KB.
 163   # (see the kernel doc: Documentation/arm/Booting)
 164   gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x4000|UINT32|0x00000023
 165   # The FDT blob must be loaded at a 64bit aligned address.
 166   gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x8|UINT32|0x00000026
 167
 168   # Non Secure Access Control Register
 169   # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality
 170   # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31
 171   # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable
 172   # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable
 173   # 0xC00 = cp10 | cp11
 174   gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039
 175
 176 [PcdsFixedAtBuild.AARCH64]
 177   #
 178   # AArch64 Security Extension
 179   #
 180
 181   # Secure Configuration Register
 182   # - BIT0 : NS - Non Secure bit
 183   # - BIT1 : IRQ Handler
 184   # - BIT2 : FIQ Handler
 185   # - BIT3 : EA - External Abort
 186   # - BIT4 : FW - F bit writable
 187   # - BIT5 : AW - A bit writable
 188   # - BIT6 : nET - Not Early Termination
 189   # - BIT7 : SCD - Secure Monitor Call Disable
 190   # - BIT8 : HCE - Hyp Call enable
 191   # - BIT9 : SIF - Secure Instruction Fetch
 192   # - BIT10: RW -  Register width control for lower exception levels
 193   # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer
 194   # - BIT12: TWI - Trap WFI
 195   # - BIT13: TWE - Trap WFE
 196   # 0x501 = NS | HCE | RW
 197   gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038
 198
 199   # By default we do transition to EL2 non-secure mode with Stack for EL2.
 200   #        Mode Description              Bits
 201   # NS EL2 SP2 all interrupts disabled =  0x3c9
 202   # NS EL1 SP1 all interrupts disabled =  0x3c5
 203   # Other modes include using SP0 or switching to Aarch32, but these are
 204   # not currently supported.
 205   gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E
 206   # If the fixed FDT address is not available, then it should be loaded above the kernel.
 207   # The recommendation from the AArch64 Linux kernel is to have the FDT below 512MB.
 208   # (see the kernel doc: Documentation/arm64/booting.txt)
 209   gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x20000000|UINT32|0x00000023
 210   # The FDT blob must be loaded at a 2MB aligned address.
 211   gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x00200000|UINT32|0x00000026
 212
 213
 214 #
 215 # These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be
 216 # redefined when using UEFI in a context of virtual machine.
 217 #
 218 [PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]
 219
 220   # System Memory (DRAM): These PCDs define the region of in-built system memory
 221   # Some platforms can get DRAM extensions, these additional regions may be
 222   # declared to UEFI using separate resource descriptor HOBs
 223   gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029
 224   gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A
 225
 226 [PcdsFixedAtBuild.common, PcdsDynamic.common]
 227   #
 228   # ARM Architectural Timer
 229   #
 230   gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034
 231
 232   # ARM Architectural Timer Interrupt(GIC PPI) numbers
 233   gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035
 234   gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036
 235   gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040
 236   gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041
 237
 238   #
 239   # ARM Generic Watchdog
 240   #
 241
 242   gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT64|0x00000007
 243   gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT64|0x00000008
 244   gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009
 245
 246   #
 247   # ARM Generic Interrupt Controller
 248   #
 249   gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C
 250   # Base address for the GIC Redistributor region that contains the boot CPU
 251   gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E
 252   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D
 253   gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025
 254
 255   #
 256   # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.
 257   # Note that "IO" is just another MMIO range that simulates IO space; there
 258   # are no special instructions to access it.
 259   #
 260   # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are
 261   # specific to their containing address spaces. In order to get the physical
 262   # address for the CPU, for a given access, the respective translation value
 263   # has to be added.
 264   #
 265   # The translations always have to be initialized like this, using UINT64:
 266   #
 267   #   UINT64 IoCpuBase;     // mapping target in 64-bit cpu-physical space
 268   #   UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space
 269   #   UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space
 270   #
 271   #   PcdPciIoTranslation     = IoCpuBase     - PcdPciIoBase;
 272   #   PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;
 273   #   PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;
 274   #
 275   # because (a) the target address space (ie. the cpu-physical space) is
 276   # 64-bit, and (b) the translation values are meant as offsets for *modular*
 277   # arithmetic.
 278   #
 279   # Accordingly, the translation itself needs to be implemented as:
 280   #
 281   #   UINT64 UntranslatedIoAddress;     // input parameter
 282   #   UINT32 UntranslatedMmio32Address; // input parameter
 283   #   UINT64 UntranslatedMmio64Address; // input parameter
 284   #
 285   #   UINT64 TranslatedIoAddress;       // output parameter
 286   #   UINT64 TranslatedMmio32Address;   // output parameter
 287   #   UINT64 TranslatedMmio64Address;   // output parameter
 288   #
 289   #   TranslatedIoAddress     = UntranslatedIoAddress +
 290   #                             PcdPciIoTranslation;
 291   #   TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +
 292   #                             PcdPciMmio32Translation;
 293   #   TranslatedMmio64Address = UntranslatedMmio64Address +
 294   #                             PcdPciMmio64Translation;
 295   #
 296   #  The modular arithmetic performed in UINT64 ensures that the translation
 297   #  works correctly regardless of the relation between IoCpuBase and
 298   #  PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and
 299   #  PcdPciMmio64Base.
 300   #
 301   gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050
 302   gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051
 303   gArmTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000052
 304   gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053
 305   gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054
 306   gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000055
 307   gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056
 308   gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057
 309   gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000058
 310
 311   #
 312   # Inclusive range of allowed PCI buses.
 313   #
 314   gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059
 315   gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A