ArmPkg/ArmPkg.dec

   1 #/** @file
   2 # ARM processor package.
   3 #
   4 # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
   5 # Copyright (c) 2011 - 2017, ARM Limited. All rights reserved.
   6 #
   7 #    This program and the accompanying materials
   8 #    are licensed and made available under the terms and conditions of the BSD License
   9 #    which accompanies this distribution. The full text of the license may be found at
  10 #    http://opensource.org/licenses/bsd-license.php
  11 #
  12 #    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13 #    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14 #
  15 #**/
  16
  17 [Defines]
  18   DEC_SPECIFICATION              = 0x00010005
  19   PACKAGE_NAME                   = ArmPkg
  20   PACKAGE_GUID                   = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F
  21   PACKAGE_VERSION                = 0.1
  22
  23 ################################################################################
  24 #
  25 # Include Section - list of Include Paths that are provided by this package.
  26 #                   Comments are used for Keywords and Module Types.
  27 #
  28 # Supported Module Types:
  29 #  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
  30 #
  31 ################################################################################
  32 [Includes.common]
  33   Include                        # Root include for the package
  34
  35 [LibraryClasses.common]
  36   ArmLib|Include/Library/ArmLib.h
  37   ArmMmuLib|Include/Library/ArmMmuLib.h
  38   SemihostLib|Include/Library/Semihosting.h
  39   DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h
  40   ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h
  41   ArmGicArchLib|Include/Library/ArmGicArchLib.h
  42   ArmSvcLib|Include/Library/ArmSvcLib.h
  43
  44 [Guids.common]
  45   gArmTokenSpaceGuid       = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }
  46
  47   ## ARM MPCore table
  48   # Include/Guid/ArmMpCoreInfo.h
  49   gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5,  {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }
  50
  51 [Ppis]
  52   ## Include/Ppi/ArmMpCoreInfo.h
  53   gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }
  54
  55 [PcdsFeatureFlag.common]
  56   gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001
  57
  58   # On ARM Architecture with the Security Extension, the address for the
  59   # Vector Table can be mapped anywhere in the memory map. It means we can
  60   # point the Exception Vector Table to its location in CpuDxe.
  61   # By default we copy the Vector Table at  PcdGet64(PcdCpuVectorBaseAddress)
  62   gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022
  63   # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before
  64   # it has been configured by the CPU DXE
  65   gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032
  66
  67   # Define if the spin-table mechanism is used by the secondary cores when booting
  68   # Linux (instead of PSCI)
  69   gArmTokenSpaceGuid.PcdArmLinuxSpinTable|FALSE|BOOLEAN|0x00000033
  70
  71   # Define if the GICv3 controller should use the GICv2 legacy
  72   gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042
  73
  74 [PcdsFeatureFlag.ARM]
  75   # Whether to map normal memory as non-shareable. FALSE is the safe choice, but
  76   # TRUE may be appropriate to fix performance problems if you don't care about
  77   # hardware coherency (i.e., no virtualization or cache coherent DMA)
  78   gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043
  79
  80 [PcdsFixedAtBuild.common]
  81   gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006
  82
  83   # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.
  84   # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
  85   gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024
  86
  87   gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004
  88   gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005
  89
  90   #
  91   # ARM Secure Firmware PCDs
  92   #
  93   gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015
  94   gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016
  95   gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F
  96   gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030
  97
  98   #
  99   # ARM Hypervisor Firmware PCDs
 100   #
 101   gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A
 102   gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B
 103   gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C
 104   gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D
 105
 106   # Use ClusterId + CoreId to identify the PrimaryCore
 107   gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031
 108   # The Primary Core is ClusterId[0] & CoreId[0]
 109   gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037
 110
 111   #
 112   # ARM L2x0 PCDs
 113   #
 114   gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B
 115
 116   #
 117   # ARM Normal (or Non Secure) Firmware PCDs
 118   #
 119   gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C
 120   gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E
 121
 122   #
 123   # Value to add to a host address to obtain a device address, using
 124   # unsigned 64-bit integer arithmetic on both ARM and AArch64. This
 125   # means we can rely on truncation on overflow to specify negative
 126   # offsets.
 127   #
 128   gArmTokenSpaceGuid.PcdArmDmaDeviceOffset|0x0|UINT64|0x0000044
 129
 130 [PcdsFixedAtBuild.common, PcdsPatchableInModule.common]
 131   gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B
 132   gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D
 133
 134 [PcdsFixedAtBuild.ARM]
 135   #
 136   # ARM Security Extension
 137   #
 138
 139   # Secure Configuration Register
 140   # - BIT0 : NS - Non Secure bit
 141   # - BIT1 : IRQ Handler
 142   # - BIT2 : FIQ Handler
 143   # - BIT3 : EA - External Abort
 144   # - BIT4 : FW - F bit writable
 145   # - BIT5 : AW - A bit writable
 146   # - BIT6 : nET - Not Early Termination
 147   # - BIT7 : SCD - Secure Monitor Call Disable
 148   # - BIT8 : HCE - Hyp Call enable
 149   # - BIT9 : SIF - Secure Instruction Fetch
 150   # 0x31 = NS | EA | FW
 151   gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038
 152
 153   # By default we do not do a transition to non-secure mode
 154   gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E
 155
 156   # The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory
 157   gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset|0x4000|UINT32|0x00000020
 158
 159   # If the fixed FDT address is not available, then it should be loaded below the kernel.
 160   # The recommendation from the Linux kernel is to have the FDT below 16KB.
 161   # (see the kernel doc: Documentation/arm/Booting)
 162   gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x4000|UINT32|0x00000023
 163   # The FDT blob must be loaded at a 64bit aligned address.
 164   gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x8|UINT32|0x00000026
 165
 166   # Non Secure Access Control Register
 167   # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality
 168   # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31
 169   # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable
 170   # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable
 171   # 0xC00 = cp10 | cp11
 172   gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039
 173
 174 [PcdsFixedAtBuild.AARCH64]
 175   #
 176   # AArch64 Security Extension
 177   #
 178
 179   # Secure Configuration Register
 180   # - BIT0 : NS - Non Secure bit
 181   # - BIT1 : IRQ Handler
 182   # - BIT2 : FIQ Handler
 183   # - BIT3 : EA - External Abort
 184   # - BIT4 : FW - F bit writable
 185   # - BIT5 : AW - A bit writable
 186   # - BIT6 : nET - Not Early Termination
 187   # - BIT7 : SCD - Secure Monitor Call Disable
 188   # - BIT8 : HCE - Hyp Call enable
 189   # - BIT9 : SIF - Secure Instruction Fetch
 190   # - BIT10: RW -  Register width control for lower exception levels
 191   # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer
 192   # - BIT12: TWI - Trap WFI
 193   # - BIT13: TWE - Trap WFE
 194   # 0x501 = NS | HCE | RW
 195   gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038
 196
 197   # By default we do transition to EL2 non-secure mode with Stack for EL2.
 198   #        Mode Description              Bits
 199   # NS EL2 SP2 all interrupts disabled =  0x3c9
 200   # NS EL1 SP1 all interrupts disabled =  0x3c5
 201   # Other modes include using SP0 or switching to Aarch32, but these are
 202   # not currently supported.
 203   gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E
 204   # If the fixed FDT address is not available, then it should be loaded above the kernel.
 205   # The recommendation from the AArch64 Linux kernel is to have the FDT below 512MB.
 206   # (see the kernel doc: Documentation/arm64/booting.txt)
 207   gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x20000000|UINT32|0x00000023
 208   # The FDT blob must be loaded at a 2MB aligned address.
 209   gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x00200000|UINT32|0x00000026
 210
 211
 212 #
 213 # These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be
 214 # redefined when using UEFI in a context of virtual machine.
 215 #
 216 [PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]
 217
 218   # System Memory (DRAM): These PCDs define the region of in-built system memory
 219   # Some platforms can get DRAM extensions, these additional regions may be
 220   # declared to UEFI using separate resource descriptor HOBs
 221   gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029
 222   gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A
 223
 224 [PcdsFixedAtBuild.common, PcdsDynamic.common]
 225   #
 226   # ARM Architectural Timer
 227   #
 228   gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034
 229
 230   # ARM Architectural Timer Interrupt(GIC PPI) numbers
 231   gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035
 232   gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036
 233   gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040
 234   gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041
 235
 236   #
 237   # ARM Generic Watchdog
 238   #
 239
 240   gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT64|0x00000007
 241   gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT64|0x00000008
 242   gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009
 243
 244   #
 245   # ARM Generic Interrupt Controller
 246   #
 247   gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C
 248   # Base address for the GIC Redistributor region that contains the boot CPU
 249   gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E
 250   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D
 251   gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025
 252
 253   #
 254   # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.
 255   # Note that "IO" is just another MMIO range that simulates IO space; there
 256   # are no special instructions to access it.
 257   #
 258   # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are
 259   # specific to their containing address spaces. In order to get the physical
 260   # address for the CPU, for a given access, the respective translation value
 261   # has to be added.
 262   #
 263   # The translations always have to be initialized like this, using UINT64:
 264   #
 265   #   UINT64 IoCpuBase;     // mapping target in 64-bit cpu-physical space
 266   #   UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space
 267   #   UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space
 268   #
 269   #   PcdPciIoTranslation     = IoCpuBase     - PcdPciIoBase;
 270   #   PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;
 271   #   PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;
 272   #
 273   # because (a) the target address space (ie. the cpu-physical space) is
 274   # 64-bit, and (b) the translation values are meant as offsets for *modular*
 275   # arithmetic.
 276   #
 277   # Accordingly, the translation itself needs to be implemented as:
 278   #
 279   #   UINT64 UntranslatedIoAddress;     // input parameter
 280   #   UINT32 UntranslatedMmio32Address; // input parameter
 281   #   UINT64 UntranslatedMmio64Address; // input parameter
 282   #
 283   #   UINT64 TranslatedIoAddress;       // output parameter
 284   #   UINT64 TranslatedMmio32Address;   // output parameter
 285   #   UINT64 TranslatedMmio64Address;   // output parameter
 286   #
 287   #   TranslatedIoAddress     = UntranslatedIoAddress +
 288   #                             PcdPciIoTranslation;
 289   #   TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +
 290   #                             PcdPciMmio32Translation;
 291   #   TranslatedMmio64Address = UntranslatedMmio64Address +
 292   #                             PcdPciMmio64Translation;
 293   #
 294   #  The modular arithmetic performed in UINT64 ensures that the translation
 295   #  works correctly regardless of the relation between IoCpuBase and
 296   #  PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and
 297   #  PcdPciMmio64Base.
 298   #
 299   gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050
 300   gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051
 301   gArmTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000052
 302   gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053
 303   gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054
 304   gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000055
 305   gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056
 306   gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057
 307   gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000058
 308
 309   #
 310   # Inclusive range of allowed PCI buses.
 311   #
 312   gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059
 313   gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A