ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.c

   1 /** @file
   2
   3   Copyright (c) 2011-2012, ARM Limited. All rights reserved.
   4
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #include <Base.h>
  16 #include <Library/ArmLib.h>
  17 #include <Library/ArmCpuLib.h>
  18 #include <Library/ArmV7ArchTimerLib.h>
  19 #include <Library/DebugLib.h>
  20 #include <Library/IoLib.h>
  21 #include <Library/PcdLib.h>
  22
  23 #include <Chipset/ArmCortexA15.h>
  24
  25 VOID
  26 ArmCpuSetup (
  27   IN  UINTN         MpId
  28   )
  29 {
  30   // Check if Architectural Timer frequency is valid number (should not be 0)
  31   ASSERT (PcdGet32 (PcdArmArchTimerFreqInHz));
  32   ASSERT(ArmIsArchTimerImplemented () != 0);
  33
  34   // Enable SWP instructions
  35   ArmEnableSWPInstruction ();
  36
  37   // Enable program flow prediction, if supported.
  38   ArmEnableBranchPrediction ();
  39
  40   // Note: System Counter frequency can only be set in Secure privileged mode,
  41   // if security extensions are implemented.
  42   ArmArchTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));
  43
  44   if (ArmIsMpCore()) {
  45     // Turn on SMP coherency
  46     ArmSetAuxCrBit (A15_FEATURE_SMP);
  47   }
  48
  49 }
  50
  51
  52 VOID
  53 ArmCpuSetupSmpNonSecure (
  54   IN  UINTN         MpId
  55   )
  56 {
  57   /*// Make the SCU accessible in Non Secure world
  58   if (ArmPlatformIsPrimaryCore (MpId)) {
  59     ScuBase = ArmGetScuBaseAddress();
  60
  61     // Allow NS access to SCU register
  62     MmioOr32 (ScuBase + A9_SCU_SACR_OFFSET, 0xf);
  63     // Allow NS access to Private Peripherals
  64     MmioOr32 (ScuBase + A9_SCU_SSACR_OFFSET, 0xfff);
  65   }*/
  66 }