ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.c

   1 /** @file
   2
   3   Copyright (c) 2011-2012, ARM Limited. All rights reserved.
   4
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #include <Base.h>
  16 #include <Library/ArmLib.h>
  17 #include <Library/ArmCpuLib.h>
  18 #include <Library/ArmGenericTimerCounterLib.h>
  19 #include <Library/DebugLib.h>
  20 #include <Library/PcdLib.h>
  21
  22 #include <Chipset/ArmV7.h>
  23
  24 #define A15_FEATURE_SMP     (1<<6)
  25
  26 VOID
  27 ArmCpuSetup (
  28   IN  UINTN         MpId
  29   )
  30 {
  31   // Check if Architectural Timer frequency is valid number (should not be 0)
  32   ASSERT (PcdGet32 (PcdArmArchTimerFreqInHz));
  33   ASSERT(ArmIsArchTimerImplemented () != 0);
  34
  35   // Enable SWP instructions
  36   ArmEnableSWPInstruction ();
  37
  38   // Enable program flow prediction, if supported.
  39   ArmEnableBranchPrediction ();
  40
  41   // Note: System Counter frequency can only be set in Secure privileged mode,
  42   // if security extensions are implemented.
  43   ArmGenericTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));
  44
  45   if (ArmIsMpCore()) {
  46     // Turn on SMP coherency
  47     ArmSetAuxCrBit (A15_FEATURE_SMP);
  48   }
  49
  50 }
  51
  52
  53 VOID
  54 ArmCpuSetupSmpNonSecure (
  55   IN  UINTN         MpId
  56   )
  57 {
  58   /*// Make the SCU accessible in Non Secure world
  59   if (ArmPlatformIsPrimaryCore (MpId)) {
  60     ScuBase = ArmGetScuBaseAddress();
  61
  62     // Allow NS access to SCU register
  63     MmioOr32 (ScuBase + A9_SCU_SACR_OFFSET, 0xf);
  64     // Allow NS access to Private Peripherals
  65     MmioOr32 (ScuBase + A9_SCU_SSACR_OFFSET, 0xfff);
  66   }*/
  67 }