3 Copyright (c) 2011-2014, ARM Limited. All rights reserved.
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #include <Library/ArmLib.h>
17 #include <Library/ArmCpuLib.h>
18 #include <Library/ArmGenericTimerCounterLib.h>
19 #include <Library/DebugLib.h>
20 #include <Library/PcdLib.h>
22 #include <Chipset/ArmCortexA5x.h>
29 // Check if Architectural Timer frequency is valid number (should not be 0)
30 ASSERT (PcdGet32 (PcdArmArchTimerFreqInHz
));
31 ASSERT (ArmIsArchTimerImplemented () != 0);
33 // Note: System Counter frequency can only be set in Secure privileged mode,
34 // if security extensions are implemented.
35 ArmGenericTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz
));
38 // Turn on SMP coherency
39 ArmSetCpuExCrBit (A5X_FEATURE_SMP
);
43 // If CPU is CortexA57 r0p0 apply Errata workarounds
45 if ((ArmReadMidr () & ((ARM_CPU_TYPE_MASK
<< 4) | ARM_CPU_REV_MASK
)) ==
46 ((ARM_CPU_TYPE_A57
<< 4) | ARM_CPU_REV(0,0))) {
48 // Errata 806969: DisableLoadStoreWB (1ULL << 49)
49 // Errata 813420: Execute Data Cache clean as Data Cache clean/invalidate (1ULL << 44)
50 // Errata 814670: disable DMB nullification (1ULL << 58)
51 ArmSetCpuActlrBit ( (1ULL << 49) | (1ULL << 44) | (1ULL << 58) );
56 ArmCpuSetupSmpNonSecure (
69 Value
= ArmReadCpuExCr ();
71 ArmWriteCpuExCr (Value
);
81 Value
= ArmReadCpuExCr ();
83 ArmWriteCpuExCr (Value
);