ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.c

   1 /** @file
   2
   3   Copyright (c) 2011-2012, ARM Limited. All rights reserved.
   4
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #include <Base.h>
  16 #include <Library/ArmLib.h>
  17 #include <Library/ArmCpuLib.h>
  18 #include <Library/ArmPlatformLib.h>
  19 #include <Library/IoLib.h>
  20 #include <Library/PcdLib.h>
  21
  22 #include <Chipset/ArmCortexA9.h>
  23
  24 VOID
  25 ArmEnableScu (
  26   VOID
  27   )
  28 {
  29   INTN          ScuBase;
  30
  31   ScuBase = ArmGetScuBaseAddress();
  32
  33   // Invalidate all: write -1 to SCU Invalidate All register
  34   MmioWrite32(ScuBase + A9_SCU_INVALL_OFFSET, 0xffffffff);
  35   // Enable SCU
  36   MmioWrite32(ScuBase + A9_SCU_CONTROL_OFFSET, 0x1);
  37 }
  38
  39 VOID
  40 ArmCpuSetup (
  41   IN  UINTN         MpId
  42   )
  43 {
  44   // Enable SWP instructions
  45   ArmEnableSWPInstruction ();
  46
  47   // Enable program flow prediction, if supported.
  48   ArmEnableBranchPrediction ();
  49
  50   // If MPCore then Enable the SCU
  51   if (ArmIsMpCore()) {
  52     // Signals the Cortex-A9 processor is taking part in coherency
  53     ArmSetAuxCrBit (A9_FEATURE_SMP);
  54
  55     ArmEnableScu ();
  56   }
  57 }
  58
  59
  60 VOID
  61 ArmCpuSetupSmpNonSecure (
  62   IN  UINTN         MpId
  63   )
  64 {
  65   INTN          ScuBase;
  66
  67   // Make the SCU accessible in Non Secure world
  68   if (ArmPlatformIsPrimaryCore (MpId)) {
  69     ScuBase = ArmGetScuBaseAddress();
  70
  71     // Allow NS access to SCU register
  72     MmioOr32 (ScuBase + A9_SCU_SACR_OFFSET, 0xf);
  73     // Allow NS access to Private Peripherals
  74     MmioOr32 (ScuBase + A9_SCU_SSACR_OFFSET, 0xfff);
  75   }
  76 }