ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.c

   1 /** @file
   2
   3   Copyright (c) 2011-2012, ARM Limited. All rights reserved.
   4
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #include <Base.h>
  16 #include <Library/ArmLib.h>
  17 #include <Library/ArmCpuLib.h>
  18 #include <Library/IoLib.h>
  19 #include <Library/PcdLib.h>
  20
  21 #include <Chipset/ArmCortexA9.h>
  22
  23 VOID
  24 ArmEnableScu (
  25   VOID
  26   )
  27 {
  28   INTN          ScuBase;
  29
  30   ScuBase = ArmGetScuBaseAddress();
  31
  32   // Invalidate all: write -1 to SCU Invalidate All register
  33   MmioWrite32(ScuBase + A9_SCU_INVALL_OFFSET, 0xffffffff);
  34   // Enable SCU
  35   MmioWrite32(ScuBase + A9_SCU_CONTROL_OFFSET, 0x1);
  36 }
  37
  38 VOID
  39 ArmCpuSetup (
  40   IN  UINTN         MpId
  41   )
  42 {
  43   // Enable SWP instructions
  44   ArmEnableSWPInstruction ();
  45
  46   // Enable program flow prediction, if supported.
  47   ArmEnableBranchPrediction ();
  48
  49   // If MPCore then Enable the SCU
  50   if (ArmIsMpCore()) {
  51     // Signals the Cortex-A9 processor is taking part in coherency
  52     ArmSetAuxCrBit (A9_FEATURE_SMP);
  53
  54     ArmEnableScu ();
  55   }
  56 }
  57
  58
  59 VOID
  60 ArmCpuSetupSmpNonSecure (
  61   IN  UINTN         MpId
  62   )
  63 {
  64   INTN          ScuBase;
  65
  66   // Make the SCU accessible in Non Secure world
  67   if (IS_PRIMARY_CORE(MpId)) {
  68     ScuBase = ArmGetScuBaseAddress();
  69
  70     // Allow NS access to SCU register
  71     MmioOr32 (ScuBase + A9_SCU_SACR_OFFSET, 0xf);
  72     // Allow NS access to Private Peripherals
  73     MmioOr32 (ScuBase + A9_SCU_SSACR_OFFSET, 0xfff);
  74   }
  75 }