ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.asm

   1 //------------------------------------------------------------------------------
   2 //
   3 // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4 //
   5 // This program and the accompanying materials
   6 // are licensed and made available under the terms and conditions of the BSD License
   7 // which accompanies this distribution.  The full text of the license may be found at
   8 // http://opensource.org/licenses/bsd-license.php
   9 //
  10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 //
  13 //------------------------------------------------------------------------------
  14
  15   EXPORT  ExceptionHandlersStart
  16   EXPORT  ExceptionHandlersEnd
  17   EXPORT  CommonExceptionEntry
  18   EXPORT  AsmCommonExceptionEntry
  19   IMPORT  CommonCExceptionHandler
  20
  21   PRESERVE8
  22   AREA  DxeExceptionHandlers, CODE, READONLY
  23
  24 ExceptionHandlersStart
  25
  26 Reset
  27   b   ResetEntry
  28
  29 UndefinedInstruction
  30   b   UndefinedInstructionEntry
  31
  32 SoftwareInterrupt
  33   b   SoftwareInterruptEntry
  34
  35 PrefetchAbort
  36   b   PrefetchAbortEntry
  37
  38 DataAbort
  39   b   DataAbortEntry
  40
  41 ReservedException
  42   b   ReservedExceptionEntry
  43
  44 Irq
  45   b   IrqEntry
  46
  47 Fiq
  48   b   FiqEntry
  49
  50 ResetEntry
  51   stmfd     SP!,{R0-R1}
  52   mov       R0,#0
  53   ldr       R1,CommonExceptionEntry
  54   bx        R1
  55
  56 UndefinedInstructionEntry
  57   stmfd     SP!,{R0-R1}
  58   mov       R0,#1
  59   ldr       R1,CommonExceptionEntry
  60   bx        R1
  61
  62 SoftwareInterruptEntry
  63   stmfd     SP!,{R0-R1}
  64   mov       R0,#2
  65   ldr       R1,CommonExceptionEntry
  66   bx        R1
  67
  68 PrefetchAbortEntry
  69   stmfd     SP!,{R0-R1}
  70   mov       R0,#3
  71   SUB       LR,LR,#4
  72   ldr       R1,CommonExceptionEntry
  73   bx        R1
  74
  75 DataAbortEntry
  76   stmfd     SP!,{R0-R1}
  77   mov       R0,#4
  78   SUB       LR,LR,#8
  79   ldr       R1,CommonExceptionEntry
  80   bx        R1
  81
  82 ReservedExceptionEntry
  83   stmfd     SP!,{R0-R1}
  84   mov       R0,#5
  85   ldr       R1,CommonExceptionEntry
  86   bx        R1
  87
  88 IrqEntry
  89   stmfd     SP!,{R0-R1}
  90   mov       R0,#6
  91   SUB       LR,LR,#4
  92   ldr       R1,CommonExceptionEntry
  93   bx        R1
  94
  95 FiqEntry
  96   stmfd     SP!,{R0-R1}
  97   mov       R0,#7
  98   SUB       LR,LR,#4
  99   ldr       R1,CommonExceptionEntry
 100   bx        R1
 101
 102 CommonExceptionEntry
 103   dcd       0x12345678
 104
 105 ExceptionHandlersEnd
 106
 107 AsmCommonExceptionEntry
 108   mrc       p15, 0, r1, c6, c0, 2   ; Read IFAR
 109   stmfd     SP!,{R1}                ; Store the IFAR
 110
 111   mrc       p15, 0, r1, c5, c0, 1   ; Read IFSR
 112   stmfd     SP!,{R1}                ; Store the IFSR
 113
 114   mrc       p15, 0, r1, c6, c0, 0   ; Read DFAR
 115   stmfd     SP!,{R1}                ; Store the DFAR
 116
 117   mrc       p15, 0, r1, c5, c0, 0   ; Read DFSR
 118   stmfd     SP!,{R1}                ; Store the DFSR
 119
 120   mrs       R1,SPSR                 ; Read SPSR (which is the pre-exception CPSR)
 121   stmfd     SP!,{R1}                ; Store the SPSR
 122
 123   stmfd     SP!,{LR}                ; Store the link register (which is the pre-exception PC)
 124   stmfd     SP,{SP,LR}^             ; Store user/system mode stack pointer and link register
 125   nop                               ; Required by ARM architecture
 126   SUB       SP,SP,#0x08             ; Adjust stack pointer
 127   stmfd     SP!,{R2-R12}            ; Store general purpose registers
 128
 129   ldr       R3,[SP,#0x50]           ; Read saved R1 from the stack (it was saved by the exception entry routine)
 130   ldr       R2,[SP,#0x4C]           ; Read saved R0 from the stack (it was saved by the exception entry routine)
 131   stmfd     SP!,{R2-R3}             ; Store general purpose registers R0 and R1
 132
 133   mov       R1,SP                   ; Prepare System Context pointer as an argument for the exception handler
 134
 135   sub       SP,SP,#4                ; Adjust SP to preserve 8-byte alignment
 136   blx       CommonCExceptionHandler ; Call exception handler
 137   add       SP,SP,#4                ; Adjust SP back to where we were
 138
 139   ldr       R2,[SP,#0x40]           ; Load CPSR from context, in case it has changed
 140   MSR       SPSR_cxsf,R2            ; Store it back to the SPSR to be restored when exiting this handler
 141
 142   ldmfd     SP!,{R0-R12}            ; Restore general purpose registers
 143   ldm       SP,{SP,LR}^             ; Restore user/system mode stack pointer and link register
 144   nop                               ; Required by ARM architecture
 145   add       SP,SP,#0x08             ; Adjust stack pointer
 146   ldmfd     SP!,{LR}                ; Restore the link register (which is the pre-exception PC)
 147   add       SP,SP,#0x1C             ; Clear out the remaining stack space
 148   movs      PC,LR                   ; Return from exception
 149
 150   END
 151
 152