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1 /** @file
2
3 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
4
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #include "CpuDxe.h"
16
17 //FIXME: Will not compile on non-ARMv7 builds
18 #include <Chipset/ArmV7.h>
19
20 VOID
21 ExceptionHandlersStart (
22 VOID
23 );
24
25 VOID
26 ExceptionHandlersEnd (
27 VOID
28 );
29
30 VOID
31 CommonExceptionEntry (
32 VOID
33 );
34
35 VOID
36 AsmCommonExceptionEntry (
37 VOID
38 );
39
40
41 EFI_EXCEPTION_CALLBACK gExceptionHandlers[MAX_ARM_EXCEPTION + 1];
42 EFI_EXCEPTION_CALLBACK gDebuggerExceptionHandlers[MAX_ARM_EXCEPTION + 1];
43
44
45
46 /**
47 This function registers and enables the handler specified by InterruptHandler for a processor
48 interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the
49 handler for the processor interrupt or exception type specified by InterruptType is uninstalled.
50 The installed handler is called once for each processor interrupt or exception.
51
52 @param InterruptType A pointer to the processor's current interrupt state. Set to TRUE if interrupts
53 are enabled and FALSE if interrupts are disabled.
54 @param InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called
55 when a processor interrupt occurs. If this parameter is NULL, then the handler
56 will be uninstalled.
57
58 @retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled.
59 @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was
60 previously installed.
61 @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not
62 previously installed.
63 @retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported.
64
65 **/
66 EFI_STATUS
67 RegisterInterruptHandler (
68 IN EFI_EXCEPTION_TYPE InterruptType,
69 IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
70 )
71 {
72 if (InterruptType > MAX_ARM_EXCEPTION) {
73 return EFI_UNSUPPORTED;
74 }
75
76 if ((InterruptHandler != NULL) && (gExceptionHandlers[InterruptType] != NULL)) {
77 return EFI_ALREADY_STARTED;
78 }
79
80 gExceptionHandlers[InterruptType] = InterruptHandler;
81
82 return EFI_SUCCESS;
83 }
84
85
86
87
88 VOID
89 EFIAPI
90 CommonCExceptionHandler (
91 IN EFI_EXCEPTION_TYPE ExceptionType,
92 IN OUT EFI_SYSTEM_CONTEXT SystemContext
93 )
94 {
95
96 if (ExceptionType <= MAX_ARM_EXCEPTION) {
97 if (gExceptionHandlers[ExceptionType]) {
98 gExceptionHandlers[ExceptionType] (ExceptionType, SystemContext);
99 return;
100 }
101 } else {
102 DEBUG ((EFI_D_ERROR, "Unknown exception type %d from %08x\n", ExceptionType, SystemContext.SystemContextArm->PC));
103 ASSERT (FALSE);
104 }
105
106 if (ExceptionType == EXCEPT_ARM_SOFTWARE_INTERRUPT) {
107 //
108 // ARM JTAG debuggers some times use this vector, so it is not an error to get one
109 //
110 return;
111 }
112
113 DefaultExceptionHandler (ExceptionType, SystemContext);
114 }
115
116
117
118 EFI_STATUS
119 InitializeExceptions (
120 IN EFI_CPU_ARCH_PROTOCOL *Cpu
121 )
122 {
123 EFI_STATUS Status;
124 UINTN Offset;
125 UINTN Length;
126 UINTN Index;
127 BOOLEAN IrqEnabled;
128 BOOLEAN FiqEnabled;
129 EFI_PHYSICAL_ADDRESS Base;
130 UINT32 *VectorBase;
131
132 Status = EFI_SUCCESS;
133 //
134 // Disable interrupts
135 //
136 Cpu->GetInterruptState (Cpu, &IrqEnabled);
137 Cpu->DisableInterrupt (Cpu);
138
139 //
140 // EFI does not use the FIQ, but a debugger might so we must disable
141 // as we take over the exception vectors.
142 //
143 FiqEnabled = ArmGetFiqState ();
144 ArmDisableFiq ();
145
146 if (FeaturePcdGet(PcdRelocateVectorTable) == TRUE) {
147 //
148 // Copy an implementation of the ARM exception vectors to PcdCpuVectorBaseAddress.
149 //
150 Length = (UINTN)ExceptionHandlersEnd - (UINTN)ExceptionHandlersStart;
151
152 //
153 // Reserve space for the exception handlers
154 //
155 Base = (EFI_PHYSICAL_ADDRESS)PcdGet32 (PcdCpuVectorBaseAddress);
156 VectorBase = (UINT32 *)(UINTN)Base;
157 Status = gBS->AllocatePages (AllocateAddress, EfiBootServicesCode, EFI_SIZE_TO_PAGES (Length), &Base);
158 // If the request was for memory that's not in the memory map (which is often the case for 0x00000000
159 // on embedded systems, for example, we don't want to hang up. So we'll check here for a status of
160 // EFI_NOT_FOUND, and continue in that case.
161 if (EFI_ERROR(Status) && (Status != EFI_NOT_FOUND)) {
162 ASSERT_EFI_ERROR (Status);
163 }
164
165 // Save existing vector table, in case debugger is already hooked in
166 CopyMem ((VOID *)gDebuggerExceptionHandlers, (VOID *)VectorBase, sizeof (gDebuggerExceptionHandlers));
167
168 // Copy our assembly code into the page that contains the exception vectors.
169 CopyMem ((VOID *)VectorBase, (VOID *)ExceptionHandlersStart, Length);
170
171 //
172 // Patch in the common Assembly exception handler
173 //
174 Offset = (UINTN)CommonExceptionEntry - (UINTN)ExceptionHandlersStart;
175 *(UINTN *) ((UINT8 *)(UINTN)PcdGet32 (PcdCpuVectorBaseAddress) + Offset) = (UINTN)AsmCommonExceptionEntry;
176
177 //
178 // Initialize the C entry points for interrupts
179 //
180 for (Index = 0; Index <= MAX_ARM_EXCEPTION; Index++) {
181 if ((gDebuggerExceptionHandlers[Index] == 0) || (gDebuggerExceptionHandlers[Index] == (VOID *)(UINTN)0xEAFFFFFE)) {
182 // Exception handler contains branch to vector location (jmp $) so no handler
183 // NOTE: This code assumes vectors are ARM and not Thumb code
184 Status = RegisterInterruptHandler (Index, NULL);
185 ASSERT_EFI_ERROR (Status);
186 } else {
187 // If the debugger has alread hooked put its vector back
188 VectorBase[Index] = (UINT32)(UINTN)gDebuggerExceptionHandlers[Index];
189 }
190 }
191
192 // Flush Caches since we updated executable stuff
193 InvalidateInstructionCacheRange ((VOID *)PcdGet32(PcdCpuVectorBaseAddress), Length);
194
195 //Note: On ARM processor with the Security Extension, the Vector Table can be located anywhere in the memory.
196 // The Vector Base Address Register defines the location
197 ArmWriteVBar(PcdGet32(PcdCpuVectorBaseAddress));
198 } else {
199 // We do not copy the Exception Table at PcdGet32(PcdCpuVectorBaseAddress). We just set Vector Base Address to point into CpuDxe code.
200 ArmWriteVBar((UINT32)ExceptionHandlersStart);
201 }
202
203 if (FiqEnabled) {
204 ArmEnableFiq ();
205 }
206
207 if (IrqEnabled) {
208 //
209 // Restore interrupt state
210 //
211 Status = Cpu->EnableInterrupt (Cpu);
212 }
213
214 return Status;
215 }