ArmPkg/Drivers/CpuDxe/Mmu.c

   1 /*++
   2
   3 Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>
   4 Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>
   5
   6 This program and the accompanying materials
   7 are licensed and made available under the terms and conditions of the BSD License
   8 which accompanies this distribution.  The full text of the license may be found at
   9 http://opensource.org/licenses/bsd-license.php
  10
  11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14
  15 --*/
  16
  17 #include "CpuDxe.h"
  18 //FIXME: Remove this ARMv7 specific header
  19 #include <Chipset/ArmV7.h>
  20
  21 // First Level Descriptors
  22 typedef UINT32    ARM_FIRST_LEVEL_DESCRIPTOR;
  23
  24 // Second Level Descriptors
  25 typedef UINT32    ARM_PAGE_TABLE_ENTRY;
  26
  27 EFI_STATUS
  28 SectionToGcdAttributes (
  29   IN  UINT32  SectionAttributes,
  30   OUT UINT64  *GcdAttributes
  31   )
  32 {
  33   *GcdAttributes = 0;
  34
  35   // determine cacheability attributes
  36   switch(SectionAttributes & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) {
  37     case TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED:
  38       *GcdAttributes |= EFI_MEMORY_UC;
  39       break;
  40     case TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE:
  41       *GcdAttributes |= EFI_MEMORY_UC;
  42       break;
  43     case TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC:
  44       *GcdAttributes |= EFI_MEMORY_WT;
  45       break;
  46     case TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_NO_ALLOC:
  47       *GcdAttributes |= EFI_MEMORY_WB;
  48       break;
  49     case TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE:
  50       *GcdAttributes |= EFI_MEMORY_WC;
  51       break;
  52     case TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC:
  53       *GcdAttributes |= EFI_MEMORY_WB;
  54       break;
  55     case TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_SHAREABLE_DEVICE:
  56       *GcdAttributes |= EFI_MEMORY_UC;
  57       break;
  58     default:
  59       return EFI_UNSUPPORTED;
  60   }
  61
  62   // determine protection attributes
  63   switch(SectionAttributes & TT_DESCRIPTOR_SECTION_AP_MASK) {
  64     case TT_DESCRIPTOR_SECTION_AP_NO_NO: // no read, no write
  65       //*GcdAttributes |= EFI_MEMORY_WP | EFI_MEMORY_RP;
  66       break;
  67
  68     case TT_DESCRIPTOR_SECTION_AP_RW_NO:
  69     case TT_DESCRIPTOR_SECTION_AP_RW_RW:
  70       // normal read/write access, do not add additional attributes
  71       break;
  72
  73     // read only cases map to write-protect
  74     case TT_DESCRIPTOR_SECTION_AP_RO_NO:
  75     case TT_DESCRIPTOR_SECTION_AP_RO_RO:
  76       *GcdAttributes |= EFI_MEMORY_WP;
  77       break;
  78
  79     default:
  80       return EFI_UNSUPPORTED;
  81   }
  82
  83   // now process eXectue Never attribute
  84   if ((SectionAttributes & TT_DESCRIPTOR_SECTION_XN_MASK) != 0 ) {
  85     *GcdAttributes |= EFI_MEMORY_XP;
  86   }
  87
  88   return EFI_SUCCESS;
  89 }
  90
  91 /**
  92   Searches memory descriptors covered by given memory range.
  93
  94   This function searches into the Gcd Memory Space for descriptors
  95   (from StartIndex to EndIndex) that contains the memory range
  96   specified by BaseAddress and Length.
  97
  98   @param  MemorySpaceMap       Gcd Memory Space Map as array.
  99   @param  NumberOfDescriptors  Number of descriptors in map.
 100   @param  BaseAddress          BaseAddress for the requested range.
 101   @param  Length               Length for the requested range.
 102   @param  StartIndex           Start index into the Gcd Memory Space Map.
 103   @param  EndIndex             End index into the Gcd Memory Space Map.
 104
 105   @retval EFI_SUCCESS          Search successfully.
 106   @retval EFI_NOT_FOUND        The requested descriptors does not exist.
 107
 108 **/
 109 EFI_STATUS
 110 SearchGcdMemorySpaces (
 111   IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR     *MemorySpaceMap,
 112   IN UINTN                               NumberOfDescriptors,
 113   IN EFI_PHYSICAL_ADDRESS                BaseAddress,
 114   IN UINT64                              Length,
 115   OUT UINTN                              *StartIndex,
 116   OUT UINTN                              *EndIndex
 117   )
 118 {
 119   UINTN           Index;
 120
 121   *StartIndex = 0;
 122   *EndIndex   = 0;
 123   for (Index = 0; Index < NumberOfDescriptors; Index++) {
 124     if (BaseAddress >= MemorySpaceMap[Index].BaseAddress &&
 125         BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
 126       *StartIndex = Index;
 127     }
 128     if (BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress &&
 129         BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
 130       *EndIndex = Index;
 131       return EFI_SUCCESS;
 132     }
 133   }
 134   return EFI_NOT_FOUND;
 135 }
 136
 137
 138 /**
 139   Sets the attributes for a specified range in Gcd Memory Space Map.
 140
 141   This function sets the attributes for a specified range in
 142   Gcd Memory Space Map.
 143
 144   @param  MemorySpaceMap       Gcd Memory Space Map as array
 145   @param  NumberOfDescriptors  Number of descriptors in map
 146   @param  BaseAddress          BaseAddress for the range
 147   @param  Length               Length for the range
 148   @param  Attributes           Attributes to set
 149
 150   @retval EFI_SUCCESS          Memory attributes set successfully
 151   @retval EFI_NOT_FOUND        The specified range does not exist in Gcd Memory Space
 152
 153 **/
 154 EFI_STATUS
 155 SetGcdMemorySpaceAttributes (
 156   IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR     *MemorySpaceMap,
 157   IN UINTN                               NumberOfDescriptors,
 158   IN EFI_PHYSICAL_ADDRESS                BaseAddress,
 159   IN UINT64                              Length,
 160   IN UINT64                              Attributes
 161   )
 162 {
 163   EFI_STATUS            Status;
 164   UINTN                 Index;
 165   UINTN                 StartIndex;
 166   UINTN                 EndIndex;
 167   EFI_PHYSICAL_ADDRESS  RegionStart;
 168   UINT64                RegionLength;
 169
 170   //
 171   // Get all memory descriptors covered by the memory range
 172   //
 173   Status = SearchGcdMemorySpaces (
 174              MemorySpaceMap,
 175              NumberOfDescriptors,
 176              BaseAddress,
 177              Length,
 178              &StartIndex,
 179              &EndIndex
 180              );
 181   if (EFI_ERROR (Status)) {
 182     return Status;
 183   }
 184
 185   //
 186   // Go through all related descriptors and set attributes accordingly
 187   //
 188   for (Index = StartIndex; Index <= EndIndex; Index++) {
 189     if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
 190       continue;
 191     }
 192     //
 193     // Calculate the start and end address of the overlapping range
 194     //
 195     if (BaseAddress >= MemorySpaceMap[Index].BaseAddress) {
 196       RegionStart = BaseAddress;
 197     } else {
 198       RegionStart = MemorySpaceMap[Index].BaseAddress;
 199     }
 200     if (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
 201       RegionLength = BaseAddress + Length - RegionStart;
 202     } else {
 203       RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;
 204     }
 205     //
 206     // Set memory attributes according to MTRR attribute and the original attribute of descriptor
 207     //
 208     gDS->SetMemorySpaceAttributes (
 209            RegionStart,
 210            RegionLength,
 211            (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes)
 212            );
 213   }
 214
 215   return EFI_SUCCESS;
 216 }
 217
 218
 219 EFI_STATUS
 220 SyncCacheConfig (
 221   IN  EFI_CPU_ARCH_PROTOCOL *CpuProtocol
 222   )
 223 {
 224   EFI_STATUS                          Status;
 225   UINT32                              i;
 226   UINT32                              Descriptor;
 227   UINT32                              SectionAttributes;
 228   EFI_PHYSICAL_ADDRESS                NextRegionBase;
 229   UINT64                              NextRegionLength;
 230   UINT64                              GcdAttributes;
 231   UINT32                              NextRegionAttributes = 0;
 232   volatile ARM_FIRST_LEVEL_DESCRIPTOR   *FirstLevelTable;
 233   UINTN                               NumberOfDescriptors;
 234   EFI_GCD_MEMORY_SPACE_DESCRIPTOR     *MemorySpaceMap;
 235
 236
 237   DEBUG ((EFI_D_PAGE, "SyncCacheConfig()\n"));
 238
 239   // This code assumes MMU is enabled and filed with section translations
 240   ASSERT (ArmMmuEnabled ());
 241
 242   //
 243   // Get the memory space map from GCD
 244   //
 245   MemorySpaceMap = NULL;
 246   Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
 247   ASSERT_EFI_ERROR (Status);
 248
 249
 250   // The GCD implementation maintains its own copy of the state of memory space attributes.  GCD needs
 251   // to know what the initial memory space attributes are.  The CPU Arch. Protocol does not provide a
 252   // GetMemoryAttributes function for GCD to get this so we must resort to calling GCD (as if we were
 253   // a client) to update its copy of the attributes.  This is bad architecture and should be replaced
 254   // with a way for GCD to query the CPU Arch. driver of the existing memory space attributes instead.
 255
 256   // obtain page table base
 257   FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)(ArmGetTTBR0BaseAddress ());
 258
 259
 260   // iterate through each 1MB descriptor
 261   NextRegionBase = NextRegionLength = 0;
 262   for (i=0; i< TRANSLATION_TABLE_SECTION_COUNT; i++) {
 263
 264     // obtain existing descriptor and make sure it contains a valid Base Address even if it is a fault section
 265     Descriptor = FirstLevelTable[i] | TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
 266
 267     // extract attributes (cacheability and permissions)
 268     SectionAttributes = Descriptor & (TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK);
 269
 270     // do we already have an existing region (or are we about to finish)?
 271     // Skip the first entry, and make sure we close on the last entry
 272     if ( (NextRegionLength > 0) || (i == (TRANSLATION_TABLE_SECTION_COUNT-1)) ) {
 273       // attributes are changing, update attributes in GCD
 274       if (SectionAttributes != NextRegionAttributes) {
 275
 276         // convert section entry attributes to GCD bitmask
 277         Status = SectionToGcdAttributes (NextRegionAttributes, &GcdAttributes);
 278         ASSERT_EFI_ERROR (Status);
 279
 280         // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)
 281         SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);
 282
 283
 284         // start on a new region
 285         NextRegionLength = 0;
 286         NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(Descriptor);
 287       }
 288     }
 289
 290     // starting a new region?
 291     if (NextRegionLength == 0) {
 292       NextRegionAttributes = SectionAttributes;
 293     }
 294
 295     NextRegionLength += TT_DESCRIPTOR_SECTION_SIZE;
 296
 297   } // section entry loop
 298
 299   return EFI_SUCCESS;
 300 }
 301
 302
 303
 304 EFI_STATUS
 305 UpdatePageEntries (
 306   IN EFI_PHYSICAL_ADDRESS      BaseAddress,
 307   IN UINT64                    Length,
 308   IN UINT64                    Attributes,
 309   IN EFI_PHYSICAL_ADDRESS      VirtualMask
 310   )
 311 {
 312   EFI_STATUS    Status;
 313   UINT32        EntryValue;
 314   UINT32        EntryMask;
 315   UINT32        FirstLevelIdx;
 316   UINT32        Offset;
 317   UINT32        NumPageEntries;
 318   UINT32        Descriptor;
 319   UINT32        p;
 320   UINT32        PageTableIndex;
 321   UINT32        PageTableEntry;
 322   UINT32        CurrentPageTableEntry;
 323   VOID          *Mva;
 324
 325   volatile ARM_FIRST_LEVEL_DESCRIPTOR   *FirstLevelTable;
 326   volatile ARM_PAGE_TABLE_ENTRY         *PageTable;
 327
 328   Status = EFI_SUCCESS;
 329
 330   // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)
 331   // EntryValue: values at bit positions specified by EntryMask
 332   EntryMask = TT_DESCRIPTOR_PAGE_TYPE_MASK;
 333   EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE;
 334   // Although the PI spec is unclear on this the GCD guarantees that only
 335   // one Attribute bit is set at a time, so we can safely use a switch statement
 336   switch (Attributes) {
 337     case EFI_MEMORY_UC:
 338       // modify cacheability attributes
 339       EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
 340       if (FeaturePcdGet(PcdEfiUncachedMemoryToStronglyOrdered)) {
 341 \s\s\s\s    // map to strongly ordered
 342 \s\s\s\s    EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
 343       } else {
 344     \s\s  // map to normal non-cachable
 345     \s\s  EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
 346       }
 347       break;
 348
 349     case EFI_MEMORY_WC:
 350       // modify cacheability attributes
 351       EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
 352       // map to normal non-cachable
 353       EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
 354       break;
 355
 356     case EFI_MEMORY_WT:
 357       // modify cacheability attributes
 358       EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
 359       // write through with no-allocate
 360       EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0
 361       break;
 362
 363     case EFI_MEMORY_WB:
 364       // modify cacheability attributes
 365       EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
 366       // write back (with allocate)
 367       EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1
 368       break;
 369
 370     case EFI_MEMORY_WP:
 371     case EFI_MEMORY_XP:
 372     case EFI_MEMORY_UCE:
 373       // cannot be implemented UEFI definition unclear for ARM
 374       // Cause a page fault if these ranges are accessed.
 375       EntryValue = TT_DESCRIPTOR_PAGE_TYPE_FAULT;
 376       DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting page %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));
 377       break;
 378
 379     default:
 380       return EFI_UNSUPPORTED;
 381   }
 382
 383   // obtain page table base
 384   FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();
 385
 386   // calculate number of 4KB page table entries to change
 387   NumPageEntries = Length/SIZE_4KB;
 388
 389   // iterate for the number of 4KB pages to change
 390   Offset = 0;
 391   for(p=0; p<NumPageEntries; p++) {
 392     // calculate index into first level translation table for page table value
 393
 394     FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress + Offset) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
 395     ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);
 396
 397     // read the descriptor from the first level page table
 398     Descriptor = FirstLevelTable[FirstLevelIdx];
 399
 400     // does this descriptor need to be converted from section entry to 4K pages?
 401     if (!TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Descriptor)) {
 402       Status = ConvertSectionToPages (FirstLevelIdx << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
 403       if (EFI_ERROR(Status)) {
 404         // exit for loop
 405         break;
 406       }
 407
 408       // re-read descriptor
 409       Descriptor = FirstLevelTable[FirstLevelIdx];
 410     }
 411
 412     // obtain page table base address
 413     PageTable = (ARM_PAGE_TABLE_ENTRY *)TT_DESCRIPTOR_PAGE_BASE_ADDRESS(Descriptor);
 414
 415     // calculate index into the page table
 416     PageTableIndex = ((BaseAddress + Offset) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;
 417     ASSERT (PageTableIndex < TRANSLATION_TABLE_PAGE_COUNT);
 418
 419     // get the entry
 420     CurrentPageTableEntry = PageTable[PageTableIndex];
 421
 422     // mask off appropriate fields
 423     PageTableEntry = CurrentPageTableEntry & ~EntryMask;
 424
 425     // mask in new attributes and/or permissions
 426     PageTableEntry |= EntryValue;
 427
 428     if (VirtualMask != 0) {
 429       // Make this virtual address point at a physical page
 430       PageTableEntry &= ~VirtualMask;
 431     }
 432
 433     if (CurrentPageTableEntry  != PageTableEntry) {
 434       Mva = (VOID *)(UINTN)((((UINTN)FirstLevelIdx) << TT_DESCRIPTOR_SECTION_BASE_SHIFT) + (PageTableIndex << TT_DESCRIPTOR_PAGE_BASE_SHIFT));
 435       if ((CurrentPageTableEntry & TT_DESCRIPTOR_PAGE_CACHEABLE_MASK) == TT_DESCRIPTOR_PAGE_CACHEABLE_MASK) {
 436         // The current section mapping is cacheable so Clean/Invalidate the MVA of the page
 437         // Note assumes switch(Attributes), not ARMv7 possibilities
 438         WriteBackInvalidateDataCacheRange (Mva, SIZE_4KB);
 439       }
 440
 441       // Only need to update if we are changing the entry
 442       PageTable[PageTableIndex] = PageTableEntry;
 443       ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], Mva);
 444     }
 445
 446     Status = EFI_SUCCESS;
 447     Offset += SIZE_4KB;
 448
 449   } // end first level translation table loop
 450
 451   return Status;
 452 }
 453
 454
 455
 456 EFI_STATUS
 457 UpdateSectionEntries (
 458   IN EFI_PHYSICAL_ADDRESS      BaseAddress,
 459   IN UINT64                    Length,
 460   IN UINT64                    Attributes,
 461   IN EFI_PHYSICAL_ADDRESS      VirtualMask
 462   )
 463 {
 464   EFI_STATUS    Status = EFI_SUCCESS;
 465   UINT32        EntryMask;
 466   UINT32        EntryValue;
 467   UINT32        FirstLevelIdx;
 468   UINT32        NumSections;
 469   UINT32        i;
 470   UINT32        CurrentDescriptor;
 471   UINT32        Descriptor;
 472   VOID          *Mva;
 473   volatile ARM_FIRST_LEVEL_DESCRIPTOR   *FirstLevelTable;
 474
 475   // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)
 476   // EntryValue: values at bit positions specified by EntryMask
 477
 478   // Make sure we handle a section range that is unmapped
 479   EntryMask = TT_DESCRIPTOR_SECTION_TYPE_MASK;
 480   EntryValue = TT_DESCRIPTOR_SECTION_TYPE_SECTION;
 481
 482   // Although the PI spec is unclear on this the GCD guarantees that only
 483   // one Attribute bit is set at a time, so we can safely use a switch statement
 484   switch(Attributes) {
 485     case EFI_MEMORY_UC:
 486       // modify cacheability attributes
 487       EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
 488       if (FeaturePcdGet(PcdEfiUncachedMemoryToStronglyOrdered)) {
 489 \s\s\s\s    // map to strongly ordered
 490 \s\s\s\s    EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
 491       } else {
 492     \s\s  // map to normal non-cachable
 493     \s\s  EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
 494       }
 495       break;
 496
 497     case EFI_MEMORY_WC:
 498       // modify cacheability attributes
 499       EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
 500       // map to normal non-cachable
 501       EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
 502       break;
 503
 504     case EFI_MEMORY_WT:
 505       // modify cacheability attributes
 506       EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
 507       // write through with no-allocate
 508       EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0
 509       break;
 510
 511     case EFI_MEMORY_WB:
 512       // modify cacheability attributes
 513       EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
 514       // write back (with allocate)
 515       EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1
 516       break;
 517
 518     case EFI_MEMORY_WP:
 519     case EFI_MEMORY_XP:
 520     case EFI_MEMORY_RP:
 521     case EFI_MEMORY_UCE:
 522       // cannot be implemented UEFI definition unclear for ARM
 523       // Cause a page fault if these ranges are accessed.
 524       EntryValue = TT_DESCRIPTOR_SECTION_TYPE_FAULT;
 525       DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting section %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));
 526       break;
 527
 528
 529     default:
 530       return EFI_UNSUPPORTED;
 531   }
 532
 533   // obtain page table base
 534   FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();
 535
 536   // calculate index into first level translation table for start of modification
 537   FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
 538   ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);
 539
 540   // calculate number of 1MB first level entries this applies to
 541   NumSections = Length / TT_DESCRIPTOR_SECTION_SIZE;
 542
 543   // iterate through each descriptor
 544   for(i=0; i<NumSections; i++) {
 545     CurrentDescriptor = FirstLevelTable[FirstLevelIdx + i];
 546
 547     // has this descriptor already been coverted to pages?
 548     if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(CurrentDescriptor)) {
 549       // forward this 1MB range to page table function instead
 550       Status = UpdatePageEntries ((FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT, TT_DESCRIPTOR_SECTION_SIZE, Attributes, VirtualMask);
 551     } else {
 552       // still a section entry
 553
 554       // mask off appropriate fields
 555       Descriptor = CurrentDescriptor & ~EntryMask;
 556
 557       // mask in new attributes and/or permissions
 558       Descriptor |= EntryValue;
 559       if (VirtualMask != 0) {
 560         Descriptor &= ~VirtualMask;
 561       }
 562
 563       if (CurrentDescriptor  != Descriptor) {
 564         Mva = (VOID *)(UINTN)(((UINTN)FirstLevelTable) << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
 565         if ((CurrentDescriptor & TT_DESCRIPTOR_SECTION_CACHEABLE_MASK) == TT_DESCRIPTOR_SECTION_CACHEABLE_MASK) {
 566           // The current section mapping is cacheable so Clean/Invalidate the MVA of the section
 567           // Note assumes switch(Attributes), not ARMv7 possabilities
 568           WriteBackInvalidateDataCacheRange (Mva, SIZE_1MB);
 569         }
 570
 571         // Only need to update if we are changing the descriptor
 572         FirstLevelTable[FirstLevelIdx + i] = Descriptor;
 573         ArmUpdateTranslationTableEntry ((VOID *)&FirstLevelTable[FirstLevelIdx + i], Mva);
 574       }
 575
 576       Status = EFI_SUCCESS;
 577     }
 578   }
 579
 580   return Status;
 581 }
 582
 583 EFI_STATUS
 584 ConvertSectionToPages (
 585   IN EFI_PHYSICAL_ADDRESS  BaseAddress
 586   )
 587 {
 588   EFI_STATUS              Status;
 589   EFI_PHYSICAL_ADDRESS    PageTableAddr;
 590   UINT32                  FirstLevelIdx;
 591   UINT32                  SectionDescriptor;
 592   UINT32                  PageTableDescriptor;
 593   UINT32                  PageDescriptor;
 594   UINT32                  i;
 595
 596   volatile ARM_FIRST_LEVEL_DESCRIPTOR   *FirstLevelTable;
 597   volatile ARM_PAGE_TABLE_ENTRY         *PageTable;
 598
 599   DEBUG ((EFI_D_PAGE, "Converting section at 0x%x to pages\n", (UINTN)BaseAddress));
 600
 601   // obtain page table base
 602   FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();
 603
 604   // calculate index into first level translation table for start of modification
 605   FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
 606   ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);
 607
 608   // get section attributes and convert to page attributes
 609   SectionDescriptor = FirstLevelTable[FirstLevelIdx];
 610   PageDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE;
 611   PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(SectionDescriptor,0);
 612   PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(SectionDescriptor);
 613   PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_XN(SectionDescriptor,0);
 614   PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(SectionDescriptor);
 615   PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_S(SectionDescriptor);
 616
 617   // allocate a page table for the 4KB entries (we use up a full page even though we only need 1KB)
 618   Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData, 1, &PageTableAddr);
 619   if (EFI_ERROR(Status)) {
 620     return Status;
 621   }
 622
 623   PageTable = (volatile ARM_PAGE_TABLE_ENTRY *)(UINTN)PageTableAddr;
 624
 625   // write the page table entries out
 626   for (i=0; i < TRANSLATION_TABLE_PAGE_COUNT; i++) {
 627     PageTable[i] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseAddress + (i << 12)) | PageDescriptor;
 628   }
 629
 630   // flush d-cache so descriptors make it back to uncached memory for subsequent table walks
 631   WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)PageTableAddr, SIZE_4KB);
 632
 633   // formulate page table entry, Domain=0, NS=0
 634   PageTableDescriptor = (((UINTN)PageTableAddr) & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;
 635
 636   // write the page table entry out, repalcing section entry
 637   FirstLevelTable[FirstLevelIdx] = PageTableDescriptor;
 638
 639   return EFI_SUCCESS;
 640 }
 641
 642
 643
 644 EFI_STATUS
 645 SetMemoryAttributes (
 646   IN EFI_PHYSICAL_ADDRESS      BaseAddress,
 647   IN UINT64                    Length,
 648   IN UINT64                    Attributes,
 649   IN EFI_PHYSICAL_ADDRESS      VirtualMask
 650   )
 651 {
 652   EFI_STATUS    Status;
 653
 654   if(((BaseAddress & 0xFFFFF) == 0) && ((Length & 0xFFFFF) == 0)) {
 655     // is the base and length a multiple of 1 MB?
 656     DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));
 657     Status = UpdateSectionEntries (BaseAddress, Length, Attributes, VirtualMask);
 658   } else {
 659     // base and/or length is not a multiple of 1 MB
 660     DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU page 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));
 661     Status = UpdatePageEntries (BaseAddress, Length, Attributes, VirtualMask);
 662   }
 663
 664   // flush d-cache so descriptors make it back to uncached memory for subsequent table walks
 665   // flush and invalidate pages
 666   ArmCleanInvalidateDataCache ();
 667
 668   ArmInvalidateInstructionCache ();
 669
 670   // invalidate all TLB entries so changes are synced
 671   ArmInvalidateTlb ();
 672
 673   return Status;
 674 }
 675
 676
 677 /**
 678   This function modifies the attributes for the memory region specified by BaseAddress and
 679   Length from their current attributes to the attributes specified by Attributes.
 680
 681   @param  This             The EFI_CPU_ARCH_PROTOCOL instance.
 682   @param  BaseAddress      The physical address that is the start address of a memory region.
 683   @param  Length           The size in bytes of the memory region.
 684   @param  Attributes       The bit mask of attributes to set for the memory region.
 685
 686   @retval EFI_SUCCESS           The attributes were set for the memory region.
 687   @retval EFI_ACCESS_DENIED     The attributes for the memory resource range specified by
 688                                 BaseAddress and Length cannot be modified.
 689   @retval EFI_INVALID_PARAMETER Length is zero.
 690   @retval EFI_OUT_OF_RESOURCES  There are not enough system resources to modify the attributes of
 691                                 the memory resource range.
 692   @retval EFI_UNSUPPORTED       The processor does not support one or more bytes of the memory
 693                                 resource range specified by BaseAddress and Length.
 694                                 The bit mask of attributes is not support for the memory resource
 695                                 range specified by BaseAddress and Length.
 696
 697 **/
 698 EFI_STATUS
 699 EFIAPI
 700 CpuSetMemoryAttributes (
 701   IN EFI_CPU_ARCH_PROTOCOL     *This,
 702   IN EFI_PHYSICAL_ADDRESS      BaseAddress,
 703   IN UINT64                    Length,
 704   IN UINT64                    Attributes
 705   )
 706 {
 707   DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx)\n", BaseAddress, Length, Attributes));
 708   if ( ((BaseAddress & (SIZE_4KB-1)) != 0) || ((Length & (SIZE_4KB-1)) != 0)){
 709     // minimum granularity is SIZE_4KB (4KB on ARM)
 710     DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx): minimum ganularity is SIZE_4KB\n", BaseAddress, Length, Attributes));
 711     return EFI_UNSUPPORTED;
 712   }
 713
 714   return SetMemoryAttributes (BaseAddress, Length, Attributes, 0);
 715 }
 716
 717
 718
 719 //
 720 // Add a new protocol to support
 721 //
 722
 723 EFI_STATUS
 724 EFIAPI
 725 CpuConvertPagesToUncachedVirtualAddress (
 726   IN  VIRTUAL_UNCACHED_PAGES_PROTOCOL   *This,
 727   IN  EFI_PHYSICAL_ADDRESS              Address,
 728   IN  UINTN                             Length,
 729   IN  EFI_PHYSICAL_ADDRESS              VirtualMask,
 730   OUT UINT64                            *Attributes     OPTIONAL
 731   )
 732 {
 733   EFI_STATUS  Status;
 734   EFI_GCD_MEMORY_SPACE_DESCRIPTOR GcdDescriptor;
 735
 736
 737   if (Attributes != NULL) {
 738     Status = gDS->GetMemorySpaceDescriptor (Address, &GcdDescriptor);
 739     if (!EFI_ERROR (Status)) {
 740       *Attributes = GcdDescriptor.Attributes;
 741     }
 742   }
 743
 744   //
 745   // Make this address range page fault if accessed. If it is a DMA buffer than this would
 746   // be the PCI address. Code should always use the CPU address, and we will or in VirtualMask
 747   // to that address.
 748   //
 749   Status = SetMemoryAttributes (Address, Length, EFI_MEMORY_WP, 0);
 750   if (!EFI_ERROR (Status)) {
 751     Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_UC, VirtualMask);
 752   }
 753
 754   DEBUG ((DEBUG_INFO | DEBUG_LOAD, "ConvertPagesToUncachedVirtualAddress()\n    Unmapped 0x%08lx Mapped 0x%08lx 0x%x bytes\n", Address, Address | VirtualMask, Length));
 755
 756   return Status;
 757 }
 758
 759
 760 EFI_STATUS
 761 EFIAPI
 762 CpuReconvertPages (
 763   IN  VIRTUAL_UNCACHED_PAGES_PROTOCOL   *This,
 764   IN  EFI_PHYSICAL_ADDRESS              Address,
 765   IN  UINTN                             Length,
 766   IN  EFI_PHYSICAL_ADDRESS              VirtualMask,
 767   IN  UINT64                            Attributes
 768   )
 769 {
 770   EFI_STATUS      Status;
 771
 772   DEBUG ((DEBUG_INFO | DEBUG_LOAD, "CpuReconvertPages(%lx, %x, %lx, %lx)\n", Address, Length, VirtualMask, Attributes));
 773
 774   //
 775   // Unmap the alaised Address
 776   //
 777   Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_WP, 0);
 778   if (!EFI_ERROR (Status)) {
 779     //
 780     // Restore atttributes
 781     //
 782     Status = SetMemoryAttributes (Address, Length, Attributes, 0);
 783   }
 784
 785   return Status;
 786 }
 787
 788
 789 VIRTUAL_UNCACHED_PAGES_PROTOCOL  gVirtualUncachedPages = {
 790   CpuConvertPagesToUncachedVirtualAddress,
 791   CpuReconvertPages
 792 };