3 Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>
4 Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
21 // Translation/page table definitions
24 // First Level Descriptors
25 typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR
;
27 // memory space covered by a first level descriptor
28 #define ARM_PAGE_DESC_ENTRY_MVA_SIZE 0x00100000 // 1MB
30 // number of first level descriptors to cover entire 32-bit memory space
31 #define FIRST_LEVEL_ENTRY_COUNT (0xFFFFFFFF / ARM_PAGE_DESC_ENTRY_MVA_SIZE + 1)
34 // page table 1st level descriptor entries
35 #define ARM_PAGE_DESC_BASE_MASK 0xFFFFFC00
36 #define ARM_PAGE_DESC_BASE_SHFIT 10
37 #define ARM_PAGE_DESC_DOMAIN_MASK 0x000001E0
38 #define ARM_PAGE_DESC_DOMAIN_SHIFT 5
39 #define ARM_PAGE_DESC_NS 0x00000008
41 #define ARM_FIRST_LEVEL_DESC_ALIGN 0x00004000 // 16KB
43 // section 1st level desriptor entries
44 #define ARM_SECTION_BASE_MASK 0xFFF00000
45 #define ARM_SECTION_BASE_SHIFT 20
46 #define ARM_SECTION_NS 0x00080000
47 #define ARM_SECTION_nG 0x00020000
48 #define ARM_SECTION_S 0x00010000
49 #define ARM_SECTION_AP2 0x00008000
50 #define ARM_SECTION_TEX_MASK 0x00007000
51 #define ARM_SECTION_TEX_SHIFT 12
52 #define ARM_SECTION_AP10_MASK 0x00000C00
53 #define ARM_SECTION_AP10_SHIFT 10
54 #define ARM_SECTION_DOMAIN_MASK 0x000001E0
55 #define ARM_SECTION_DOMAIN_SHIFT 5
56 #define ARM_SECTION_XN 0x00000010
57 #define ARM_SECTION_C 0x00000008
58 #define ARM_SECTION_B 0x00000004
60 // section level AP[2:0] definitions
61 #define ARM_SECTION_AP_NO_ACCESS 0 // AP[2:0] = 0
62 #define ARM_SECTION_AP_READ_WRITE ARM_SECTION_AP10_MASK // AP[2:0] = 011
63 #define ARM_SECTION_AP_READ_ONLY (ARM_SECTION_AP2 | ARM_SECTION_AP10_MASK) // AP[2:0] = 111
65 // common 1st level descriptor fields
66 #define ARM_DESC_TYPE_MASK 0x00000003
68 // descriptor type values
69 #define ARM_DESC_TYPE_FAULT 0x0
70 #define ARM_DESC_TYPE_PAGE_TABLE 0x1
71 #define ARM_DESC_TYPE_SECTION 0x2
74 // Second Level Descriptors
75 typedef UINT32 ARM_PAGE_TABLE_ENTRY
;
77 // small page 2nd level descriptor entries
78 #define ARM_SMALL_PAGE_BASE_MASK 0xFFFFF000
79 #define ARM_SMALL_PAGE_INDEX_MASK 0x000FF000
80 #define ARM_SMALL_PAGE_BASE_SHIFT 12
81 #define ARM_SMALL_PAGE_TEX_MASK 0x000001C0
82 #define ARM_SMALL_PAGE_TEX_SHIFT 6
83 #define ARM_SMALL_PAGE_XN 0x00000001
85 // large page 2nd level descriptor entries
86 #define ARM_LARGE_PAGE_BASE_MASK 0xFFFF0000
87 #define ARM_LARGE_PAGE_BASE_SHIFT 16
88 #define ARM_LARGE_PAGE_TEX_MASK 0x00007000
89 #define ARM_LARGE_PAGE_TEX_SHIFT 12
90 #define ARM_LARGE_PAGE_XN 0x00008000
92 // common 2nd level desriptor fields
93 #define ARM_PAGE_nG 0x00000800
94 #define ARM_PAGE_S 0x00000400
95 #define ARM_PAGE_AP2 0x00000200
96 #define ARM_PAGE_AP10_MASK 0x00000030
97 #define ARM_PAGE_AP10_SHIFT 4
98 #define ARM_PAGE_C 0x00000008
99 #define ARM_PAGE_B 0x00000004
100 #define ARM_PAGE_DESC_TYPE_MASK 0x00000003
102 // descriptor type values
103 #define ARM_PAGE_TYPE_FAULT 0x0
104 #define ARM_PAGE_TYPE_LARGE 0x1
105 #define ARM_PAGE_TYPE_SMALL 0x2
106 #define ARM_PAGE_TYPE_SMALL_XN 0x3
108 #define SMALL_PAGE_TABLE_ENTRY_COUNT (ARM_PAGE_DESC_ENTRY_MVA_SIZE / SIZE_4KB)
111 // Translation Table Base 0 fields
112 #define ARM_TTBR0_BASE_MASK 0xFFFFC000
113 #define ARM_TTBR0_BASE_SHIFT 14
114 #define ARM_TTRB0_NOS 0x00000020
116 // define the combination of interesting attributes: cacheability and access permissions
117 #define ARM_SECTION_CACHEABILITY_MASK ( ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B )
118 #define ARM_SECTION_RW_PERMISSIONS_MASK ( ARM_SECTION_AP2 | ARM_SECTION_AP10_MASK )
119 #define ARM_DESCRIPTOR_ATTRIBUTES ( ARM_SECTION_CACHEABILITY_MASK | ARM_SECTION_RW_PERMISSIONS_MASK | ARM_SECTION_XN )
121 // cacheability values for section entries
122 #define ARM_SECTION_STRONGLY_ORDERED 0
123 #define ARM_SECTION_SHAREABLE_DEVICE ARM_SECTION_B
124 #define ARM_SECTION_WRITE_THROUGH ARM_SECTION_C
125 #define ARM_SECTION_WRITE_BACK_NWA ( ARM_SECTION_C| ARM_SECTION_B )
126 #define ARM_SECTION_NORMAL_UNCACHEABLE ( 0x1 << ARM_SECTION_TEX_SHIFT )
127 #define ARM_SECTION_WRITE_BACK ( ( 0x1 << ARM_SECTION_TEX_SHIFT ) | ARM_SECTION_C | ARM_SECTION_B )
128 #define ARM_SECTION_NONSHAREABLE_DEVICE ( 0x2 << ARM_SECTION_TEX_SHIFT )
130 // permissions values for section entries
131 #define ARM_SECTION_NO_ACCESS 0
132 #define ARM_SECTION_PRIV_ACCESS_ONLY ( 0x1 << ARM_SECTION_AP10_SHIFT)
133 #define ARM_SECTION_USER_READ_ONLY ( 0x2 << ARM_SECTION_AP10_SHIFT)
134 #define ARM_SECTION_FULL_ACCESS ( 0x3 << ARM_SECTION_AP10_SHIFT)
135 #define ARM_SECTION_PRIV_READ_ONLY ( ARM_SECTION_AP2 | (0x1 << ARM_SECTION_AP10_SHIFT) )
136 #define ARM_SECTION_READ_ONLY_DEP ( ARM_SECTION_AP2 | (0x2 << ARM_SECTION_AP10_SHIFT) )
137 #define ARM_SECTION_READ_ONLY ( ARM_SECTION_AP2 | (0x3 << ARM_SECTION_AP10_SHIFT) )
142 SectionToGcdAttributes (
143 IN UINT32 SectionAttributes
,
144 OUT UINT64
*GcdAttributes
149 // determine cacheability attributes
150 switch(SectionAttributes
& ARM_SECTION_CACHEABILITY_MASK
) {
151 case ARM_SECTION_STRONGLY_ORDERED
:
152 *GcdAttributes
|= EFI_MEMORY_UC
;
154 case ARM_SECTION_SHAREABLE_DEVICE
:
155 *GcdAttributes
|= EFI_MEMORY_UC
;
157 case ARM_SECTION_WRITE_THROUGH
:
158 *GcdAttributes
|= EFI_MEMORY_WT
;
160 case ARM_SECTION_WRITE_BACK_NWA
:
161 *GcdAttributes
|= EFI_MEMORY_WB
;
163 case ARM_SECTION_NORMAL_UNCACHEABLE
:
164 *GcdAttributes
|= EFI_MEMORY_WC
;
166 case ARM_SECTION_WRITE_BACK
:
167 *GcdAttributes
|= EFI_MEMORY_WB
;
169 case ARM_SECTION_NONSHAREABLE_DEVICE
:
170 *GcdAttributes
|= EFI_MEMORY_UC
;
173 return EFI_UNSUPPORTED
;
176 // determine protection attributes
177 switch(SectionAttributes
& ARM_SECTION_RW_PERMISSIONS_MASK
) {
178 case ARM_SECTION_NO_ACCESS
: // no read, no write
179 //*GcdAttributes |= EFI_MEMORY_WP | EFI_MEMORY_RP;
182 case ARM_SECTION_PRIV_ACCESS_ONLY
:
183 case ARM_SECTION_FULL_ACCESS
:
184 // normal read/write access, do not add additional attributes
187 // read only cases map to write-protect
188 case ARM_SECTION_PRIV_READ_ONLY
:
189 case ARM_SECTION_READ_ONLY_DEP
:
190 case ARM_SECTION_READ_ONLY
:
191 *GcdAttributes
|= EFI_MEMORY_WP
;
195 return EFI_UNSUPPORTED
;
198 // now process eXectue Never attribute
199 if ((SectionAttributes
& ARM_SECTION_XN
) != 0 ) {
200 *GcdAttributes
|= EFI_MEMORY_XP
;
207 Searches memory descriptors covered by given memory range.
209 This function searches into the Gcd Memory Space for descriptors
210 (from StartIndex to EndIndex) that contains the memory range
211 specified by BaseAddress and Length.
213 @param MemorySpaceMap Gcd Memory Space Map as array.
214 @param NumberOfDescriptors Number of descriptors in map.
215 @param BaseAddress BaseAddress for the requested range.
216 @param Length Length for the requested range.
217 @param StartIndex Start index into the Gcd Memory Space Map.
218 @param EndIndex End index into the Gcd Memory Space Map.
220 @retval EFI_SUCCESS Search successfully.
221 @retval EFI_NOT_FOUND The requested descriptors does not exist.
225 SearchGcdMemorySpaces (
226 IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR
*MemorySpaceMap
,
227 IN UINTN NumberOfDescriptors
,
228 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
230 OUT UINTN
*StartIndex
,
238 for (Index
= 0; Index
< NumberOfDescriptors
; Index
++) {
239 if (BaseAddress
>= MemorySpaceMap
[Index
].BaseAddress
&&
240 BaseAddress
< MemorySpaceMap
[Index
].BaseAddress
+ MemorySpaceMap
[Index
].Length
) {
243 if (BaseAddress
+ Length
- 1 >= MemorySpaceMap
[Index
].BaseAddress
&&
244 BaseAddress
+ Length
- 1 < MemorySpaceMap
[Index
].BaseAddress
+ MemorySpaceMap
[Index
].Length
) {
249 return EFI_NOT_FOUND
;
254 Sets the attributes for a specified range in Gcd Memory Space Map.
256 This function sets the attributes for a specified range in
257 Gcd Memory Space Map.
259 @param MemorySpaceMap Gcd Memory Space Map as array
260 @param NumberOfDescriptors Number of descriptors in map
261 @param BaseAddress BaseAddress for the range
262 @param Length Length for the range
263 @param Attributes Attributes to set
265 @retval EFI_SUCCESS Memory attributes set successfully
266 @retval EFI_NOT_FOUND The specified range does not exist in Gcd Memory Space
270 SetGcdMemorySpaceAttributes (
271 IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR
*MemorySpaceMap
,
272 IN UINTN NumberOfDescriptors
,
273 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
282 EFI_PHYSICAL_ADDRESS RegionStart
;
286 // Get all memory descriptors covered by the memory range
288 Status
= SearchGcdMemorySpaces (
296 if (EFI_ERROR (Status
)) {
301 // Go through all related descriptors and set attributes accordingly
303 for (Index
= StartIndex
; Index
<= EndIndex
; Index
++) {
304 if (MemorySpaceMap
[Index
].GcdMemoryType
== EfiGcdMemoryTypeNonExistent
) {
308 // Calculate the start and end address of the overlapping range
310 if (BaseAddress
>= MemorySpaceMap
[Index
].BaseAddress
) {
311 RegionStart
= BaseAddress
;
313 RegionStart
= MemorySpaceMap
[Index
].BaseAddress
;
315 if (BaseAddress
+ Length
- 1 < MemorySpaceMap
[Index
].BaseAddress
+ MemorySpaceMap
[Index
].Length
) {
316 RegionLength
= BaseAddress
+ Length
- RegionStart
;
318 RegionLength
= MemorySpaceMap
[Index
].BaseAddress
+ MemorySpaceMap
[Index
].Length
- RegionStart
;
321 // Set memory attributes according to MTRR attribute and the original attribute of descriptor
323 gDS
->SetMemorySpaceAttributes (
326 (MemorySpaceMap
[Index
].Attributes
& ~EFI_MEMORY_CACHETYPE_MASK
) | (MemorySpaceMap
[Index
].Capabilities
& Attributes
)
336 IN EFI_CPU_ARCH_PROTOCOL
*CpuProtocol
342 UINT32 SectionAttributes
;
343 EFI_PHYSICAL_ADDRESS NextRegionBase
;
344 UINT64 NextRegionLength
;
345 UINT64 GcdAttributes
;
346 UINT32 NextRegionAttributes
= 0;
347 volatile ARM_FIRST_LEVEL_DESCRIPTOR
*FirstLevelTable
;
348 UINTN NumberOfDescriptors
;
349 EFI_GCD_MEMORY_SPACE_DESCRIPTOR
*MemorySpaceMap
;
352 DEBUG ((EFI_D_PAGE
, "SyncCacheConfig()\n"));
354 // This code assumes MMU is enabled and filed with section translations
355 ASSERT (ArmMmuEnabled ());
358 // Get the memory space map from GCD
360 MemorySpaceMap
= NULL
;
361 Status
= gDS
->GetMemorySpaceMap (&NumberOfDescriptors
, &MemorySpaceMap
);
362 ASSERT_EFI_ERROR (Status
);
365 // The GCD implementation maintains its own copy of the state of memory space attributes. GCD needs
366 // to know what the initial memory space attributes are. The CPU Arch. Protocol does not provide a
367 // GetMemoryAttributes function for GCD to get this so we must resort to calling GCD (as if we were
368 // a client) to update its copy of the attributes. This is bad architecture and should be replaced
369 // with a way for GCD to query the CPU Arch. driver of the existing memory space attributes instead.
371 // obtain page table base
372 FirstLevelTable
= (ARM_FIRST_LEVEL_DESCRIPTOR
*)(ArmGetTranslationTableBaseAddress ());
375 // iterate through each 1MB descriptor
376 NextRegionBase
= NextRegionLength
= 0;
377 for (i
=0; i
< FIRST_LEVEL_ENTRY_COUNT
; i
++) {
379 // obtain existing descriptor and make sure it contains a valid Base Address even if it is a fault section
380 Descriptor
= FirstLevelTable
[i
] | (ARM_SECTION_BASE_MASK
& (i
<< ARM_SECTION_BASE_SHIFT
));
382 // extract attributes (cacheability and permissions)
383 SectionAttributes
= Descriptor
& 0xDEC;
385 // do we already have an existing region (or are we about to finish)?
386 // Skip the first entry, and make sure we close on the last entry
387 if ( (NextRegionLength
> 0) || (i
== (FIRST_LEVEL_ENTRY_COUNT
-1)) ) {
388 // attributes are changing, update attributes in GCD
389 if (SectionAttributes
!= NextRegionAttributes
) {
391 // convert section entry attributes to GCD bitmask
392 Status
= SectionToGcdAttributes (NextRegionAttributes
, &GcdAttributes
);
393 ASSERT_EFI_ERROR (Status
);
395 // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)
396 SetGcdMemorySpaceAttributes (MemorySpaceMap
, NumberOfDescriptors
, NextRegionBase
, NextRegionLength
, GcdAttributes
);
399 // start on a new region
400 NextRegionLength
= 0;
401 NextRegionBase
= Descriptor
& ARM_SECTION_BASE_MASK
;
405 // starting a new region?
406 if (NextRegionLength
== 0) {
407 NextRegionAttributes
= SectionAttributes
;
410 NextRegionLength
+= ARM_PAGE_DESC_ENTRY_MVA_SIZE
;
412 } // section entry loop
421 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
423 IN UINT64 Attributes
,
424 IN EFI_PHYSICAL_ADDRESS VirtualMask
430 UINT32 FirstLevelIdx
;
432 UINT32 NumPageEntries
;
435 UINT32 PageTableIndex
;
436 UINT32 PageTableEntry
;
437 UINT32 CurrentPageTableEntry
;
440 volatile ARM_FIRST_LEVEL_DESCRIPTOR
*FirstLevelTable
;
441 volatile ARM_PAGE_TABLE_ENTRY
*PageTable
;
443 Status
= EFI_SUCCESS
;
445 // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)
446 // EntryValue: values at bit positions specified by EntryMask
447 EntryMask
= ARM_PAGE_DESC_TYPE_MASK
;
448 EntryValue
= ARM_PAGE_TYPE_SMALL
;
449 // Although the PI spec is unclear on this the GCD guarantees that only
450 // one Attribute bit is set at a time, so we can safely use a switch statement
451 switch (Attributes
) {
453 // modify cacheability attributes
454 EntryMask
|= ARM_SMALL_PAGE_TEX_MASK
| ARM_PAGE_C
| ARM_PAGE_B
;
455 // map to strongly ordered
456 EntryValue
|= 0; // TEX[2:0] = 0, C=0, B=0
460 // modify cacheability attributes
461 EntryMask
|= ARM_SMALL_PAGE_TEX_MASK
| ARM_PAGE_C
| ARM_PAGE_B
;
462 // map to normal non-cachable
463 EntryValue
|= (0x1 << ARM_SMALL_PAGE_TEX_SHIFT
); // TEX [2:0]= 001 = 0x2, B=0, C=0
467 // modify cacheability attributes
468 EntryMask
|= ARM_SMALL_PAGE_TEX_MASK
| ARM_PAGE_C
| ARM_PAGE_B
;
469 // write through with no-allocate
470 EntryValue
|= ARM_PAGE_C
; // TEX [2:0] = 0, C=1, B=0
474 // modify cacheability attributes
475 EntryMask
|= ARM_SMALL_PAGE_TEX_MASK
| ARM_PAGE_C
| ARM_PAGE_B
;
476 // write back (with allocate)
477 EntryValue
|= (0x1 << ARM_SMALL_PAGE_TEX_SHIFT
) | ARM_PAGE_C
| ARM_PAGE_B
; // TEX [2:0] = 001, C=1, B=1
483 // cannot be implemented UEFI definition unclear for ARM
484 // Cause a page fault if these ranges are accessed.
485 EntryValue
= ARM_PAGE_TYPE_FAULT
;
486 DEBUG ((EFI_D_PAGE
, "SetMemoryAttributes(): setting page %lx with unsupported attribute %x will page fault on access\n", BaseAddress
, Attributes
));
490 return EFI_UNSUPPORTED
;
493 // obtain page table base
494 FirstLevelTable
= (ARM_FIRST_LEVEL_DESCRIPTOR
*)ArmGetTranslationTableBaseAddress ();
496 // calculate number of 4KB page table entries to change
497 NumPageEntries
= Length
/SIZE_4KB
;
499 // iterate for the number of 4KB pages to change
501 for(p
=0; p
<NumPageEntries
; p
++) {
502 // calculate index into first level translation table for page table value
504 FirstLevelIdx
= ((BaseAddress
+ Offset
) & ARM_SECTION_BASE_MASK
) >> ARM_SECTION_BASE_SHIFT
;
505 ASSERT (FirstLevelIdx
< FIRST_LEVEL_ENTRY_COUNT
);
507 // read the descriptor from the first level page table
508 Descriptor
= FirstLevelTable
[FirstLevelIdx
];
510 // does this descriptor need to be converted from section entry to 4K pages?
511 if ((Descriptor
& ARM_DESC_TYPE_MASK
) != ARM_DESC_TYPE_PAGE_TABLE
) {
512 Status
= ConvertSectionToPages (FirstLevelIdx
<< ARM_SECTION_BASE_SHIFT
);
513 if (EFI_ERROR(Status
)) {
518 // re-read descriptor
519 Descriptor
= FirstLevelTable
[FirstLevelIdx
];
522 // obtain page table base address
523 PageTable
= (ARM_PAGE_TABLE_ENTRY
*)(Descriptor
& ARM_SMALL_PAGE_BASE_MASK
);
525 // calculate index into the page table
526 PageTableIndex
= ((BaseAddress
+ Offset
) & ARM_SMALL_PAGE_INDEX_MASK
) >> ARM_SMALL_PAGE_BASE_SHIFT
;
527 ASSERT (PageTableIndex
< SMALL_PAGE_TABLE_ENTRY_COUNT
);
530 CurrentPageTableEntry
= PageTable
[PageTableIndex
];
532 // mask off appropriate fields
533 PageTableEntry
= CurrentPageTableEntry
& ~EntryMask
;
535 // mask in new attributes and/or permissions
536 PageTableEntry
|= EntryValue
;
538 if (VirtualMask
!= 0) {
539 // Make this virtual address point at a physical page
540 PageTableEntry
&= ~VirtualMask
;
543 if (CurrentPageTableEntry
!= PageTableEntry
) {
544 Mva
= (VOID
*)(UINTN
)((((UINTN
)FirstLevelIdx
) << ARM_SECTION_BASE_SHIFT
) + (PageTableIndex
<< ARM_SMALL_PAGE_BASE_SHIFT
));
545 if ((CurrentPageTableEntry
& ARM_PAGE_C
) == ARM_PAGE_C
) {
546 // The current section mapping is cacheable so Clean/Invalidate the MVA of the page
547 // Note assumes switch(Attributes), not ARMv7 possibilities
548 WriteBackInvalidateDataCacheRange (Mva
, SIZE_4KB
);
551 // Only need to update if we are changing the entry
552 PageTable
[PageTableIndex
] = PageTableEntry
;
553 ArmUpdateTranslationTableEntry ((VOID
*)&PageTable
[PageTableIndex
], Mva
);
556 Status
= EFI_SUCCESS
;
559 } // end first level translation table loop
567 UpdateSectionEntries (
568 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
570 IN UINT64 Attributes
,
571 IN EFI_PHYSICAL_ADDRESS VirtualMask
574 EFI_STATUS Status
= EFI_SUCCESS
;
577 UINT32 FirstLevelIdx
;
580 UINT32 CurrentDescriptor
;
583 volatile ARM_FIRST_LEVEL_DESCRIPTOR
*FirstLevelTable
;
585 // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)
586 // EntryValue: values at bit positions specified by EntryMask
588 // Make sure we handle a section range that is unmapped
589 EntryMask
= ARM_DESC_TYPE_MASK
;
590 EntryValue
= ARM_DESC_TYPE_SECTION
;
592 // Although the PI spec is unclear on this the GCD guarantees that only
593 // one Attribute bit is set at a time, so we can safely use a switch statement
596 // modify cacheability attributes
597 EntryMask
|= ARM_SECTION_CACHEABILITY_MASK
;
598 // map to strongly ordered
599 EntryValue
|= 0; // TEX[2:0] = 0, C=0, B=0
603 // modify cacheability attributes
604 EntryMask
|= ARM_SECTION_CACHEABILITY_MASK
;
605 // map to normal non-cachable
606 EntryValue
|= (0x1 << ARM_SECTION_TEX_SHIFT
); // TEX [2:0]= 001 = 0x2, B=0, C=0
610 // modify cacheability attributes
611 EntryMask
|= ARM_SECTION_CACHEABILITY_MASK
;
612 // write through with no-allocate
613 EntryValue
|= ARM_SECTION_C
; // TEX [2:0] = 0, C=1, B=0
617 // modify cacheability attributes
618 EntryMask
|= ARM_SECTION_CACHEABILITY_MASK
;
619 // write back (with allocate)
620 EntryValue
|= (0x1 << ARM_SECTION_TEX_SHIFT
) | ARM_SECTION_C
| ARM_SECTION_B
; // TEX [2:0] = 001, C=1, B=1
627 // cannot be implemented UEFI definition unclear for ARM
628 // Cause a page fault if these ranges are accessed.
629 EntryValue
= ARM_DESC_TYPE_FAULT
;
630 DEBUG ((EFI_D_PAGE
, "SetMemoryAttributes(): setting section %lx with unsupported attribute %x will page fault on access\n", BaseAddress
, Attributes
));
635 return EFI_UNSUPPORTED
;
638 // obtain page table base
639 FirstLevelTable
= (ARM_FIRST_LEVEL_DESCRIPTOR
*)ArmGetTranslationTableBaseAddress ();
641 // calculate index into first level translation table for start of modification
642 FirstLevelIdx
= (BaseAddress
& ARM_SECTION_BASE_MASK
) >> ARM_SECTION_BASE_SHIFT
;
643 ASSERT (FirstLevelIdx
< FIRST_LEVEL_ENTRY_COUNT
);
645 // calculate number of 1MB first level entries this applies to
646 NumSections
= Length
/ ARM_PAGE_DESC_ENTRY_MVA_SIZE
;
648 // iterate through each descriptor
649 for(i
=0; i
<NumSections
; i
++) {
650 CurrentDescriptor
= FirstLevelTable
[FirstLevelIdx
+ i
];
652 // has this descriptor already been coverted to pages?
653 if ((CurrentDescriptor
& ARM_DESC_TYPE_MASK
) != ARM_DESC_TYPE_PAGE_TABLE
) {
654 // forward this 1MB range to page table function instead
655 Status
= UpdatePageEntries ((FirstLevelIdx
+ i
) << ARM_SECTION_BASE_SHIFT
, ARM_PAGE_DESC_ENTRY_MVA_SIZE
, Attributes
, VirtualMask
);
657 // still a section entry
659 // mask off appropriate fields
660 Descriptor
= CurrentDescriptor
& ~EntryMask
;
662 // mask in new attributes and/or permissions
663 Descriptor
|= EntryValue
;
664 if (VirtualMask
!= 0) {
665 Descriptor
&= ~VirtualMask
;
668 if (CurrentDescriptor
!= Descriptor
) {
669 Mva
= (VOID
*)(UINTN
)(((UINTN
)FirstLevelTable
) << ARM_SECTION_BASE_SHIFT
);
670 if ((CurrentDescriptor
& ARM_SECTION_C
) == ARM_SECTION_C
) {
671 // The current section mapping is cacheable so Clean/Invalidate the MVA of the section
672 // Note assumes switch(Attributes), not ARMv7 possabilities
673 WriteBackInvalidateDataCacheRange (Mva
, SIZE_1MB
);
676 // Only need to update if we are changing the descriptor
677 FirstLevelTable
[FirstLevelIdx
+ i
] = Descriptor
;
678 ArmUpdateTranslationTableEntry ((VOID
*)&FirstLevelTable
[FirstLevelIdx
+ i
], Mva
);
681 Status
= EFI_SUCCESS
;
689 ConvertSectionToPages (
690 IN EFI_PHYSICAL_ADDRESS BaseAddress
694 EFI_PHYSICAL_ADDRESS PageTableAddr
;
695 UINT32 FirstLevelIdx
;
696 UINT32 SectionDescriptor
;
697 UINT32 PageTableDescriptor
;
698 UINT32 PageDescriptor
;
701 volatile ARM_FIRST_LEVEL_DESCRIPTOR
*FirstLevelTable
;
702 volatile ARM_PAGE_TABLE_ENTRY
*PageTable
;
704 DEBUG ((EFI_D_PAGE
, "Converting section at 0x%x to pages\n", (UINTN
)BaseAddress
));
706 // obtain page table base
707 FirstLevelTable
= (ARM_FIRST_LEVEL_DESCRIPTOR
*)ArmGetTranslationTableBaseAddress ();
709 // calculate index into first level translation table for start of modification
710 FirstLevelIdx
= (BaseAddress
& ARM_SECTION_BASE_MASK
) >> ARM_SECTION_BASE_SHIFT
;
711 ASSERT (FirstLevelIdx
< FIRST_LEVEL_ENTRY_COUNT
);
713 // get section attributes and convert to page attributes
714 SectionDescriptor
= FirstLevelTable
[FirstLevelIdx
];
715 PageDescriptor
= ARM_PAGE_TYPE_SMALL
;
716 PageDescriptor
|= ((SectionDescriptor
& ARM_SECTION_TEX_MASK
) >> ARM_SECTION_TEX_SHIFT
) << ARM_SMALL_PAGE_TEX_SHIFT
;
717 if ((SectionDescriptor
& ARM_SECTION_B
) != 0) {
718 PageDescriptor
|= ARM_PAGE_B
;
720 if ((SectionDescriptor
& ARM_SECTION_C
) != 0) {
721 PageDescriptor
|= ARM_PAGE_C
;
723 PageDescriptor
|= ((SectionDescriptor
& ARM_SECTION_AP10_MASK
) >> ARM_SECTION_AP10_SHIFT
) << ARM_PAGE_AP10_SHIFT
;
724 if ((SectionDescriptor
& ARM_SECTION_AP2
) != 0) {
725 PageDescriptor
|= ARM_PAGE_AP2
;
727 if ((SectionDescriptor
& ARM_SECTION_XN
) != 0) {
728 PageDescriptor
|= ARM_PAGE_TYPE_SMALL_XN
;
730 if ((SectionDescriptor
& ARM_SECTION_nG
) != 0) {
731 PageDescriptor
|= ARM_PAGE_nG
;
733 if ((SectionDescriptor
& ARM_SECTION_S
) != 0) {
734 PageDescriptor
|= ARM_PAGE_S
;
737 // allocate a page table for the 4KB entries (we use up a full page even though we only need 1KB)
738 Status
= gBS
->AllocatePages (AllocateAnyPages
, EfiBootServicesData
, 1, &PageTableAddr
);
739 if (EFI_ERROR(Status
)) {
743 PageTable
= (volatile ARM_PAGE_TABLE_ENTRY
*)(UINTN
)PageTableAddr
;
745 // write the page table entries out
746 for (i
=0; i
<(ARM_PAGE_DESC_ENTRY_MVA_SIZE
/SIZE_4KB
); i
++) {
747 PageTable
[i
] = ((BaseAddress
+ (i
<< 12)) & ARM_SMALL_PAGE_BASE_MASK
) | PageDescriptor
;
750 // flush d-cache so descriptors make it back to uncached memory for subsequent table walks
751 WriteBackInvalidateDataCacheRange ((VOID
*)(UINTN
)PageTableAddr
, SIZE_4KB
);
753 // formulate page table entry, Domain=0, NS=0
754 PageTableDescriptor
= (((UINTN
)PageTableAddr
) & ARM_PAGE_DESC_BASE_MASK
) | ARM_DESC_TYPE_PAGE_TABLE
;
756 // write the page table entry out, repalcing section entry
757 FirstLevelTable
[FirstLevelIdx
] = PageTableDescriptor
;
765 SetMemoryAttributes (
766 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
768 IN UINT64 Attributes
,
769 IN EFI_PHYSICAL_ADDRESS VirtualMask
774 if(((BaseAddress
& 0xFFFFF) == 0) && ((Length
& 0xFFFFF) == 0)) {
775 // is the base and length a multiple of 1 MB?
776 DEBUG ((EFI_D_PAGE
, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN
)BaseAddress
, (UINTN
)Length
, Attributes
));
777 Status
= UpdateSectionEntries (BaseAddress
, Length
, Attributes
, VirtualMask
);
779 // base and/or length is not a multiple of 1 MB
780 DEBUG ((EFI_D_PAGE
, "SetMemoryAttributes(): MMU page 0x%x length 0x%x to %lx\n", (UINTN
)BaseAddress
, (UINTN
)Length
, Attributes
));
781 Status
= UpdatePageEntries (BaseAddress
, Length
, Attributes
, VirtualMask
);
784 // flush d-cache so descriptors make it back to uncached memory for subsequent table walks
785 // flush and invalidate pages
786 ArmCleanInvalidateDataCache ();
788 ArmInvalidateInstructionCache ();
790 // invalidate all TLB entries so changes are synced
798 This function modifies the attributes for the memory region specified by BaseAddress and
799 Length from their current attributes to the attributes specified by Attributes.
801 @param This The EFI_CPU_ARCH_PROTOCOL instance.
802 @param BaseAddress The physical address that is the start address of a memory region.
803 @param Length The size in bytes of the memory region.
804 @param Attributes The bit mask of attributes to set for the memory region.
806 @retval EFI_SUCCESS The attributes were set for the memory region.
807 @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by
808 BaseAddress and Length cannot be modified.
809 @retval EFI_INVALID_PARAMETER Length is zero.
810 @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of
811 the memory resource range.
812 @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory
813 resource range specified by BaseAddress and Length.
814 The bit mask of attributes is not support for the memory resource
815 range specified by BaseAddress and Length.
820 CpuSetMemoryAttributes (
821 IN EFI_CPU_ARCH_PROTOCOL
*This
,
822 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
827 DEBUG ((EFI_D_PAGE
, "SetMemoryAttributes(%lx, %lx, %lx)\n", BaseAddress
, Length
, Attributes
));
828 if ( ((BaseAddress
& (SIZE_4KB
-1)) != 0) || ((Length
& (SIZE_4KB
-1)) != 0)){
829 // minimum granularity is SIZE_4KB (4KB on ARM)
830 DEBUG ((EFI_D_PAGE
, "SetMemoryAttributes(%lx, %lx, %lx): minimum ganularity is SIZE_4KB\n", BaseAddress
, Length
, Attributes
));
831 return EFI_UNSUPPORTED
;
834 return SetMemoryAttributes (BaseAddress
, Length
, Attributes
, 0);
840 // Add a new protocol to support
845 CpuConvertPagesToUncachedVirtualAddress (
846 IN VIRTUAL_UNCACHED_PAGES_PROTOCOL
*This
,
847 IN EFI_PHYSICAL_ADDRESS Address
,
849 IN EFI_PHYSICAL_ADDRESS VirtualMask
,
850 OUT UINT64
*Attributes OPTIONAL
854 EFI_GCD_MEMORY_SPACE_DESCRIPTOR GcdDescriptor
;
857 if (Attributes
!= NULL
) {
858 Status
= gDS
->GetMemorySpaceDescriptor (Address
, &GcdDescriptor
);
859 if (!EFI_ERROR (Status
)) {
860 *Attributes
= GcdDescriptor
.Attributes
;
865 // Make this address range page fault if accessed. If it is a DMA buffer than this would
866 // be the PCI address. Code should always use the CPU address, and we will or in VirtualMask
869 Status
= SetMemoryAttributes (Address
, Length
, EFI_MEMORY_WP
, 0);
870 if (!EFI_ERROR (Status
)) {
871 Status
= SetMemoryAttributes (Address
| VirtualMask
, Length
, EFI_MEMORY_UC
, VirtualMask
);
874 DEBUG ((DEBUG_INFO
| DEBUG_LOAD
, "ConvertPagesToUncachedVirtualAddress()\n Unmapped 0x%08lx Mapped 0x%08lx 0x%x bytes\n", Address
, Address
| VirtualMask
, Length
));
883 IN VIRTUAL_UNCACHED_PAGES_PROTOCOL
*This
,
884 IN EFI_PHYSICAL_ADDRESS Address
,
886 IN EFI_PHYSICAL_ADDRESS VirtualMask
,
892 DEBUG ((DEBUG_INFO
| DEBUG_LOAD
, "CpuReconvertPages(%lx, %x, %lx, %lx)\n", Address
, Length
, VirtualMask
, Attributes
));
895 // Unmap the alaised Address
897 Status
= SetMemoryAttributes (Address
| VirtualMask
, Length
, EFI_MEMORY_WP
, 0);
898 if (!EFI_ERROR (Status
)) {
900 // Restore atttributes
902 Status
= SetMemoryAttributes (Address
, Length
, Attributes
, 0);
909 VIRTUAL_UNCACHED_PAGES_PROTOCOL gVirtualUncachedPages
= {
910 CpuConvertPagesToUncachedVirtualAddress
,