Missed a fix in the Cpu Driver. Added some more debug for Execption handling and...
[mirror_edk2.git] / ArmPkg / Drivers / CpuDxe / Mmu.c
1 /*++
2
3 Copyright (c) 2009, Hewlett-Packard Company
4 Portions copyright (c) 2010, Apple Inc. All rights reserved.
5
6 All rights reserved. This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14
15 --*/
16
17 #include "CpuDxe.h"
18
19
20 //
21 // Translation/page table definitions
22 //
23
24 // First Level Descriptors
25 typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR;
26
27 // memory space covered by a first level descriptor
28 #define ARM_PAGE_DESC_ENTRY_MVA_SIZE 0x00100000 // 1MB
29
30 // number of first level descriptors to cover entire 32-bit memory space
31 #define FIRST_LEVEL_ENTRY_COUNT (0xFFFFFFFF / ARM_PAGE_DESC_ENTRY_MVA_SIZE + 1)
32
33
34 // page table 1st level descriptor entries
35 #define ARM_PAGE_DESC_BASE_MASK 0xFFFFFC00
36 #define ARM_PAGE_DESC_BASE_SHFIT 10
37 #define ARM_PAGE_DESC_DOMAIN_MASK 0x000001E0
38 #define ARM_PAGE_DESC_DOMAIN_SHIFT 5
39 #define ARM_PAGE_DESC_NS 0x00000008
40
41 #define ARM_FIRST_LEVEL_DESC_ALIGN 0x00004000 // 16KB
42
43 // section 1st level desriptor entries
44 #define ARM_SECTION_BASE_MASK 0xFFF00000
45 #define ARM_SECTION_BASE_SHIFT 20
46 #define ARM_SECTION_NS 0x00080000
47 #define ARM_SECTION_nG 0x00020000
48 #define ARM_SECTION_S 0x00010000
49 #define ARM_SECTION_AP2 0x00008000
50 #define ARM_SECTION_TEX_MASK 0x00007000
51 #define ARM_SECTION_TEX_SHIFT 12
52 #define ARM_SECTION_AP10_MASK 0x00000C00
53 #define ARM_SECTION_AP10_SHIFT 10
54 #define ARM_SECTION_DOMAIN_MASK 0x000001E0
55 #define ARM_SECTION_DOMAIN_SHIFT 5
56 #define ARM_SECTION_XN 0x00000010
57 #define ARM_SECTION_C 0x00000008
58 #define ARM_SECTION_B 0x00000004
59
60 // section level AP[2:0] definitions
61 #define ARM_SECTION_AP_NO_ACCESS 0 // AP[2:0] = 0
62 #define ARM_SECTION_AP_READ_WRITE ARM_SECTION_AP10_MASK // AP[2:0] = 011
63 #define ARM_SECTION_AP_READ_ONLY (ARM_SECTION_AP2 | ARM_SECTION_AP10_MASK) // AP[2:0] = 111
64
65 // common 1st level descriptor fields
66 #define ARM_DESC_TYPE_MASK 0x00000003
67
68 // descriptor type values
69 #define ARM_DESC_TYPE_FAULT 0x0
70 #define ARM_DESC_TYPE_PAGE_TABLE 0x1
71 #define ARM_DESC_TYPE_SECTION 0x2
72
73
74 // Second Level Descriptors
75 typedef UINT32 ARM_PAGE_TABLE_ENTRY;
76
77 // small page 2nd level descriptor entries
78 #define ARM_SMALL_PAGE_BASE_MASK 0xFFFFF000
79 #define ARM_SMALL_PAGE_INDEX_MASK 0x000FF000
80 #define ARM_SMALL_PAGE_BASE_SHIFT 12
81 #define ARM_SMALL_PAGE_TEX_MASK 0x000001C0
82 #define ARM_SMALL_PAGE_TEX_SHIFT 6
83 #define ARM_SMALL_PAGE_XN 0x00000001
84
85 // large page 2nd level descriptor entries
86 #define ARM_LARGE_PAGE_BASE_MASK 0xFFFF0000
87 #define ARM_LARGE_PAGE_BASE_SHIFT 16
88 #define ARM_LARGE_PAGE_TEX_MASK 0x00007000
89 #define ARM_LARGE_PAGE_TEX_SHIFT 12
90 #define ARM_LARGE_PAGE_XN 0x00008000
91
92 // common 2nd level desriptor fields
93 #define ARM_PAGE_nG 0x00000800
94 #define ARM_PAGE_S 0x00000400
95 #define ARM_PAGE_AP2 0x00000200
96 #define ARM_PAGE_AP10_MASK 0x00000030
97 #define ARM_PAGE_AP10_SHIFT 4
98 #define ARM_PAGE_C 0x00000008
99 #define ARM_PAGE_B 0x00000004
100 #define ARM_PAGE_DESC_TYPE_MASK 0x00000003
101
102 // descriptor type values
103 #define ARM_PAGE_TYPE_FAULT 0x0
104 #define ARM_PAGE_TYPE_LARGE 0x1
105 #define ARM_PAGE_TYPE_SMALL 0x2
106 #define ARM_PAGE_TYPE_SMALL_XN 0x3
107
108 #define SMALL_PAGE_TABLE_ENTRY_COUNT (ARM_PAGE_DESC_ENTRY_MVA_SIZE / EFI_PAGE_SIZE)
109
110
111 // Translation Table Base 0 fields
112 #define ARM_TTBR0_BASE_MASK 0xFFFFC000
113 #define ARM_TTBR0_BASE_SHIFT 14
114 #define ARM_TTRB0_NOS 0x00000020
115
116 // define the combination of interesting attributes: cacheability and access permissions
117 #define ARM_SECTION_CACHEABILITY_MASK ( ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B )
118 #define ARM_SECTION_RW_PERMISSIONS_MASK ( ARM_SECTION_AP2 | ARM_SECTION_AP10_MASK )
119 #define ARM_DESCRIPTOR_ATTRIBUTES ( ARM_SECTION_CACHEABILITY_MASK | ARM_SECTION_RW_PERMISSIONS_MASK | ARM_SECTION_XN )
120
121 // cacheability values for section entries
122 #define ARM_SECTION_STRONGLY_ORDERED 0
123 #define ARM_SECTION_SHAREABLE_DEVICE ARM_SECTION_B
124 #define ARM_SECTION_WRITE_THROUGH ARM_SECTION_C
125 #define ARM_SECTION_WRITE_BACK_NWA ( ARM_SECTION_C| ARM_SECTION_B )
126 #define ARM_SECTION_NORMAL_UNCACHEABLE ( 0x1 << ARM_SECTION_TEX_SHIFT )
127 #define ARM_SECTION_WRITE_BACK ( ( 0x1 << ARM_SECTION_TEX_SHIFT ) | ARM_SECTION_C | ARM_SECTION_B )
128 #define ARM_SECTION_NONSHAREABLE_DEVICE ( 0x2 << ARM_SECTION_TEX_SHIFT )
129
130 // permissions values for section entries
131 #define ARM_SECTION_NO_ACCESS 0
132 #define ARM_SECTION_PRIV_ACCESS_ONLY ( 0x1 << ARM_SECTION_AP10_SHIFT)
133 #define ARM_SECTION_USER_READ_ONLY ( 0x2 << ARM_SECTION_AP10_SHIFT)
134 #define ARM_SECTION_FULL_ACCESS ( 0x3 << ARM_SECTION_AP10_SHIFT)
135 #define ARM_SECTION_PRIV_READ_ONLY ( ARM_SECTION_AP2 | (0x1 << ARM_SECTION_AP10_SHIFT) )
136 #define ARM_SECTION_READ_ONLY_DEP ( ARM_SECTION_AP2 | (0x2 << ARM_SECTION_AP10_SHIFT) )
137 #define ARM_SECTION_READ_ONLY ( ARM_SECTION_AP2 | (0x3 << ARM_SECTION_AP10_SHIFT) )
138
139
140
141 EFI_STATUS
142 SectionToGcdAttributes (
143 IN UINT32 SectionAttributes,
144 OUT UINT64 *GcdAttributes
145 )
146 {
147 *GcdAttributes = 0;
148
149 // determine cacheability attributes
150 switch(SectionAttributes & ARM_SECTION_CACHEABILITY_MASK) {
151 case ARM_SECTION_STRONGLY_ORDERED:
152 *GcdAttributes |= EFI_MEMORY_UC;
153 break;
154 case ARM_SECTION_SHAREABLE_DEVICE:
155 *GcdAttributes |= EFI_MEMORY_UC;
156 break;
157 case ARM_SECTION_WRITE_THROUGH:
158 *GcdAttributes |= EFI_MEMORY_WT;
159 break;
160 case ARM_SECTION_WRITE_BACK_NWA:
161 *GcdAttributes |= EFI_MEMORY_WB;
162 break;
163 case ARM_SECTION_NORMAL_UNCACHEABLE:
164 *GcdAttributes |= EFI_MEMORY_WC;
165 break;
166 case ARM_SECTION_WRITE_BACK:
167 *GcdAttributes |= EFI_MEMORY_WB;
168 break;
169 case ARM_SECTION_NONSHAREABLE_DEVICE:
170 *GcdAttributes |= EFI_MEMORY_UC;
171 break;
172 default:
173 return EFI_UNSUPPORTED;
174 }
175
176 // determine protection attributes
177 switch(SectionAttributes & ARM_SECTION_RW_PERMISSIONS_MASK) {
178 case ARM_SECTION_NO_ACCESS: // no read, no write
179 //*GcdAttributes |= EFI_MEMORY_WP | EFI_MEMORY_RP;
180 break;
181
182 case ARM_SECTION_PRIV_ACCESS_ONLY:
183 case ARM_SECTION_FULL_ACCESS:
184 // normal read/write access, do not add additional attributes
185 break;
186
187 // read only cases map to write-protect
188 case ARM_SECTION_PRIV_READ_ONLY:
189 case ARM_SECTION_READ_ONLY_DEP:
190 case ARM_SECTION_READ_ONLY:
191 *GcdAttributes |= EFI_MEMORY_WP;
192 break;
193
194 default:
195 return EFI_UNSUPPORTED;
196 }
197
198 // now process eXectue Never attribute
199 if ((SectionAttributes & ARM_SECTION_XN) != 0 ) {
200 *GcdAttributes |= EFI_MEMORY_XP;
201 }
202
203 return EFI_SUCCESS;
204 }
205
206 /**
207 Searches memory descriptors covered by given memory range.
208
209 This function searches into the Gcd Memory Space for descriptors
210 (from StartIndex to EndIndex) that contains the memory range
211 specified by BaseAddress and Length.
212
213 @param MemorySpaceMap Gcd Memory Space Map as array.
214 @param NumberOfDescriptors Number of descriptors in map.
215 @param BaseAddress BaseAddress for the requested range.
216 @param Length Length for the requested range.
217 @param StartIndex Start index into the Gcd Memory Space Map.
218 @param EndIndex End index into the Gcd Memory Space Map.
219
220 @retval EFI_SUCCESS Search successfully.
221 @retval EFI_NOT_FOUND The requested descriptors does not exist.
222
223 **/
224 EFI_STATUS
225 SearchGcdMemorySpaces (
226 IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
227 IN UINTN NumberOfDescriptors,
228 IN EFI_PHYSICAL_ADDRESS BaseAddress,
229 IN UINT64 Length,
230 OUT UINTN *StartIndex,
231 OUT UINTN *EndIndex
232 )
233 {
234 UINTN Index;
235
236 *StartIndex = 0;
237 *EndIndex = 0;
238 for (Index = 0; Index < NumberOfDescriptors; Index++) {
239 if (BaseAddress >= MemorySpaceMap[Index].BaseAddress &&
240 BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
241 *StartIndex = Index;
242 }
243 if (BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress &&
244 BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
245 *EndIndex = Index;
246 return EFI_SUCCESS;
247 }
248 }
249 return EFI_NOT_FOUND;
250 }
251
252
253 /**
254 Sets the attributes for a specified range in Gcd Memory Space Map.
255
256 This function sets the attributes for a specified range in
257 Gcd Memory Space Map.
258
259 @param MemorySpaceMap Gcd Memory Space Map as array
260 @param NumberOfDescriptors Number of descriptors in map
261 @param BaseAddress BaseAddress for the range
262 @param Length Length for the range
263 @param Attributes Attributes to set
264
265 @retval EFI_SUCCESS Memory attributes set successfully
266 @retval EFI_NOT_FOUND The specified range does not exist in Gcd Memory Space
267
268 **/
269 EFI_STATUS
270 SetGcdMemorySpaceAttributes (
271 IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
272 IN UINTN NumberOfDescriptors,
273 IN EFI_PHYSICAL_ADDRESS BaseAddress,
274 IN UINT64 Length,
275 IN UINT64 Attributes
276 )
277 {
278 EFI_STATUS Status;
279 UINTN Index;
280 UINTN StartIndex;
281 UINTN EndIndex;
282 EFI_PHYSICAL_ADDRESS RegionStart;
283 UINT64 RegionLength;
284
285 //
286 // Get all memory descriptors covered by the memory range
287 //
288 Status = SearchGcdMemorySpaces (
289 MemorySpaceMap,
290 NumberOfDescriptors,
291 BaseAddress,
292 Length,
293 &StartIndex,
294 &EndIndex
295 );
296 if (EFI_ERROR (Status)) {
297 return Status;
298 }
299
300 //
301 // Go through all related descriptors and set attributes accordingly
302 //
303 for (Index = StartIndex; Index <= EndIndex; Index++) {
304 if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
305 continue;
306 }
307 //
308 // Calculate the start and end address of the overlapping range
309 //
310 if (BaseAddress >= MemorySpaceMap[Index].BaseAddress) {
311 RegionStart = BaseAddress;
312 } else {
313 RegionStart = MemorySpaceMap[Index].BaseAddress;
314 }
315 if (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
316 RegionLength = BaseAddress + Length - RegionStart;
317 } else {
318 RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;
319 }
320 //
321 // Set memory attributes according to MTRR attribute and the original attribute of descriptor
322 //
323 gDS->SetMemorySpaceAttributes (
324 RegionStart,
325 RegionLength,
326 (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes)
327 );
328 }
329
330 return EFI_SUCCESS;
331 }
332
333
334 EFI_STATUS
335 SyncCacheConfig (
336 IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol
337 )
338 {
339 EFI_STATUS Status;
340 UINT32 i;
341 UINT32 Descriptor;
342 UINT32 SectionAttributes;
343 EFI_PHYSICAL_ADDRESS NextRegionBase;
344 UINT64 NextRegionLength;
345 UINT64 GcdAttributes;
346 UINT32 NextRegionAttributes = 0;
347 volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
348 UINTN NumberOfDescriptors;
349 EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
350
351
352 DEBUG ((EFI_D_PAGE, "SyncCacheConfig()\n"));
353
354 // This code assumes MMU is enabled and filed with section translations
355 ASSERT (ArmMmuEnabled ());
356
357 //
358 // Get the memory space map from GCD
359 //
360 MemorySpaceMap = NULL;
361 Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
362 ASSERT_EFI_ERROR (Status);
363
364
365 // The GCD implementation maintains its own copy of the state of memory space attributes. GCD needs
366 // to know what the initial memory space attributes are. The CPU Arch. Protocol does not provide a
367 // GetMemoryAttributes function for GCD to get this so we must resort to calling GCD (as if we were
368 // a client) to update its copy of the attributes. This is bad architecture and should be replaced
369 // with a way for GCD to query the CPU Arch. driver of the existing memory space attributes instead.
370
371 // obtain page table base
372 FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)(ArmGetTranslationTableBaseAddress ());
373
374
375 // iterate through each 1MB descriptor
376 NextRegionBase = NextRegionLength = 0;
377 for (i=0; i< FIRST_LEVEL_ENTRY_COUNT; i++) {
378
379 // obtain existing descriptor and make sure it contains a valid Base Address even if it is a fault section
380 Descriptor = FirstLevelTable[i] | (ARM_SECTION_BASE_MASK & (i << ARM_SECTION_BASE_SHIFT));
381
382 // extract attributes (cacheability and permissions)
383 SectionAttributes = Descriptor & 0xDEC;
384
385 // do we already have an existing region (or are we about to finish)?
386 // Skip the first entry, and make sure we close on the last entry
387 if ( (NextRegionLength > 0) || (i == (FIRST_LEVEL_ENTRY_COUNT-1)) ) {
388 // attributes are changing, update attributes in GCD
389 if (SectionAttributes != NextRegionAttributes) {
390
391 // convert section entry attributes to GCD bitmask
392 Status = SectionToGcdAttributes (NextRegionAttributes, &GcdAttributes);
393 ASSERT_EFI_ERROR (Status);
394
395 // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)
396 SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);
397
398
399 // start on a new region
400 NextRegionLength = 0;
401 NextRegionBase = Descriptor & ARM_SECTION_BASE_MASK;
402 }
403 }
404
405 // starting a new region?
406 if (NextRegionLength == 0) {
407 NextRegionAttributes = SectionAttributes;
408 }
409
410 NextRegionLength += ARM_PAGE_DESC_ENTRY_MVA_SIZE;
411
412 } // section entry loop
413
414 return EFI_SUCCESS;
415 }
416
417
418
419 EFI_STATUS
420 UpdatePageEntries (
421 IN EFI_PHYSICAL_ADDRESS BaseAddress,
422 IN UINT64 Length,
423 IN UINT64 Attributes,
424 IN EFI_PHYSICAL_ADDRESS VirtualMask
425 )
426 {
427 EFI_STATUS Status;
428 UINT32 EntryValue;
429 UINT32 EntryMask;
430 UINT32 FirstLevelIdx;
431 UINT32 Offset;
432 UINT32 NumPageEntries;
433 UINT32 Descriptor;
434 UINT32 p;
435 UINT32 PageTableIndex;
436 UINT32 PageTableEntry;
437
438 volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
439 volatile ARM_PAGE_TABLE_ENTRY *PageTable;
440
441 // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)
442 // EntryValue: values at bit positions specified by EntryMask
443 EntryMask = ARM_PAGE_DESC_TYPE_MASK;
444 EntryValue = ARM_PAGE_TYPE_SMALL;
445 // Although the PI spec is unclear on this the GCD guarantees that only
446 // one Attribute bit is set at a time, so we can safely use a switch statement
447 switch (Attributes) {
448 case EFI_MEMORY_UC:
449 // modify cacheability attributes
450 EntryMask |= ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;
451 // map to strongly ordered
452 EntryValue |= 0; // TEX[2:0] = 0, C=0, B=0
453 break;
454
455 case EFI_MEMORY_WC:
456 // modify cacheability attributes
457 EntryMask |= ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;
458 // map to normal non-cachable
459 EntryValue |= (0x1 << ARM_SMALL_PAGE_TEX_SHIFT); // TEX [2:0]= 001 = 0x2, B=0, C=0
460 break;
461
462 case EFI_MEMORY_WT:
463 // modify cacheability attributes
464 EntryMask |= ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;
465 // write through with no-allocate
466 EntryValue |= ARM_PAGE_C; // TEX [2:0] = 0, C=1, B=0
467 break;
468
469 case EFI_MEMORY_WB:
470 // modify cacheability attributes
471 EntryMask |= ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;
472 // write back (with allocate)
473 EntryValue |= (0x1 << ARM_SMALL_PAGE_TEX_SHIFT) | ARM_PAGE_C | ARM_PAGE_B; // TEX [2:0] = 001, C=1, B=1
474 break;
475
476 case EFI_MEMORY_WP:
477 case EFI_MEMORY_XP:
478 case EFI_MEMORY_UCE:
479 // cannot be implemented UEFI definition unclear for ARM
480 // Cause a page fault if these ranges are accessed.
481 EntryValue = ARM_PAGE_TYPE_FAULT;
482 DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting page %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));
483 break;
484
485 default:
486 return EFI_UNSUPPORTED;
487 }
488
489 // obtain page table base
490 FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTranslationTableBaseAddress ();
491
492 // calculate number of 4KB page table entries to change
493 NumPageEntries = Length/EFI_PAGE_SIZE;
494
495 // iterate for the number of 4KB pages to change
496 Offset = 0;
497 for(p=0; p<NumPageEntries; p++) {
498 // calculate index into first level translation table for page table value
499
500 FirstLevelIdx = ((BaseAddress + Offset) & ARM_SECTION_BASE_MASK) >> ARM_SECTION_BASE_SHIFT;
501 ASSERT (FirstLevelIdx < FIRST_LEVEL_ENTRY_COUNT);
502
503 // read the descriptor from the first level page table
504 Descriptor = FirstLevelTable[FirstLevelIdx];
505
506 // does this descriptor need to be converted from section entry to 4K pages?
507 if ((Descriptor & ARM_DESC_TYPE_MASK) != ARM_DESC_TYPE_PAGE_TABLE ) {
508 Status = ConvertSectionToPages (FirstLevelIdx << ARM_SECTION_BASE_SHIFT);
509 if (EFI_ERROR(Status)) {
510 // exit for loop
511 break;
512 }
513
514 // re-read descriptor
515 Descriptor = FirstLevelTable[FirstLevelIdx];
516 }
517
518 // obtain page table base address
519 PageTable = (ARM_PAGE_TABLE_ENTRY *)(Descriptor & ARM_SMALL_PAGE_BASE_MASK);
520
521 // calculate index into the page table
522 PageTableIndex = ((BaseAddress + Offset) & ARM_SMALL_PAGE_INDEX_MASK) >> ARM_SMALL_PAGE_BASE_SHIFT;
523 ASSERT (PageTableIndex < SMALL_PAGE_TABLE_ENTRY_COUNT);
524
525 // get the entry
526 PageTableEntry = PageTable[PageTableIndex];
527
528 // mask off appropriate fields
529 PageTableEntry &= ~EntryMask;
530
531 // mask in new attributes and/or permissions
532 PageTableEntry |= EntryValue;
533
534 if (VirtualMask != 0) {
535 // Make this virtual address point at a physical page
536 PageTableEntry &= ~VirtualMask;
537 }
538
539 // update the entry
540 PageTable[PageTableIndex] = PageTableEntry;
541
542
543 Status = EFI_SUCCESS;
544 Offset += EFI_PAGE_SIZE;
545
546 } // end first level translation table loop
547
548 return Status;
549 }
550
551
552
553 EFI_STATUS
554 UpdateSectionEntries (
555 IN EFI_PHYSICAL_ADDRESS BaseAddress,
556 IN UINT64 Length,
557 IN UINT64 Attributes,
558 IN EFI_PHYSICAL_ADDRESS VirtualMask
559 )
560 {
561 EFI_STATUS Status = EFI_SUCCESS;
562 UINT32 EntryMask;
563 UINT32 EntryValue;
564 UINT32 FirstLevelIdx;
565 UINT32 NumSections;
566 UINT32 i;
567 UINT32 Descriptor;
568
569 volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
570
571 // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)
572 // EntryValue: values at bit positions specified by EntryMask
573
574 // Make sure we handle a section range that is unmapped
575 EntryMask = ARM_DESC_TYPE_MASK;
576 EntryValue = ARM_DESC_TYPE_SECTION;
577
578 // Although the PI spec is unclear on this the GCD guarantees that only
579 // one Attribute bit is set at a time, so we can safely use a switch statement
580 switch(Attributes) {
581 case EFI_MEMORY_UC:
582 // modify cacheability attributes
583 EntryMask |= ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;
584 // map to strongly ordered
585 EntryValue |= 0; // TEX[2:0] = 0, C=0, B=0
586 break;
587
588 case EFI_MEMORY_WC:
589 // modify cacheability attributes
590 EntryMask |= ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;
591 // map to normal non-cachable
592 EntryValue |= (0x1 << ARM_SECTION_TEX_SHIFT); // TEX [2:0]= 001 = 0x2, B=0, C=0
593 break;
594
595 case EFI_MEMORY_WT:
596 // modify cacheability attributes
597 EntryMask |= ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;
598 // write through with no-allocate
599 EntryValue |= ARM_SECTION_C; // TEX [2:0] = 0, C=1, B=0
600 break;
601
602 case EFI_MEMORY_WB:
603 // modify cacheability attributes
604 EntryMask |= ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;
605 // write back (with allocate)
606 EntryValue |= (0x1 << ARM_SECTION_TEX_SHIFT) | ARM_SECTION_C | ARM_SECTION_B; // TEX [2:0] = 001, C=1, B=1
607 break;
608
609 case EFI_MEMORY_WP:
610 case EFI_MEMORY_XP:
611 case EFI_MEMORY_RP:
612 case EFI_MEMORY_UCE:
613 // cannot be implemented UEFI definition unclear for ARM
614 // Cause a page fault if these ranges are accessed.
615 EntryValue = ARM_DESC_TYPE_FAULT;
616 DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting section %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));
617 break;
618
619
620 default:
621 return EFI_UNSUPPORTED;
622 }
623
624 // obtain page table base
625 FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTranslationTableBaseAddress ();
626
627 // calculate index into first level translation table for start of modification
628 FirstLevelIdx = (BaseAddress & ARM_SECTION_BASE_MASK) >> ARM_SECTION_BASE_SHIFT;
629 ASSERT (FirstLevelIdx < FIRST_LEVEL_ENTRY_COUNT);
630
631 // calculate number of 1MB first level entries this applies to
632 NumSections = Length / ARM_PAGE_DESC_ENTRY_MVA_SIZE;
633
634 // iterate through each descriptor
635 for(i=0; i<NumSections; i++) {
636 Descriptor = FirstLevelTable[FirstLevelIdx + i];
637
638 // has this descriptor already been coverted to pages?
639 if ((Descriptor & ARM_DESC_TYPE_MASK) != ARM_DESC_TYPE_PAGE_TABLE ) {
640 // forward this 1MB range to page table function instead
641 Status = UpdatePageEntries ((FirstLevelIdx + i) << ARM_SECTION_BASE_SHIFT, ARM_PAGE_DESC_ENTRY_MVA_SIZE, Attributes, VirtualMask);
642 } else {
643 // still a section entry
644
645 // mask off appropriate fields
646 Descriptor &= ~EntryMask;
647
648 // mask in new attributes and/or permissions
649 Descriptor |= EntryValue;
650 if (VirtualMask != 0) {
651 Descriptor &= ~VirtualMask;
652 }
653
654 FirstLevelTable[FirstLevelIdx + i] = Descriptor;
655
656 Status = EFI_SUCCESS;
657 }
658 }
659
660 return Status;
661 }
662
663 EFI_STATUS
664 ConvertSectionToPages (
665 IN EFI_PHYSICAL_ADDRESS BaseAddress
666 )
667 {
668 EFI_STATUS Status;
669 EFI_PHYSICAL_ADDRESS PageTableAddr;
670 UINT32 FirstLevelIdx;
671 UINT32 SectionDescriptor;
672 UINT32 PageTableDescriptor;
673 UINT32 PageDescriptor;
674 UINT32 i;
675
676 volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
677 volatile ARM_PAGE_TABLE_ENTRY *PageTable;
678
679 DEBUG ((EFI_D_PAGE, "Converting section at 0x%x to pages\n", (UINTN)BaseAddress));
680
681 // obtain page table base
682 FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTranslationTableBaseAddress ();
683
684 // calculate index into first level translation table for start of modification
685 FirstLevelIdx = (BaseAddress & ARM_SECTION_BASE_MASK) >> ARM_SECTION_BASE_SHIFT;
686 ASSERT (FirstLevelIdx < FIRST_LEVEL_ENTRY_COUNT);
687
688 // get section attributes and convert to page attributes
689 SectionDescriptor = FirstLevelTable[FirstLevelIdx];
690 PageDescriptor = ARM_PAGE_TYPE_SMALL;
691 PageDescriptor |= ((SectionDescriptor & ARM_SECTION_TEX_MASK) >> ARM_SECTION_TEX_SHIFT) << ARM_SMALL_PAGE_TEX_SHIFT;
692 if ((SectionDescriptor & ARM_SECTION_B) != 0) {
693 PageDescriptor |= ARM_PAGE_B;
694 }
695 if ((SectionDescriptor & ARM_SECTION_C) != 0) {
696 PageDescriptor |= ARM_PAGE_C;
697 }
698 PageDescriptor |= ((SectionDescriptor & ARM_SECTION_AP10_MASK) >> ARM_SECTION_AP10_SHIFT) << ARM_PAGE_AP10_SHIFT;
699 if ((SectionDescriptor & ARM_SECTION_AP2) != 0) {
700 PageDescriptor |= ARM_PAGE_AP2;
701 }
702 if ((SectionDescriptor & ARM_SECTION_XN) != 0) {
703 PageDescriptor |= ARM_PAGE_TYPE_SMALL_XN;
704 }
705 if ((SectionDescriptor & ARM_SECTION_nG) != 0) {
706 PageDescriptor |= ARM_PAGE_nG;
707 }
708 if ((SectionDescriptor & ARM_SECTION_S) != 0) {
709 PageDescriptor |= ARM_PAGE_S;
710 }
711
712 // allocate a page table for the 4KB entries (we use up a full page even though we only need 1KB)
713 Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData, 1, &PageTableAddr);
714 if (EFI_ERROR(Status)) {
715 return Status;
716 }
717
718 PageTable = (volatile ARM_PAGE_TABLE_ENTRY *)(UINTN)PageTableAddr;
719
720 // write the page table entries out
721 for (i=0; i<(ARM_PAGE_DESC_ENTRY_MVA_SIZE/EFI_PAGE_SIZE); i++) {
722 PageTable[i] = ((BaseAddress + (i << 12)) & ARM_SMALL_PAGE_BASE_MASK) | PageDescriptor;
723 }
724
725 // flush d-cache so descriptors make it back to uncached memory for subsequent table walks
726 InvalidateDataCacheRange ((VOID *)(UINTN)PageTableAddr, EFI_PAGE_SIZE);
727
728 // formulate page table entry, Domain=0, NS=0
729 PageTableDescriptor = (((UINTN)PageTableAddr) & ARM_PAGE_DESC_BASE_MASK) | ARM_DESC_TYPE_PAGE_TABLE;
730
731 // write the page table entry out, repalcing section entry
732 FirstLevelTable[FirstLevelIdx] = PageTableDescriptor;
733
734 return EFI_SUCCESS;
735 }
736
737
738
739 EFI_STATUS
740 SetMemoryAttributes (
741 IN EFI_PHYSICAL_ADDRESS BaseAddress,
742 IN UINT64 Length,
743 IN UINT64 Attributes,
744 IN EFI_PHYSICAL_ADDRESS VirtualMask
745 )
746 {
747 EFI_STATUS Status;
748
749 if(((BaseAddress & 0xFFFFF) == 0) && ((Length & 0xFFFFF) == 0)) {
750 // is the base and length a multiple of 1 MB?
751 DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));
752 Status = UpdateSectionEntries (BaseAddress, Length, Attributes, VirtualMask);
753 } else {
754 // base and/or length is not a multiple of 1 MB
755 DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU page 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));
756 Status = UpdatePageEntries (BaseAddress, Length, Attributes, VirtualMask);
757 }
758
759 // flush d-cache so descriptors make it back to uncached memory for subsequent table walks
760 // flush and invalidate pages
761 ArmCleanInvalidateDataCache ();
762
763 ArmInvalidateInstructionCache ();
764
765 // invalidate all TLB entries so changes are synced
766 ArmInvalidateTlb ();
767
768 return Status;
769 }
770
771
772 /**
773 This function modifies the attributes for the memory region specified by BaseAddress and
774 Length from their current attributes to the attributes specified by Attributes.
775
776 @param This The EFI_CPU_ARCH_PROTOCOL instance.
777 @param BaseAddress The physical address that is the start address of a memory region.
778 @param Length The size in bytes of the memory region.
779 @param Attributes The bit mask of attributes to set for the memory region.
780
781 @retval EFI_SUCCESS The attributes were set for the memory region.
782 @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by
783 BaseAddress and Length cannot be modified.
784 @retval EFI_INVALID_PARAMETER Length is zero.
785 @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of
786 the memory resource range.
787 @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory
788 resource range specified by BaseAddress and Length.
789 The bit mask of attributes is not support for the memory resource
790 range specified by BaseAddress and Length.
791
792 **/
793 EFI_STATUS
794 EFIAPI
795 CpuSetMemoryAttributes (
796 IN EFI_CPU_ARCH_PROTOCOL *This,
797 IN EFI_PHYSICAL_ADDRESS BaseAddress,
798 IN UINT64 Length,
799 IN UINT64 Attributes
800 )
801 {
802 DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx)\n", BaseAddress, Length, Attributes));
803 if ( ((BaseAddress & (EFI_PAGE_SIZE-1)) != 0) || ((Length & (EFI_PAGE_SIZE-1)) != 0)){
804 // minimum granularity is EFI_PAGE_SIZE (4KB on ARM)
805 DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx): minimum ganularity is EFI_PAGE_SIZE\n", BaseAddress, Length, Attributes));
806 return EFI_UNSUPPORTED;
807 }
808
809 return SetMemoryAttributes (BaseAddress, Length, Attributes, 0);
810 }
811
812
813
814 //
815 // Add a new protocol to support
816 //
817
818 EFI_STATUS
819 EFIAPI
820 CpuConvertPagesToUncachedVirtualAddress (
821 IN VIRTUAL_UNCACHED_PAGES_PROTOCOL *This,
822 IN EFI_PHYSICAL_ADDRESS Address,
823 IN UINTN Length,
824 IN EFI_PHYSICAL_ADDRESS VirtualMask,
825 OUT UINT64 *Attributes OPTIONAL
826 )
827 {
828 EFI_STATUS Status;
829 EFI_GCD_MEMORY_SPACE_DESCRIPTOR GcdDescriptor;
830
831
832 if (Attributes != NULL) {
833 Status = gDS->GetMemorySpaceDescriptor (Address, &GcdDescriptor);
834 if (!EFI_ERROR (Status)) {
835 *Attributes = GcdDescriptor.Attributes;
836 }
837 }
838
839 //
840 // Make this address range page fault if accessed. If it is a DMA buffer than this would
841 // be the PCI address. Code should always use the CPU address, and we will or in VirtualMask
842 // to that address.
843 //
844 Status = SetMemoryAttributes (Address, Length, EFI_MEMORY_WP, 0);
845 if (!EFI_ERROR (Status)) {
846 Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_UC, VirtualMask);
847 }
848
849 return Status;
850 }
851
852
853 EFI_STATUS
854 EFIAPI
855 CpuReconvertPagesPages (
856 IN VIRTUAL_UNCACHED_PAGES_PROTOCOL *This,
857 IN EFI_PHYSICAL_ADDRESS Address,
858 IN UINTN Length,
859 IN EFI_PHYSICAL_ADDRESS VirtualMask,
860 IN UINT64 Attributes
861 )
862 {
863 EFI_STATUS Status;
864 DEBUG ((EFI_D_ERROR, "CpuReconvertPagesPages(%lx, %x, %lx, %lx)\n", Address, Length, VirtualMask, Attributes));
865 ASSERT (FALSE);
866 //
867 // Unmap the alaised Address
868 //
869 Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_WP, 0);
870 if (!EFI_ERROR (Status)) {
871 //
872 // Restore atttributes
873 //
874 Status = SetMemoryAttributes (Address, Length, Attributes, 0);
875 }
876
877 return Status;
878 }
879
880
881 VIRTUAL_UNCACHED_PAGES_PROTOCOL gVirtualUncachedPages = {
882 CpuConvertPagesToUncachedVirtualAddress,
883 CpuReconvertPagesPages
884 };
885
886
887
888