Working on adding paging to the CpuDxe driver so it can update cachablity. At this...
[mirror_edk2.git] / ArmPkg / Drivers / CpuDxe / Mmu.c
1 /*++
2
3 Copyright (c) 2009, Hewlett-Packard Company
4 Portions copyright (c) 2010, Apple Inc. All rights reserved.
5
6 All rights reserved. This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14
15 --*/
16
17 #include "CpuDxe.h"
18
19 //
20 // Translation/page table definitions
21 //
22
23 // First Level Descriptors
24 typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR;
25
26 // memory space covered by a first level descriptor
27 #define ARM_PAGE_DESC_ENTRY_MVA_SIZE 0x00100000 // 1MB
28
29 // number of first level descriptors to cover entire 32-bit memory space
30 #define FIRST_LEVEL_ENTRY_COUNT (0xFFFFFFFF / ARM_PAGE_DESC_ENTRY_MVA_SIZE + 1)
31
32
33 // page table 1st level descriptor entries
34 #define ARM_PAGE_DESC_BASE_MASK 0xFFFFFC00
35 #define ARM_PAGE_DESC_BASE_SHFIT 10
36 #define ARM_PAGE_DESC_DOMAIN_MASK 0x000001E0
37 #define ARM_PAGE_DESC_DOMAIN_SHIFT 5
38 #define ARM_PAGE_DESC_NS 0x00000008
39
40 #define ARM_FIRST_LEVEL_DESC_ALIGN 0x00004000 // 16KB
41
42 // section 1st level desriptor entries
43 #define ARM_SECTION_BASE_MASK 0xFFF00000
44 #define ARM_SECTION_BASE_SHIFT 20
45 #define ARM_SECTION_NS 0x00080000
46 #define ARM_SECTION_nG 0x00020000
47 #define ARM_SECTION_S 0x00010000
48 #define ARM_SECTION_AP2 0x00008000
49 #define ARM_SECTION_TEX_MASK 0x00007000
50 #define ARM_SECTION_TEX_SHIFT 12
51 #define ARM_SECTION_AP10_MASK 0x00000C00
52 #define ARM_SECTION_AP10_SHIFT 10
53 #define ARM_SECTION_DOMAIN_MASK 0x000001E0
54 #define ARM_SECTION_DOMAIN_SHIFT 5
55 #define ARM_SECTION_XN 0x00000010
56 #define ARM_SECTION_C 0x00000008
57 #define ARM_SECTION_B 0x00000004
58
59 // section level AP[2:0] definitions
60 #define ARM_SECTION_AP_NO_ACCESS 0 // AP[2:0] = 0
61 #define ARM_SECTION_AP_READ_WRITE ARM_SECTION_AP10_MASK // AP[2:0] = 011
62 #define ARM_SECTION_AP_READ_ONLY (ARM_SECTION_AP2 | ARM_SECTION_AP10_MASK) // AP[2:0] = 111
63
64 // common 1st level descriptor fields
65 #define ARM_DESC_TYPE_MASK 0x00000003
66
67 // descriptor type values
68 #define ARM_DESC_TYPE_FAULT 0x0
69 #define ARM_DESC_TYPE_PAGE_TABLE 0x1
70 #define ARM_DESC_TYPE_SECTION 0x2
71
72
73 // Second Level Descriptors
74 typedef UINT32 ARM_PAGE_TABLE_ENTRY;
75
76 // small page 2nd level descriptor entries
77 #define ARM_SMALL_PAGE_BASE_MASK 0xFFFFF000
78 #define ARM_SMALL_PAGE_INDEX_MASK 0x000FF000
79 #define ARM_SMALL_PAGE_BASE_SHIFT 12
80 #define ARM_SMALL_PAGE_TEX_MASK 0x000001C0
81 #define ARM_SMALL_PAGE_TEX_SHIFT 6
82 #define ARM_SMALL_PAGE_XN 0x00000001
83
84 // large page 2nd level descriptor entries
85 #define ARM_LARGE_PAGE_BASE_MASK 0xFFFF0000
86 #define ARM_LARGE_PAGE_BASE_SHIFT 16
87 #define ARM_LARGE_PAGE_TEX_MASK 0x00007000
88 #define ARM_LARGE_PAGE_TEX_SHIFT 12
89 #define ARM_LARGE_PAGE_XN 0x00008000
90
91 // common 2nd level desriptor fields
92 #define ARM_PAGE_nG 0x00000800
93 #define ARM_PAGE_S 0x00000400
94 #define ARM_PAGE_AP2 0x00000200
95 #define ARM_PAGE_AP10_MASK 0x00000030
96 #define ARM_PAGE_AP10_SHIFT 4
97 #define ARM_PAGE_C 0x00000008
98 #define ARM_PAGE_B 0x00000004
99 #define ARM_PAGE_DESC_TYPE_MASK 0x00000003
100
101 // descriptor type values
102 #define ARM_PAGE_TYPE_FAULT 0x0
103 #define ARM_PAGE_TYPE_LARGE 0x1
104 #define ARM_PAGE_TYPE_SMALL 0x2
105 #define ARM_PAGE_TYPE_SMALL_XN 0x3
106
107 #define SMALL_PAGE_TABLE_ENTRY_COUNT (ARM_PAGE_DESC_ENTRY_MVA_SIZE / EFI_PAGE_SIZE)
108
109
110 // Translation Table Base 0 fields
111 #define ARM_TTBR0_BASE_MASK 0xFFFFC000
112 #define ARM_TTBR0_BASE_SHIFT 14
113 #define ARM_TTRB0_NOS 0x00000020
114
115 // define the combination of interesting attributes: cacheability and access permissions
116 #define ARM_SECTION_CACHEABILITY_MASK ( ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B )
117 #define ARM_SECTION_RW_PERMISSIONS_MASK ( ARM_SECTION_AP2 | ARM_SECTION_AP10_MASK )
118 #define ARM_DESCRIPTOR_ATTRIBUTES ( ARM_SECTION_CACHEABILITY_MASK | ARM_SECTION_RW_PERMISSIONS_MASK | ARM_SECTION_XN )
119
120 // cacheability values for section entries
121 #define ARM_SECTION_STRONGLY_ORDERED 0
122 #define ARM_SECTION_SHAREABLE_DEVICE ARM_SECTION_B
123 #define ARM_SECTION_WRITE_THROUGH ARM_SECTION_C
124 #define ARM_SECTION_WRITE_BACK_NWA ( ARM_SECTION_C| ARM_SECTION_B )
125 #define ARM_SECTION_NORMAL_UNCACHEABLE ( 0x1 << ARM_SECTION_TEX_SHIFT )
126 #define ARM_SECTION_WRITE_BACK ( ( 0x1 << ARM_SECTION_TEX_SHIFT ) | ARM_SECTION_C | ARM_SECTION_B )
127 #define ARM_SECTION_NONSHAREABLE_DEVICE ( 0x2 << ARM_SECTION_TEX_SHIFT )
128
129 // permissions values for section entries
130 #define ARM_SECTION_NO_ACCESS 0
131 #define ARM_SECTION_PRIV_ACCESS_ONLY ( 0x1 << ARM_SECTION_AP10_SHIFT)
132 #define ARM_SECTION_USER_READ_ONLY ( 0x2 << ARM_SECTION_AP10_SHIFT)
133 #define ARM_SECTION_FULL_ACCESS ( 0x3 << ARM_SECTION_AP10_SHIFT)
134 #define ARM_SECTION_PRIV_READ_ONLY ( ARM_SECTION_AP2 | (0x1 << ARM_SECTION_AP10_SHIFT) )
135 #define ARM_SECTION_READ_ONLY_DEP ( ARM_SECTION_AP2 | (0x2 << ARM_SECTION_AP10_SHIFT) )
136 #define ARM_SECTION_READ_ONLY ( ARM_SECTION_AP2 | (0x3 << ARM_SECTION_AP10_SHIFT) )
137
138
139
140 EFI_STATUS
141 SectionToGcdAttributes (
142 IN UINT32 SectionAttributes,
143 OUT UINT64 *GcdAttributes
144 )
145 {
146 *GcdAttributes = 0;
147
148 // determine cacheability attributes
149 switch(SectionAttributes & ARM_SECTION_CACHEABILITY_MASK) {
150 case ARM_SECTION_STRONGLY_ORDERED:
151 *GcdAttributes |= EFI_MEMORY_UC;
152 break;
153 case ARM_SECTION_SHAREABLE_DEVICE:
154 *GcdAttributes |= EFI_MEMORY_UC;
155 break;
156 case ARM_SECTION_WRITE_THROUGH:
157 *GcdAttributes |= EFI_MEMORY_WT;
158 break;
159 case ARM_SECTION_WRITE_BACK_NWA:
160 *GcdAttributes |= EFI_MEMORY_WB;
161 break;
162 case ARM_SECTION_NORMAL_UNCACHEABLE:
163 *GcdAttributes |= EFI_MEMORY_WC;
164 break;
165 case ARM_SECTION_WRITE_BACK:
166 *GcdAttributes |= EFI_MEMORY_WB;
167 break;
168 case ARM_SECTION_NONSHAREABLE_DEVICE:
169 *GcdAttributes |= EFI_MEMORY_UC;
170 break;
171 default:
172 return EFI_UNSUPPORTED;
173 break;
174 }
175
176 // determine protection attributes
177 switch(SectionAttributes & ARM_SECTION_RW_PERMISSIONS_MASK) {
178 case ARM_SECTION_NO_ACCESS: // no read, no write
179 *GcdAttributes |= EFI_MEMORY_WP | EFI_MEMORY_RP;
180 break;
181
182 case ARM_SECTION_PRIV_ACCESS_ONLY:
183 case ARM_SECTION_FULL_ACCESS:
184 // normal read/write access, do not add additional attributes
185 break;
186
187 // read only cases map to write-protect
188 case ARM_SECTION_PRIV_READ_ONLY:
189 case ARM_SECTION_READ_ONLY_DEP:
190 case ARM_SECTION_READ_ONLY:
191 *GcdAttributes |= EFI_MEMORY_WP;
192 break;
193
194 default:
195 return EFI_UNSUPPORTED;
196 break;
197 }
198
199 // now process eXectue Never attribute
200 if ((SectionAttributes & ARM_SECTION_XN) != 0 ) {
201 *GcdAttributes |= EFI_MEMORY_XP;
202 }
203
204 return EFI_SUCCESS;
205 }
206
207
208
209 EFI_STATUS
210 SyncCacheConfig (
211 IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol
212 )
213 {
214 EFI_STATUS Status;
215 UINT32 i;
216 UINT32 Descriptor;
217 UINT32 SectionAttributes;
218 EFI_PHYSICAL_ADDRESS NextRegionBase;
219 UINT64 NextRegionLength;
220 UINT64 GcdAttributes;
221 UINT32 NextRegionAttributes = 0;
222 volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
223
224
225 // This code assumes MMU is enabled and filed with section translations
226 ASSERT (ArmMmuEnabled ());
227
228
229 // The GCD implementation maintains its own copy of the state of memory space attributes. GCD needs
230 // to know what the initial memory space attributes are. The CPU Arch. Protocol does not provide a
231 // GetMemoryAttributes function for GCD to get this so we must resort to calling GCD (as if we were
232 // a client) to update its copy of the attributes. This is bad architecture and should be replaced
233 // with a way for GCD to query the CPU Arch. driver of the existing memory space attributes instead.
234
235 // obtain page table base
236 FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)(ArmGetTranslationTableBaseAddress ());
237
238
239 // iterate through each 1MB descriptor
240 NextRegionBase = NextRegionLength = 0;
241 for (i=0; i< FIRST_LEVEL_ENTRY_COUNT; i++) {
242
243 // obtain existing descriptor
244 Descriptor = FirstLevelTable[i];
245
246 // extract attributes (cacheability and permissions)
247 SectionAttributes = Descriptor & 0xDEC;
248
249 // do we already have an existing region (or are we about to finish)?
250 // Skip the first entry, and make sure we close on the last entry
251 if ( (NextRegionLength > 0) || (i == (FIRST_LEVEL_ENTRY_COUNT-1)) ) {
252 // attributes are changing, update attributes in GCD
253 if (SectionAttributes != NextRegionAttributes) {
254
255 // convert section entry attributes to GCD bitmask
256 Status = SectionToGcdAttributes (NextRegionAttributes, &GcdAttributes);
257 ASSERT_EFI_ERROR(Status);
258
259 // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)
260 Status = gDS->SetMemorySpaceAttributes (NextRegionBase, NextRegionLength, GcdAttributes);
261 ASSERT_EFI_ERROR(Status);
262
263 // start on a new region
264 NextRegionLength = 0;
265 NextRegionBase = Descriptor & ARM_SECTION_BASE_MASK;
266 }
267 }
268
269 // starting a new region?
270 if (NextRegionLength == 0) {
271 NextRegionAttributes = SectionAttributes;
272 }
273
274 NextRegionLength += ARM_PAGE_DESC_ENTRY_MVA_SIZE;
275
276 } // section entry loop
277
278 return EFI_SUCCESS;
279 }
280
281
282
283 EFI_STATUS
284 UpdatePageEntries (
285 IN EFI_PHYSICAL_ADDRESS BaseAddress,
286 IN UINT64 Length,
287 IN UINT64 Attributes,
288 IN EFI_PHYSICAL_ADDRESS VirtualMask
289 )
290 {
291 EFI_STATUS Status;
292 UINT32 EntryValue;
293 UINT32 EntryMask;
294 UINT32 FirstLevelIdx;
295 UINT32 Offset;
296 UINT32 NumPageEntries;
297 UINT32 Descriptor;
298 UINT32 p;
299 UINT32 PageTableIndex;
300 UINT32 PageTableEntry;
301
302 volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
303 volatile ARM_PAGE_TABLE_ENTRY *PageTable;
304
305 // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)
306 // EntryValue: values at bit positions specified by EntryMask
307
308 // Although the PI spec is unclear on this the GCD guarantees that only
309 // one Attribute bit is set at a time, so we can safely use a switch statement
310 switch (Attributes) {
311 case EFI_MEMORY_UC:
312 // modify cacheability attributes
313 EntryMask = ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;
314 // map to strongly ordered
315 EntryValue = 0; // TEX[2:0] = 0, C=0, B=0
316 break;
317
318 case EFI_MEMORY_WC:
319 // modify cacheability attributes
320 EntryMask = ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;
321 // map to normal non-cachable
322 EntryValue = (0x1 << ARM_SMALL_PAGE_TEX_SHIFT); // TEX [2:0]= 001 = 0x2, B=0, C=0
323 break;
324
325 case EFI_MEMORY_WT:
326 // modify cacheability attributes
327 EntryMask = ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;
328 // write through with no-allocate
329 EntryValue = ARM_PAGE_C; // TEX [2:0] = 0, C=1, B=0
330 break;
331
332 case EFI_MEMORY_WB:
333 // modify cacheability attributes
334 EntryMask = ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;
335 // write back (with allocate)
336 EntryValue = (0x1 << ARM_SMALL_PAGE_TEX_SHIFT) | ARM_PAGE_C | ARM_PAGE_B; // TEX [2:0] = 001, C=1, B=1
337 break;
338
339 case EFI_MEMORY_WP:
340 case EFI_MEMORY_XP:
341 case EFI_MEMORY_UCE:
342 // cannot be implemented UEFI definition unclear for ARM
343 // Cause a page fault if these ranges are accessed.
344 EntryMask = 0x3;
345 EntryValue = 0;
346 DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting page %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));
347 break;
348
349 default:
350 return EFI_UNSUPPORTED;
351 break;
352 }
353
354 // obtain page table base
355 FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTranslationTableBaseAddress ();
356
357 // calculate number of 4KB page table entries to change
358 NumPageEntries = Length/EFI_PAGE_SIZE;
359
360 // iterate for the number of 4KB pages to change
361 Offset = 0;
362 for(p=0; p<NumPageEntries; p++) {
363 // calculate index into first level translation table for page table value
364
365 FirstLevelIdx = ((BaseAddress + Offset) & ARM_SECTION_BASE_MASK) >> ARM_SECTION_BASE_SHIFT;
366 ASSERT (FirstLevelIdx < FIRST_LEVEL_ENTRY_COUNT);
367
368 // read the descriptor from the first level page table
369 Descriptor = FirstLevelTable[FirstLevelIdx];
370
371 // does this descriptor need to be converted from section entry to 4K pages?
372 if ((Descriptor & ARM_DESC_TYPE_MASK) == ARM_DESC_TYPE_SECTION ) {
373 Status = ConvertSectionToPages (FirstLevelIdx << ARM_SECTION_BASE_SHIFT);
374 if (EFI_ERROR(Status)) {
375 // exit for loop
376 break;
377 }
378
379 // re-read descriptor
380 Descriptor = FirstLevelTable[FirstLevelIdx];
381 }
382
383 // obtain page table base address
384 PageTable = (ARM_PAGE_TABLE_ENTRY *)(Descriptor & ARM_SMALL_PAGE_BASE_MASK);
385
386 // calculate index into the page table
387 PageTableIndex = ((BaseAddress + Offset) & ARM_SMALL_PAGE_INDEX_MASK) >> ARM_SMALL_PAGE_BASE_SHIFT;
388 ASSERT(PageTableIndex < SMALL_PAGE_TABLE_ENTRY_COUNT);
389
390 // get the entry
391 PageTableEntry = PageTable[PageTableIndex];
392
393 // mask off appropriate fields
394 PageTableEntry &= ~EntryMask;
395
396 // mask in new attributes and/or permissions
397 PageTableEntry |= EntryValue;
398
399 if (VirtualMask != 0) {
400 // Make this virtual address point at a physical page
401 PageTableEntry &= ~VirtualMask;
402 }
403
404 // update the entry
405 PageTable[PageTableIndex] = PageTableEntry;
406
407
408 Status = EFI_SUCCESS;
409 Offset += EFI_PAGE_SIZE;
410
411 } // end first level translation table loop
412
413 return Status;
414 }
415
416
417
418 EFI_STATUS
419 UpdateSectionEntries (
420 IN EFI_PHYSICAL_ADDRESS BaseAddress,
421 IN UINT64 Length,
422 IN UINT64 Attributes,
423 IN EFI_PHYSICAL_ADDRESS VirtualMask
424 )
425 {
426 EFI_STATUS Status = EFI_SUCCESS;
427 UINT32 EntryMask;
428 UINT32 EntryValue;
429 UINT32 FirstLevelIdx;
430 UINT32 NumSections;
431 UINT32 i;
432 UINT32 Descriptor;
433
434 volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
435
436 // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)
437 // EntryValue: values at bit positions specified by EntryMask
438
439 // Although the PI spec is unclear on this the GCD guarantees that only
440 // one Attribute bit is set at a time, so we can safely use a switch statement
441 switch(Attributes) {
442 case EFI_MEMORY_UC:
443 // modify cacheability attributes
444 EntryMask = ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;
445 // map to strongly ordered
446 EntryValue = 0; // TEX[2:0] = 0, C=0, B=0
447 break;
448
449 case EFI_MEMORY_WC:
450 // modify cacheability attributes
451 EntryMask = ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;
452 // map to normal non-cachable
453 EntryValue = (0x1 << ARM_SECTION_TEX_SHIFT); // TEX [2:0]= 001 = 0x2, B=0, C=0
454 break;
455
456 case EFI_MEMORY_WT:
457 // modify cacheability attributes
458 EntryMask = ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;
459 // write through with no-allocate
460 EntryValue = ARM_SECTION_C; // TEX [2:0] = 0, C=1, B=0
461 break;
462
463 case EFI_MEMORY_WB:
464 // modify cacheability attributes
465 EntryMask = ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;
466 // write back (with allocate)
467 EntryValue = (0x1 << ARM_SECTION_TEX_SHIFT) | ARM_SECTION_C | ARM_SECTION_B; // TEX [2:0] = 001, C=1, B=1
468 break;
469
470 case EFI_MEMORY_WP:
471 case EFI_MEMORY_XP:
472 case EFI_MEMORY_RP:
473 case EFI_MEMORY_UCE:
474 // cannot be implemented UEFI definition unclear for ARM
475 // Cause a page fault if these ranges are accessed.
476 EntryMask = 0x3;
477 EntryValue = 0;
478 DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting section %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));
479 break;
480
481
482 default:
483 return EFI_UNSUPPORTED;
484 break;
485 }
486
487 // obtain page table base
488 FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTranslationTableBaseAddress ();
489
490 // calculate index into first level translation table for start of modification
491 FirstLevelIdx = (BaseAddress & ARM_SECTION_BASE_MASK) >> ARM_SECTION_BASE_SHIFT;
492 ASSERT (FirstLevelIdx < FIRST_LEVEL_ENTRY_COUNT);
493
494 // calculate number of 1MB first level entries this applies to
495 NumSections = Length / ARM_PAGE_DESC_ENTRY_MVA_SIZE;
496
497 // iterate through each descriptor
498 for(i=0; i<NumSections; i++) {
499 Descriptor = FirstLevelTable[FirstLevelIdx + i];
500
501 // has this descriptor already been coverted to pages?
502 if ((Descriptor & ARM_DESC_TYPE_MASK) == ARM_DESC_TYPE_PAGE_TABLE ) {
503 // forward this 1MB range to page table function instead
504 Status = UpdatePageEntries ((FirstLevelIdx + i) << ARM_SECTION_BASE_SHIFT, ARM_PAGE_DESC_ENTRY_MVA_SIZE, Attributes, VirtualMask);
505 } else {
506 // still a section entry
507
508 // mask off appropriate fields
509 Descriptor &= ~EntryMask;
510
511 // mask in new attributes and/or permissions
512 Descriptor |= EntryValue;
513 if (VirtualMask != 0) {
514 Descriptor &= ~VirtualMask;
515 }
516
517 FirstLevelTable[FirstLevelIdx + i] = Descriptor;
518
519 Status = EFI_SUCCESS;
520 }
521 }
522
523 return Status;
524 }
525
526 EFI_STATUS
527 ConvertSectionToPages (
528 IN EFI_PHYSICAL_ADDRESS BaseAddress
529 )
530 {
531 EFI_STATUS Status;
532 EFI_PHYSICAL_ADDRESS PageTableAddr;
533 UINT32 FirstLevelIdx;
534 UINT32 SectionDescriptor;
535 UINT32 PageTableDescriptor;
536 UINT32 PageDescriptor;
537 UINT32 i;
538
539 volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
540 volatile ARM_PAGE_TABLE_ENTRY *PageTable;
541
542 DEBUG ((EFI_D_PAGE, "Converting section at 0x%x to pages\n", (UINTN)BaseAddress));
543
544 // obtain page table base
545 FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTranslationTableBaseAddress ();
546
547 // calculate index into first level translation table for start of modification
548 FirstLevelIdx = (BaseAddress & ARM_SECTION_BASE_MASK) >> ARM_SECTION_BASE_SHIFT;
549 ASSERT(FirstLevelIdx < FIRST_LEVEL_ENTRY_COUNT);
550
551 // get section attributes and convert to page attributes
552 SectionDescriptor = FirstLevelTable[FirstLevelIdx];
553 PageDescriptor = ARM_PAGE_TYPE_SMALL;
554 PageDescriptor |= ((SectionDescriptor & ARM_SECTION_TEX_MASK) >> ARM_SECTION_TEX_SHIFT) << ARM_SMALL_PAGE_TEX_SHIFT;
555 if ((SectionDescriptor & ARM_SECTION_B) != 0) {
556 PageDescriptor |= ARM_PAGE_B;
557 }
558 if ((SectionDescriptor & ARM_SECTION_C) != 0) {
559 PageDescriptor |= ARM_PAGE_C;
560 }
561 PageDescriptor |= ((SectionDescriptor & ARM_SECTION_AP10_MASK) >> ARM_SECTION_AP10_SHIFT) << ARM_PAGE_AP10_SHIFT;
562 if ((SectionDescriptor & ARM_SECTION_AP2) != 0) {
563 PageDescriptor |= ARM_PAGE_AP2;
564 }
565 if ((SectionDescriptor & ARM_SECTION_XN) != 0) {
566 PageDescriptor |= ARM_PAGE_TYPE_SMALL_XN;
567 }
568 if ((SectionDescriptor & ARM_SECTION_nG) != 0) {
569 PageDescriptor |= ARM_PAGE_nG;
570 }
571 if ((SectionDescriptor & ARM_SECTION_S) != 0) {
572 PageDescriptor |= ARM_PAGE_S;
573 }
574
575 // allocate a page table for the 4KB entries (we use up a full page even though we only need 1KB)
576 Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData, 1, &PageTableAddr);
577 if (EFI_ERROR(Status)) {
578 return Status;
579 }
580
581 PageTable = (volatile ARM_PAGE_TABLE_ENTRY *)(UINTN)PageTableAddr;
582
583 // write the page table entries out
584 for (i=0; i<(ARM_PAGE_DESC_ENTRY_MVA_SIZE/EFI_PAGE_SIZE); i++) {
585 PageTable[i] = ((BaseAddress + (i << 12)) & ARM_SMALL_PAGE_BASE_MASK) | PageDescriptor;
586 }
587
588 // flush d-cache so descriptors make it back to uncached memory for subsequent table walks
589 // TODO: change to use only PageTable base and length
590 // ArmInvalidateDataCache ();
591 InvalidateDataCacheRange ((VOID *)&PageTableAddr, EFI_PAGE_SIZE);
592
593 // formulate page table entry, Domain=0, NS=0
594 PageTableDescriptor = (((UINTN)PageTableAddr) & ARM_PAGE_DESC_BASE_MASK) | ARM_DESC_TYPE_PAGE_TABLE;
595
596 // write the page table entry out, repalcing section entry
597 FirstLevelTable[FirstLevelIdx] = PageTableDescriptor;
598
599 return EFI_SUCCESS;
600 }
601
602
603
604 EFI_STATUS
605 SetMemoryAttributes (
606 IN EFI_PHYSICAL_ADDRESS BaseAddress,
607 IN UINT64 Length,
608 IN UINT64 Attributes,
609 IN EFI_PHYSICAL_ADDRESS VirtualMask
610 )
611 {
612 EFI_STATUS Status;
613
614 if(((BaseAddress & 0xFFFFF) == 0) && ((Length & 0xFFFFF) == 0)) {
615 // is the base and length a multiple of 1 MB?
616 DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));
617 Status = UpdateSectionEntries (BaseAddress, Length, Attributes, VirtualMask);
618 } else {
619 // base and/or length is not a multiple of 1 MB
620 DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU page 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));
621 Status = UpdatePageEntries (BaseAddress, Length, Attributes, VirtualMask);
622 }
623
624 // flush d-cache so descriptors make it back to uncached memory for subsequent table walks
625 // flush and invalidate pages
626 ArmCleanInvalidateDataCache ();
627
628 ArmInvalidateInstructionCache ();
629
630 // invalidate all TLB entries so changes are synced
631 ArmInvalidateTlb ();
632
633 return Status;
634 }
635
636
637 /**
638 This function modifies the attributes for the memory region specified by BaseAddress and
639 Length from their current attributes to the attributes specified by Attributes.
640
641 @param This The EFI_CPU_ARCH_PROTOCOL instance.
642 @param BaseAddress The physical address that is the start address of a memory region.
643 @param Length The size in bytes of the memory region.
644 @param Attributes The bit mask of attributes to set for the memory region.
645
646 @retval EFI_SUCCESS The attributes were set for the memory region.
647 @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by
648 BaseAddress and Length cannot be modified.
649 @retval EFI_INVALID_PARAMETER Length is zero.
650 @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of
651 the memory resource range.
652 @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory
653 resource range specified by BaseAddress and Length.
654 The bit mask of attributes is not support for the memory resource
655 range specified by BaseAddress and Length.
656
657 **/
658 EFI_STATUS
659 EFIAPI
660 CpuSetMemoryAttributes (
661 IN EFI_CPU_ARCH_PROTOCOL *This,
662 IN EFI_PHYSICAL_ADDRESS BaseAddress,
663 IN UINT64 Length,
664 IN UINT64 Attributes
665 )
666 {
667 if ( ((BaseAddress & (EFI_PAGE_SIZE-1)) != 0) || ((Length & (EFI_PAGE_SIZE-1)) != 0)){
668 // minimum granularity is EFI_PAGE_SIZE (4KB on ARM)
669 return EFI_UNSUPPORTED;
670 }
671
672 return SetMemoryAttributes (BaseAddress, Length, Attributes, 0);
673 }
674
675
676
677 //
678 // Add a new protocol to support
679 //
680
681 EFI_STATUS
682 EFIAPI
683 CpuConvertPagesToUncachedVirtualAddress (
684 IN VIRTUAL_UNCACHED_PAGES_PROTOCOL *This,
685 IN EFI_PHYSICAL_ADDRESS Address,
686 IN UINTN Length,
687 IN EFI_PHYSICAL_ADDRESS VirtualMask,
688 OUT UINT64 *Attributes OPTIONAL
689 )
690 {
691 EFI_STATUS Status;
692 EFI_GCD_MEMORY_SPACE_DESCRIPTOR GcdDescriptor;
693
694
695 if (Attributes != NULL) {
696 Status = gDS->GetMemorySpaceDescriptor (Address, &GcdDescriptor);
697 if (!EFI_ERROR (Status)) {
698 *Attributes = GcdDescriptor.Attributes;
699 }
700 }
701
702 //
703 // Make this address range page fault if accessed. If it is a DMA buffer than this would
704 // be the PCI address. Code should always use the CPU address, and we will or in VirtualMask
705 // to that address.
706 //
707 Status = SetMemoryAttributes (Address, Length, EFI_MEMORY_XP, 0);
708 if (!EFI_ERROR (Status)) {
709 Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_UC, VirtualMask);
710 }
711
712 return Status;
713 }
714
715
716 EFI_STATUS
717 EFIAPI
718 CpuFreeConvertedPages (
719 IN VIRTUAL_UNCACHED_PAGES_PROTOCOL *This,
720 IN EFI_PHYSICAL_ADDRESS Address,
721 IN UINTN Length,
722 IN EFI_PHYSICAL_ADDRESS VirtualMask,
723 IN UINT64 Attributes
724 )
725 {
726 EFI_STATUS Status;
727
728 //
729 // Unmap the alaised Address
730 //
731 Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_XP, 0);
732 if (!EFI_ERROR (Status)) {
733 //
734 // Restore atttributes
735 //
736 Status = SetMemoryAttributes (Address, Length, Attributes, 0);
737 }
738
739 return Status;
740 }
741
742
743 VIRTUAL_UNCACHED_PAGES_PROTOCOL gVirtualUncachedPages = {
744 CpuConvertPagesToUncachedVirtualAddress,
745 CpuFreeConvertedPages
746 };
747
748
749
750