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ARM Packages: Fixed coding style and typos
[mirror_edk2.git] / ArmPkg / Drivers / CpuDxe / Mmu.c
1 /*++
2
3 Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>
4 Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>
5
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14
15 --*/
16
17 #include "CpuDxe.h"
18
19 // First Level Descriptors
20 typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR;
21
22 // Second Level Descriptors
23 typedef UINT32 ARM_PAGE_TABLE_ENTRY;
24
25 EFI_STATUS
26 SectionToGcdAttributes (
27 IN UINT32 SectionAttributes,
28 OUT UINT64 *GcdAttributes
29 )
30 {
31 *GcdAttributes = 0;
32
33 // determine cacheability attributes
34 switch(SectionAttributes & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) {
35 case TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED:
36 *GcdAttributes |= EFI_MEMORY_UC;
37 break;
38 case TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE:
39 *GcdAttributes |= EFI_MEMORY_UC;
40 break;
41 case TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC:
42 *GcdAttributes |= EFI_MEMORY_WT;
43 break;
44 case TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_NO_ALLOC:
45 *GcdAttributes |= EFI_MEMORY_WB;
46 break;
47 case TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE:
48 *GcdAttributes |= EFI_MEMORY_WC;
49 break;
50 case TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC:
51 *GcdAttributes |= EFI_MEMORY_WB;
52 break;
53 case TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_SHAREABLE_DEVICE:
54 *GcdAttributes |= EFI_MEMORY_UC;
55 break;
56 default:
57 return EFI_UNSUPPORTED;
58 }
59
60 // determine protection attributes
61 switch(SectionAttributes & TT_DESCRIPTOR_SECTION_AP_MASK) {
62 case TT_DESCRIPTOR_SECTION_AP_NO_NO: // no read, no write
63 //*GcdAttributes |= EFI_MEMORY_WP | EFI_MEMORY_RP;
64 break;
65
66 case TT_DESCRIPTOR_SECTION_AP_RW_NO:
67 case TT_DESCRIPTOR_SECTION_AP_RW_RW:
68 // normal read/write access, do not add additional attributes
69 break;
70
71 // read only cases map to write-protect
72 case TT_DESCRIPTOR_SECTION_AP_RO_NO:
73 case TT_DESCRIPTOR_SECTION_AP_RO_RO:
74 *GcdAttributes |= EFI_MEMORY_WP;
75 break;
76
77 default:
78 return EFI_UNSUPPORTED;
79 }
80
81 // now process eXectue Never attribute
82 if ((SectionAttributes & TT_DESCRIPTOR_SECTION_XN_MASK) != 0 ) {
83 *GcdAttributes |= EFI_MEMORY_XP;
84 }
85
86 return EFI_SUCCESS;
87 }
88
89 EFI_STATUS
90 PageToGcdAttributes (
91 IN UINT32 PageAttributes,
92 OUT UINT64 *GcdAttributes
93 )
94 {
95 *GcdAttributes = 0;
96
97 // determine cacheability attributes
98 switch(PageAttributes & TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK) {
99 case TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED:
100 *GcdAttributes |= EFI_MEMORY_UC;
101 break;
102 case TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE:
103 *GcdAttributes |= EFI_MEMORY_UC;
104 break;
105 case TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC:
106 *GcdAttributes |= EFI_MEMORY_WT;
107 break;
108 case TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC:
109 *GcdAttributes |= EFI_MEMORY_WB;
110 break;
111 case TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE:
112 *GcdAttributes |= EFI_MEMORY_WC;
113 break;
114 case TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC:
115 *GcdAttributes |= EFI_MEMORY_WB;
116 break;
117 case TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE:
118 *GcdAttributes |= EFI_MEMORY_UC;
119 break;
120 default:
121 return EFI_UNSUPPORTED;
122 }
123
124 // determine protection attributes
125 switch(PageAttributes & TT_DESCRIPTOR_PAGE_AP_MASK) {
126 case TT_DESCRIPTOR_PAGE_AP_NO_NO: // no read, no write
127 //*GcdAttributes |= EFI_MEMORY_WP | EFI_MEMORY_RP;
128 break;
129
130 case TT_DESCRIPTOR_PAGE_AP_RW_NO:
131 case TT_DESCRIPTOR_PAGE_AP_RW_RW:
132 // normal read/write access, do not add additional attributes
133 break;
134
135 // read only cases map to write-protect
136 case TT_DESCRIPTOR_PAGE_AP_RO_NO:
137 case TT_DESCRIPTOR_PAGE_AP_RO_RO:
138 *GcdAttributes |= EFI_MEMORY_WP;
139 break;
140
141 default:
142 return EFI_UNSUPPORTED;
143 }
144
145 // now process eXectue Never attribute
146 if ((PageAttributes & TT_DESCRIPTOR_PAGE_XN_MASK) != 0 ) {
147 *GcdAttributes |= EFI_MEMORY_XP;
148 }
149
150 return EFI_SUCCESS;
151 }
152
153 /**
154 Searches memory descriptors covered by given memory range.
155
156 This function searches into the Gcd Memory Space for descriptors
157 (from StartIndex to EndIndex) that contains the memory range
158 specified by BaseAddress and Length.
159
160 @param MemorySpaceMap Gcd Memory Space Map as array.
161 @param NumberOfDescriptors Number of descriptors in map.
162 @param BaseAddress BaseAddress for the requested range.
163 @param Length Length for the requested range.
164 @param StartIndex Start index into the Gcd Memory Space Map.
165 @param EndIndex End index into the Gcd Memory Space Map.
166
167 @retval EFI_SUCCESS Search successfully.
168 @retval EFI_NOT_FOUND The requested descriptors does not exist.
169
170 **/
171 EFI_STATUS
172 SearchGcdMemorySpaces (
173 IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
174 IN UINTN NumberOfDescriptors,
175 IN EFI_PHYSICAL_ADDRESS BaseAddress,
176 IN UINT64 Length,
177 OUT UINTN *StartIndex,
178 OUT UINTN *EndIndex
179 )
180 {
181 UINTN Index;
182
183 *StartIndex = 0;
184 *EndIndex = 0;
185 for (Index = 0; Index < NumberOfDescriptors; Index++) {
186 if (BaseAddress >= MemorySpaceMap[Index].BaseAddress &&
187 BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
188 *StartIndex = Index;
189 }
190 if (BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress &&
191 BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
192 *EndIndex = Index;
193 return EFI_SUCCESS;
194 }
195 }
196 return EFI_NOT_FOUND;
197 }
198
199
200 /**
201 Sets the attributes for a specified range in Gcd Memory Space Map.
202
203 This function sets the attributes for a specified range in
204 Gcd Memory Space Map.
205
206 @param MemorySpaceMap Gcd Memory Space Map as array
207 @param NumberOfDescriptors Number of descriptors in map
208 @param BaseAddress BaseAddress for the range
209 @param Length Length for the range
210 @param Attributes Attributes to set
211
212 @retval EFI_SUCCESS Memory attributes set successfully
213 @retval EFI_NOT_FOUND The specified range does not exist in Gcd Memory Space
214
215 **/
216 EFI_STATUS
217 SetGcdMemorySpaceAttributes (
218 IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
219 IN UINTN NumberOfDescriptors,
220 IN EFI_PHYSICAL_ADDRESS BaseAddress,
221 IN UINT64 Length,
222 IN UINT64 Attributes
223 )
224 {
225 EFI_STATUS Status;
226 UINTN Index;
227 UINTN StartIndex;
228 UINTN EndIndex;
229 EFI_PHYSICAL_ADDRESS RegionStart;
230 UINT64 RegionLength;
231
232 //
233 // Get all memory descriptors covered by the memory range
234 //
235 Status = SearchGcdMemorySpaces (
236 MemorySpaceMap,
237 NumberOfDescriptors,
238 BaseAddress,
239 Length,
240 &StartIndex,
241 &EndIndex
242 );
243 if (EFI_ERROR (Status)) {
244 return Status;
245 }
246
247 //
248 // Go through all related descriptors and set attributes accordingly
249 //
250 for (Index = StartIndex; Index <= EndIndex; Index++) {
251 if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
252 continue;
253 }
254 //
255 // Calculate the start and end address of the overlapping range
256 //
257 if (BaseAddress >= MemorySpaceMap[Index].BaseAddress) {
258 RegionStart = BaseAddress;
259 } else {
260 RegionStart = MemorySpaceMap[Index].BaseAddress;
261 }
262 if (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
263 RegionLength = BaseAddress + Length - RegionStart;
264 } else {
265 RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;
266 }
267 //
268 // Set memory attributes according to MTRR attribute and the original attribute of descriptor
269 //
270 gDS->SetMemorySpaceAttributes (
271 RegionStart,
272 RegionLength,
273 (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes)
274 );
275 }
276
277 return EFI_SUCCESS;
278 }
279
280 EFI_STATUS
281 SyncCacheConfigPage (
282 IN UINT32 SectionIndex,
283 IN UINT32 FirstLevelDescriptor,
284 IN UINTN NumberOfDescriptors,
285 IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
286 IN OUT EFI_PHYSICAL_ADDRESS *NextRegionBase,
287 IN OUT UINT64 *NextRegionLength,
288 IN OUT UINT32 *NextSectionAttributes
289 )
290 {
291 EFI_STATUS Status;
292 UINT32 i;
293 volatile ARM_PAGE_TABLE_ENTRY *SecondLevelTable;
294 UINT32 NextPageAttributes = 0;
295 UINT32 PageAttributes = 0;
296 UINT32 BaseAddress;
297 UINT64 GcdAttributes;
298
299 // Get the Base Address from FirstLevelDescriptor;
300 BaseAddress = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(SectionIndex << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
301
302 // Convert SectionAttributes into PageAttributes
303 NextPageAttributes =
304 TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(*NextSectionAttributes,0) |
305 TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(*NextSectionAttributes);
306
307 // obtain page table base
308 SecondLevelTable = (ARM_PAGE_TABLE_ENTRY *)(FirstLevelDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK);
309
310 for (i=0; i < TRANSLATION_TABLE_PAGE_COUNT; i++) {
311 if ((SecondLevelTable[i] & TT_DESCRIPTOR_PAGE_TYPE_MASK) == TT_DESCRIPTOR_PAGE_TYPE_PAGE) {
312 // extract attributes (cacheability and permissions)
313 PageAttributes = SecondLevelTable[i] & (TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK | TT_DESCRIPTOR_PAGE_AP_MASK);
314
315 if (NextPageAttributes == 0) {
316 // start on a new region
317 *NextRegionLength = 0;
318 *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);
319 NextPageAttributes = PageAttributes;
320 } else if (PageAttributes != NextPageAttributes) {
321 // Convert Section Attributes into GCD Attributes
322 Status = PageToGcdAttributes (NextPageAttributes, &GcdAttributes);
323 ASSERT_EFI_ERROR (Status);
324
325 // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)
326 SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, *NextRegionBase, *NextRegionLength, GcdAttributes);
327
328 // start on a new region
329 *NextRegionLength = 0;
330 *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);
331 NextPageAttributes = PageAttributes;
332 }
333 } else if (NextPageAttributes != 0) {
334 // Convert Page Attributes into GCD Attributes
335 Status = PageToGcdAttributes (NextPageAttributes, &GcdAttributes);
336 ASSERT_EFI_ERROR (Status);
337
338 // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)
339 SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, *NextRegionBase, *NextRegionLength, GcdAttributes);
340
341 *NextRegionLength = 0;
342 *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);
343 NextPageAttributes = 0;
344 }
345 *NextRegionLength += TT_DESCRIPTOR_PAGE_SIZE;
346 }
347
348 // Convert back PageAttributes into SectionAttributes
349 *NextSectionAttributes =
350 TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(NextPageAttributes,0) |
351 TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(NextPageAttributes);
352
353 return EFI_SUCCESS;
354 }
355
356 EFI_STATUS
357 SyncCacheConfig (
358 IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol
359 )
360 {
361 EFI_STATUS Status;
362 UINT32 i;
363 EFI_PHYSICAL_ADDRESS NextRegionBase;
364 UINT64 NextRegionLength;
365 UINT32 NextSectionAttributes = 0;
366 UINT32 SectionAttributes = 0;
367 UINT64 GcdAttributes;
368 volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
369 UINTN NumberOfDescriptors;
370 EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
371
372
373 DEBUG ((EFI_D_PAGE, "SyncCacheConfig()\n"));
374
375 // This code assumes MMU is enabled and filed with section translations
376 ASSERT (ArmMmuEnabled ());
377
378 //
379 // Get the memory space map from GCD
380 //
381 MemorySpaceMap = NULL;
382 Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
383 ASSERT_EFI_ERROR (Status);
384
385
386 // The GCD implementation maintains its own copy of the state of memory space attributes. GCD needs
387 // to know what the initial memory space attributes are. The CPU Arch. Protocol does not provide a
388 // GetMemoryAttributes function for GCD to get this so we must resort to calling GCD (as if we were
389 // a client) to update its copy of the attributes. This is bad architecture and should be replaced
390 // with a way for GCD to query the CPU Arch. driver of the existing memory space attributes instead.
391
392 // obtain page table base
393 FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)(ArmGetTTBR0BaseAddress ());
394
395 // Get the first region
396 NextSectionAttributes = FirstLevelTable[0] & (TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK);
397
398 // iterate through each 1MB descriptor
399 NextRegionBase = NextRegionLength = 0;
400 for (i=0; i < TRANSLATION_TABLE_SECTION_COUNT; i++) {
401 if ((FirstLevelTable[i] & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) {
402 // extract attributes (cacheability and permissions)
403 SectionAttributes = FirstLevelTable[i] & (TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK);
404
405 if (NextSectionAttributes == 0) {
406 // start on a new region
407 NextRegionLength = 0;
408 NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
409 NextSectionAttributes = SectionAttributes;
410 } else if (SectionAttributes != NextSectionAttributes) {
411 // Convert Section Attributes into GCD Attributes
412 Status = SectionToGcdAttributes (NextSectionAttributes, &GcdAttributes);
413 ASSERT_EFI_ERROR (Status);
414
415 // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)
416 SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);
417
418 // start on a new region
419 NextRegionLength = 0;
420 NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
421 NextSectionAttributes = SectionAttributes;
422 }
423 NextRegionLength += TT_DESCRIPTOR_SECTION_SIZE;
424 } else if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(FirstLevelTable[i])) {
425 Status = SyncCacheConfigPage (
426 i,FirstLevelTable[i],
427 NumberOfDescriptors, MemorySpaceMap,
428 &NextRegionBase,&NextRegionLength,&NextSectionAttributes);
429 ASSERT_EFI_ERROR (Status);
430 } else {
431 // We do not support yet 16MB sections
432 ASSERT ((FirstLevelTable[i] & TT_DESCRIPTOR_SECTION_TYPE_MASK) != TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION);
433
434 // start on a new region
435 if (NextSectionAttributes != 0) {
436 // Convert Section Attributes into GCD Attributes
437 Status = SectionToGcdAttributes (NextSectionAttributes, &GcdAttributes);
438 ASSERT_EFI_ERROR (Status);
439
440 // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)
441 SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);
442
443 NextRegionLength = 0;
444 NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
445 NextSectionAttributes = 0;
446 }
447 NextRegionLength += TT_DESCRIPTOR_SECTION_SIZE;
448 }
449 } // section entry loop
450
451 if (NextSectionAttributes != 0) {
452 // Convert Section Attributes into GCD Attributes
453 Status = SectionToGcdAttributes (NextSectionAttributes, &GcdAttributes);
454 ASSERT_EFI_ERROR (Status);
455
456 // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)
457 SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);
458 }
459
460 return EFI_SUCCESS;
461 }
462
463
464
465 EFI_STATUS
466 UpdatePageEntries (
467 IN EFI_PHYSICAL_ADDRESS BaseAddress,
468 IN UINT64 Length,
469 IN UINT64 Attributes,
470 IN EFI_PHYSICAL_ADDRESS VirtualMask
471 )
472 {
473 EFI_STATUS Status;
474 UINT32 EntryValue;
475 UINT32 EntryMask;
476 UINT32 FirstLevelIdx;
477 UINT32 Offset;
478 UINT32 NumPageEntries;
479 UINT32 Descriptor;
480 UINT32 p;
481 UINT32 PageTableIndex;
482 UINT32 PageTableEntry;
483 UINT32 CurrentPageTableEntry;
484 VOID *Mva;
485
486 volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
487 volatile ARM_PAGE_TABLE_ENTRY *PageTable;
488
489 Status = EFI_SUCCESS;
490
491 // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)
492 // EntryValue: values at bit positions specified by EntryMask
493 EntryMask = TT_DESCRIPTOR_PAGE_TYPE_MASK;
494 EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE;
495 // Although the PI spec is unclear on this the GCD guarantees that only
496 // one Attribute bit is set at a time, so we can safely use a switch statement
497 switch (Attributes) {
498 case EFI_MEMORY_UC:
499 // modify cacheability attributes
500 EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
501 // map to strongly ordered
502 EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
503 break;
504
505 case EFI_MEMORY_WC:
506 // modify cacheability attributes
507 EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
508 // map to normal non-cachable
509 EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
510 break;
511
512 case EFI_MEMORY_WT:
513 // modify cacheability attributes
514 EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
515 // write through with no-allocate
516 EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0
517 break;
518
519 case EFI_MEMORY_WB:
520 // modify cacheability attributes
521 EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
522 // write back (with allocate)
523 EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1
524 break;
525
526 case EFI_MEMORY_WP:
527 case EFI_MEMORY_XP:
528 case EFI_MEMORY_UCE:
529 // cannot be implemented UEFI definition unclear for ARM
530 // Cause a page fault if these ranges are accessed.
531 EntryValue = TT_DESCRIPTOR_PAGE_TYPE_FAULT;
532 DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting page %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));
533 break;
534
535 default:
536 return EFI_UNSUPPORTED;
537 }
538
539 // Obtain page table base
540 FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();
541
542 // Calculate number of 4KB page table entries to change
543 NumPageEntries = Length / TT_DESCRIPTOR_PAGE_SIZE;
544
545 // Iterate for the number of 4KB pages to change
546 Offset = 0;
547 for(p = 0; p < NumPageEntries; p++) {
548 // Calculate index into first level translation table for page table value
549
550 FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress + Offset) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
551 ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);
552
553 // Read the descriptor from the first level page table
554 Descriptor = FirstLevelTable[FirstLevelIdx];
555
556 // Does this descriptor need to be converted from section entry to 4K pages?
557 if (!TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Descriptor)) {
558 Status = ConvertSectionToPages (FirstLevelIdx << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
559 if (EFI_ERROR(Status)) {
560 // Exit for loop
561 break;
562 }
563
564 // Re-read descriptor
565 Descriptor = FirstLevelTable[FirstLevelIdx];
566 }
567
568 // Obtain page table base address
569 PageTable = (ARM_PAGE_TABLE_ENTRY *)TT_DESCRIPTOR_PAGE_BASE_ADDRESS(Descriptor);
570
571 // Calculate index into the page table
572 PageTableIndex = ((BaseAddress + Offset) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;
573 ASSERT (PageTableIndex < TRANSLATION_TABLE_PAGE_COUNT);
574
575 // Get the entry
576 CurrentPageTableEntry = PageTable[PageTableIndex];
577
578 // Mask off appropriate fields
579 PageTableEntry = CurrentPageTableEntry & ~EntryMask;
580
581 // Mask in new attributes and/or permissions
582 PageTableEntry |= EntryValue;
583
584 if (VirtualMask != 0) {
585 // Make this virtual address point at a physical page
586 PageTableEntry &= ~VirtualMask;
587 }
588
589 if (CurrentPageTableEntry != PageTableEntry) {
590 Mva = (VOID *)(UINTN)((((UINTN)FirstLevelIdx) << TT_DESCRIPTOR_SECTION_BASE_SHIFT) + (PageTableIndex << TT_DESCRIPTOR_PAGE_BASE_SHIFT));
591 if ((CurrentPageTableEntry & TT_DESCRIPTOR_PAGE_CACHEABLE_MASK) == TT_DESCRIPTOR_PAGE_CACHEABLE_MASK) {
592 // The current section mapping is cacheable so Clean/Invalidate the MVA of the page
593 // Note assumes switch(Attributes), not ARMv7 possibilities
594 WriteBackInvalidateDataCacheRange (Mva, TT_DESCRIPTOR_PAGE_SIZE);
595 }
596
597 // Only need to update if we are changing the entry
598 PageTable[PageTableIndex] = PageTableEntry;
599 ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], Mva);
600 }
601
602 Status = EFI_SUCCESS;
603 Offset += TT_DESCRIPTOR_PAGE_SIZE;
604
605 } // End first level translation table loop
606
607 return Status;
608 }
609
610
611
612 EFI_STATUS
613 UpdateSectionEntries (
614 IN EFI_PHYSICAL_ADDRESS BaseAddress,
615 IN UINT64 Length,
616 IN UINT64 Attributes,
617 IN EFI_PHYSICAL_ADDRESS VirtualMask
618 )
619 {
620 EFI_STATUS Status = EFI_SUCCESS;
621 UINT32 EntryMask;
622 UINT32 EntryValue;
623 UINT32 FirstLevelIdx;
624 UINT32 NumSections;
625 UINT32 i;
626 UINT32 CurrentDescriptor;
627 UINT32 Descriptor;
628 VOID *Mva;
629 volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
630
631 // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)
632 // EntryValue: values at bit positions specified by EntryMask
633
634 // Make sure we handle a section range that is unmapped
635 EntryMask = TT_DESCRIPTOR_SECTION_TYPE_MASK;
636 EntryValue = TT_DESCRIPTOR_SECTION_TYPE_SECTION;
637
638 // Although the PI spec is unclear on this the GCD guarantees that only
639 // one Attribute bit is set at a time, so we can safely use a switch statement
640 switch(Attributes) {
641 case EFI_MEMORY_UC:
642 // modify cacheability attributes
643 EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
644 // map to strongly ordered
645 EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
646 break;
647
648 case EFI_MEMORY_WC:
649 // modify cacheability attributes
650 EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
651 // map to normal non-cachable
652 EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
653 break;
654
655 case EFI_MEMORY_WT:
656 // modify cacheability attributes
657 EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
658 // write through with no-allocate
659 EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0
660 break;
661
662 case EFI_MEMORY_WB:
663 // modify cacheability attributes
664 EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
665 // write back (with allocate)
666 EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1
667 break;
668
669 case EFI_MEMORY_WP:
670 case EFI_MEMORY_XP:
671 case EFI_MEMORY_RP:
672 case EFI_MEMORY_UCE:
673 // cannot be implemented UEFI definition unclear for ARM
674 // Cause a page fault if these ranges are accessed.
675 EntryValue = TT_DESCRIPTOR_SECTION_TYPE_FAULT;
676 DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting section %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));
677 break;
678
679
680 default:
681 return EFI_UNSUPPORTED;
682 }
683
684 // obtain page table base
685 FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();
686
687 // calculate index into first level translation table for start of modification
688 FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
689 ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);
690
691 // calculate number of 1MB first level entries this applies to
692 NumSections = Length / TT_DESCRIPTOR_SECTION_SIZE;
693
694 // iterate through each descriptor
695 for(i=0; i<NumSections; i++) {
696 CurrentDescriptor = FirstLevelTable[FirstLevelIdx + i];
697
698 // has this descriptor already been coverted to pages?
699 if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(CurrentDescriptor)) {
700 // forward this 1MB range to page table function instead
701 Status = UpdatePageEntries ((FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT, TT_DESCRIPTOR_SECTION_SIZE, Attributes, VirtualMask);
702 } else {
703 // still a section entry
704
705 // mask off appropriate fields
706 Descriptor = CurrentDescriptor & ~EntryMask;
707
708 // mask in new attributes and/or permissions
709 Descriptor |= EntryValue;
710 if (VirtualMask != 0) {
711 Descriptor &= ~VirtualMask;
712 }
713
714 if (CurrentDescriptor != Descriptor) {
715 Mva = (VOID *)(UINTN)(((UINTN)FirstLevelTable) << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
716 if ((CurrentDescriptor & TT_DESCRIPTOR_SECTION_CACHEABLE_MASK) == TT_DESCRIPTOR_SECTION_CACHEABLE_MASK) {
717 // The current section mapping is cacheable so Clean/Invalidate the MVA of the section
718 // Note assumes switch(Attributes), not ARMv7 possabilities
719 WriteBackInvalidateDataCacheRange (Mva, SIZE_1MB);
720 }
721
722 // Only need to update if we are changing the descriptor
723 FirstLevelTable[FirstLevelIdx + i] = Descriptor;
724 ArmUpdateTranslationTableEntry ((VOID *)&FirstLevelTable[FirstLevelIdx + i], Mva);
725 }
726
727 Status = EFI_SUCCESS;
728 }
729 }
730
731 return Status;
732 }
733
734 EFI_STATUS
735 ConvertSectionToPages (
736 IN EFI_PHYSICAL_ADDRESS BaseAddress
737 )
738 {
739 EFI_STATUS Status;
740 EFI_PHYSICAL_ADDRESS PageTableAddr;
741 UINT32 FirstLevelIdx;
742 UINT32 SectionDescriptor;
743 UINT32 PageTableDescriptor;
744 UINT32 PageDescriptor;
745 UINT32 Index;
746
747 volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
748 volatile ARM_PAGE_TABLE_ENTRY *PageTable;
749
750 DEBUG ((EFI_D_PAGE, "Converting section at 0x%x to pages\n", (UINTN)BaseAddress));
751
752 // Obtain page table base
753 FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();
754
755 // Calculate index into first level translation table for start of modification
756 FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
757 ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);
758
759 // Get section attributes and convert to page attributes
760 SectionDescriptor = FirstLevelTable[FirstLevelIdx];
761 PageDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE;
762 PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(SectionDescriptor,0);
763 PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(SectionDescriptor);
764 PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_XN(SectionDescriptor,0);
765 PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(SectionDescriptor);
766 PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_S(SectionDescriptor);
767
768 // Allocate a page table for the 4KB entries (we use up a full page even though we only need 1KB)
769 Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData, 1, &PageTableAddr);
770 if (EFI_ERROR(Status)) {
771 return Status;
772 }
773
774 PageTable = (volatile ARM_PAGE_TABLE_ENTRY *)(UINTN)PageTableAddr;
775
776 // Write the page table entries out
777 for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) {
778 PageTable[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseAddress + (Index << 12)) | PageDescriptor;
779 }
780
781 // Flush d-cache so descriptors make it back to uncached memory for subsequent table walks
782 WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)PageTableAddr, TT_DESCRIPTOR_PAGE_SIZE);
783
784 // Formulate page table entry, Domain=0, NS=0
785 PageTableDescriptor = (((UINTN)PageTableAddr) & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;
786
787 // Write the page table entry out, replacing section entry
788 FirstLevelTable[FirstLevelIdx] = PageTableDescriptor;
789
790 return EFI_SUCCESS;
791 }
792
793
794
795 EFI_STATUS
796 SetMemoryAttributes (
797 IN EFI_PHYSICAL_ADDRESS BaseAddress,
798 IN UINT64 Length,
799 IN UINT64 Attributes,
800 IN EFI_PHYSICAL_ADDRESS VirtualMask
801 )
802 {
803 EFI_STATUS Status;
804
805 if(((BaseAddress & 0xFFFFF) == 0) && ((Length & 0xFFFFF) == 0)) {
806 // Is the base and length a multiple of 1 MB?
807 DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));
808 Status = UpdateSectionEntries (BaseAddress, Length, Attributes, VirtualMask);
809 } else {
810 // Base and/or length is not a multiple of 1 MB
811 DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU page 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));
812 Status = UpdatePageEntries (BaseAddress, Length, Attributes, VirtualMask);
813 }
814
815 // Flush d-cache so descriptors make it back to uncached memory for subsequent table walks
816 // flush and invalidate pages
817 //TODO: Do we really need to invalidate the caches everytime we change the memory attributes ?
818 ArmCleanInvalidateDataCache ();
819
820 ArmInvalidateInstructionCache ();
821
822 // Invalidate all TLB entries so changes are synced
823 ArmInvalidateTlb ();
824
825 return Status;
826 }
827
828
829 /**
830 This function modifies the attributes for the memory region specified by BaseAddress and
831 Length from their current attributes to the attributes specified by Attributes.
832
833 @param This The EFI_CPU_ARCH_PROTOCOL instance.
834 @param BaseAddress The physical address that is the start address of a memory region.
835 @param Length The size in bytes of the memory region.
836 @param Attributes The bit mask of attributes to set for the memory region.
837
838 @retval EFI_SUCCESS The attributes were set for the memory region.
839 @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by
840 BaseAddress and Length cannot be modified.
841 @retval EFI_INVALID_PARAMETER Length is zero.
842 @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of
843 the memory resource range.
844 @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory
845 resource range specified by BaseAddress and Length.
846 The bit mask of attributes is not support for the memory resource
847 range specified by BaseAddress and Length.
848
849 **/
850 EFI_STATUS
851 EFIAPI
852 CpuSetMemoryAttributes (
853 IN EFI_CPU_ARCH_PROTOCOL *This,
854 IN EFI_PHYSICAL_ADDRESS BaseAddress,
855 IN UINT64 Length,
856 IN UINT64 Attributes
857 )
858 {
859 DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx)\n", BaseAddress, Length, Attributes));
860 if ( ((BaseAddress & ~TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK) != 0) || ((Length & ~TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK) != 0)){
861 // minimum granularity is SIZE_4KB (4KB on ARM)
862 DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx): minimum ganularity is SIZE_4KB\n", BaseAddress, Length, Attributes));
863 return EFI_UNSUPPORTED;
864 }
865
866 return SetMemoryAttributes (BaseAddress, Length, Attributes, 0);
867 }
868
869
870
871 //
872 // Add a new protocol to support
873 //
874
875 EFI_STATUS
876 EFIAPI
877 CpuConvertPagesToUncachedVirtualAddress (
878 IN VIRTUAL_UNCACHED_PAGES_PROTOCOL *This,
879 IN EFI_PHYSICAL_ADDRESS Address,
880 IN UINTN Length,
881 IN EFI_PHYSICAL_ADDRESS VirtualMask,
882 OUT UINT64 *Attributes OPTIONAL
883 )
884 {
885 EFI_STATUS Status;
886 EFI_GCD_MEMORY_SPACE_DESCRIPTOR GcdDescriptor;
887
888
889 if (Attributes != NULL) {
890 Status = gDS->GetMemorySpaceDescriptor (Address, &GcdDescriptor);
891 if (!EFI_ERROR (Status)) {
892 *Attributes = GcdDescriptor.Attributes;
893 }
894 }
895
896 //
897 // Make this address range page fault if accessed. If it is a DMA buffer than this would
898 // be the PCI address. Code should always use the CPU address, and we will or in VirtualMask
899 // to that address.
900 //
901 Status = SetMemoryAttributes (Address, Length, EFI_MEMORY_WP, 0);
902 if (!EFI_ERROR (Status)) {
903 Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_UC, VirtualMask);
904 }
905
906 DEBUG ((DEBUG_INFO | DEBUG_LOAD, "ConvertPagesToUncachedVirtualAddress()\n Unmapped 0x%08lx Mapped 0x%08lx 0x%x bytes\n", Address, Address | VirtualMask, Length));
907
908 return Status;
909 }
910
911
912 EFI_STATUS
913 EFIAPI
914 CpuReconvertPages (
915 IN VIRTUAL_UNCACHED_PAGES_PROTOCOL *This,
916 IN EFI_PHYSICAL_ADDRESS Address,
917 IN UINTN Length,
918 IN EFI_PHYSICAL_ADDRESS VirtualMask,
919 IN UINT64 Attributes
920 )
921 {
922 EFI_STATUS Status;
923
924 DEBUG ((DEBUG_INFO | DEBUG_LOAD, "CpuReconvertPages(%lx, %x, %lx, %lx)\n", Address, Length, VirtualMask, Attributes));
925
926 //
927 // Unmap the alaised Address
928 //
929 Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_WP, 0);
930 if (!EFI_ERROR (Status)) {
931 //
932 // Restore atttributes
933 //
934 Status = SetMemoryAttributes (Address, Length, Attributes, 0);
935 }
936
937 return Status;
938 }
939
940
941 VIRTUAL_UNCACHED_PAGES_PROTOCOL gVirtualUncachedPages = {
942 CpuConvertPagesToUncachedVirtualAddress,
943 CpuReconvertPages
944 };
EFI Development Kit II mirror for PVE