ArmPkg/Drivers/CpuPei/CpuPei.c

   1 /**@file
   2
   3 Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
   4 This program and the accompanying materials
   5 are licensed and made available under the terms and conditions of the BSD License
   6 which accompanies this distribution.  The full text of the license may be found at
   7 http://opensource.org/licenses/bsd-license.php
   8
   9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11
  12 Module Name:
  13
  14   MemoryInit.c
  15
  16 Abstract:
  17
  18   PEIM to provide fake memory init
  19
  20 **/
  21
  22
  23
  24 //
  25 // The package level header files this module uses
  26 //
  27 #include <PiPei.h>
  28 //
  29 // The protocols, PPI and GUID defintions for this module
  30 //
  31
  32 //
  33 // The Library classes this module consumes
  34 //
  35 #include <Library/DebugLib.h>
  36 #include <Library/PeimEntryPoint.h>
  37 #include <Library/PcdLib.h>
  38 #include <Library/HobLib.h>
  39 #include <Library/ArmLib.h>
  40
  41 //
  42 // Module globals
  43 //
  44
  45 #define DDR_ATTRIBUTES_CACHED                ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
  46 #define DDR_ATTRIBUTES_UNCACHED              ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
  47
  48 VOID
  49 JamArmMmuConfig ( VOID )
  50 {
  51   UINT32                        CacheAttributes;
  52   ARM_MEMORY_REGION_DESCRIPTOR  MemoryTable[3];
  53   VOID                          *TranslationTableBase;
  54   UINTN                         TranslationTableSize;
  55
  56   if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
  57     CacheAttributes = DDR_ATTRIBUTES_CACHED;
  58   } else {
  59     CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
  60   }
  61
  62   // DDR
  63   MemoryTable[0].PhysicalBase = 0;
  64   MemoryTable[0].VirtualBase  = 0;
  65   MemoryTable[0].Length       = 0x10000000;
  66   MemoryTable[0].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;
  67
  68   // SOC Registers. L3 interconnects
  69   MemoryTable[1].PhysicalBase = 0x10000000;
  70   MemoryTable[1].VirtualBase  = 0x10000000;
  71   MemoryTable[1].Length       = 0xF0000000;
  72   MemoryTable[1].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
  73
  74   // End of Table
  75   MemoryTable[2].PhysicalBase = 0;
  76   MemoryTable[2].VirtualBase  = 0;
  77   MemoryTable[2].Length       = 0;
  78   MemoryTable[2].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;
  79
  80   ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);
  81
  82   BuildMemoryAllocationHob((EFI_PHYSICAL_ADDRESS)(UINTN)TranslationTableBase, TranslationTableSize, EfiBootServicesData);
  83 }
  84
  85
  86 EFI_STATUS
  87 EFIAPI
  88 InitializeCpuPeim (
  89   IN       EFI_PEI_FILE_HANDLE  FileHandle,
  90   IN CONST EFI_PEI_SERVICES     **PeiServices
  91   )
  92 /*++
  93
  94 Routine Description:
  95
  96
  97
  98 Arguments:
  99
 100   FileHandle  - Handle of the file being invoked.
 101   PeiServices - Describes the list of possible PEI Services.
 102
 103 Returns:
 104
 105   Status -  EFI_SUCCESS if the boot mode could be set
 106
 107 --*/
 108 {
 109   // Enable program flow prediction, if supported.
 110   ArmEnableBranchPrediction ();
 111
 112   JamArmMmuConfig();
 113
 114   return EFI_SUCCESS;
 115 }