ArmPkg/Drivers/PL180MciDxe/PL180Mci.h

   1 /** @file
   2   Header for the MMC Host Protocol implementation for the ARM PrimeCell PL180.
   3
   4   Copyright (c) 2011, ARM Limited. All rights reserved.
   5
   6   This program and the accompanying materials
   7   are licensed and made available under the terms and conditions of the BSD License
   8   which accompanies this distribution.  The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef __PL180_MCI_H
  17 #define __PL180_MCI_H
  18
  19 #include <Uefi.h>
  20
  21 #include <Protocol/MmcHost.h>
  22
  23 #include <Library/UefiLib.h>
  24 #include <Library/DebugLib.h>
  25 #include <Library/UefiBootServicesTableLib.h>
  26 #include <Library/IoLib.h>
  27 #include <Library/TimerLib.h>
  28 #include <Library/PcdLib.h>
  29
  30 #define PL180_MCI_DXE_VERSION   0x10
  31
  32 #define MCI_SYSCTL  FixedPcdGet32(PcdPL180MciBaseAddress)
  33
  34 #define MCI_POWER_CONTROL_REG           (MCI_SYSCTL+0x000)
  35 #define MCI_CLOCK_CONTROL_REG           (MCI_SYSCTL+0x004)
  36 #define MCI_ARGUMENT_REG                (MCI_SYSCTL+0x008)
  37 #define MCI_COMMAND_REG                 (MCI_SYSCTL+0x00C)
  38 #define MCI_RESPCMD_REG                 (MCI_SYSCTL+0x010)
  39 #define MCI_RESPONSE0_REG               (MCI_SYSCTL+0x014)
  40 #define MCI_RESPONSE1_REG               (MCI_SYSCTL+0x018)
  41 #define MCI_RESPONSE2_REG               (MCI_SYSCTL+0x01C)
  42 #define MCI_RESPONSE3_REG               (MCI_SYSCTL+0x020)
  43 #define MCI_DATA_TIMER_REG              (MCI_SYSCTL+0x024)
  44 #define MCI_DATA_LENGTH_REG             (MCI_SYSCTL+0x028)
  45 #define MCI_DATA_CTL_REG                (MCI_SYSCTL+0x02C)
  46 #define MCI_DATA_COUNTER                (MCI_SYSCTL+0x030)
  47 #define MCI_STATUS_REG                  (MCI_SYSCTL+0x034)
  48 #define MCI_CLEAR_STATUS_REG            (MCI_SYSCTL+0x038)
  49 #define MCI_INT0_MASK_REG               (MCI_SYSCTL+0x03C)
  50 #define MCI_INT1_MASK_REG               (MCI_SYSCTL+0x040)
  51 #define MCI_FIFOCOUNT_REG               (MCI_SYSCTL+0x048)
  52 #define MCI_FIFO_REG                    (MCI_SYSCTL+0x080)
  53
  54 #define MCI_POWER_UP                    0x2
  55 #define MCI_POWER_ON                    0x3
  56 #define MCI_POWER_OPENDRAIN             (1 << 6)
  57 #define MCI_POWER_ROD                   (1 << 7)
  58
  59 #define MCI_CLOCK_ENABLE                0x100
  60 #define MCI_CLOCK_POWERSAVE             0x200
  61 #define MCI_CLOCK_BYPASS                0x400
  62
  63 #define MCI_STATUS_CMD_CMDCRCFAIL       0x1
  64 #define MCI_STATUS_CMD_DATACRCFAIL      0x2
  65 #define MCI_STATUS_CMD_CMDTIMEOUT       0x4
  66 #define MCI_STATUS_CMD_DATATIMEOUT      0x8
  67 #define MCI_STATUS_CMD_RXOVERRUN        0x20
  68 #define MCI_STATUS_CMD_RESPEND          0x40
  69 #define MCI_STATUS_CMD_SENT             0x80
  70 #define MCI_STATUS_CMD_TXDONE           (MCI_STATUS_CMD_DATAEND | MCI_STATUS_CMD_DATABLOCKEND)
  71 #define MCI_STATUS_CMD_DATAEND          0x000100    // Command Status - Data end
  72 #define MCI_STATUS_CMD_DATABLOCKEND     0x000400    // Command Status - Data end
  73 #define MCI_STATUS_CMD_ACTIVE           0x800
  74 #define MCI_STATUS_CMD_RXACTIVE         (1 << 13)
  75 #define MCI_STATUS_CMD_RXFIFOHALFFULL   0x008000
  76 #define MCI_STATUS_CMD_RXFIFOEMPTY      0x080000
  77 #define MCI_STATUS_CMD_RXDATAAVAILBL    (1 << 21)
  78 #define MCI_STATUS_CMD_TXACTIVE         (1 << 12)
  79 #define MCI_STATUS_CMD_TXFIFOFULL       (1 << 16)
  80 #define MCI_STATUS_CMD_TXFIFOHALFEMPTY  (1 << 14)
  81 #define MCI_STATUS_CMD_TXFIFOEMPTY      (1 << 18)
  82 #define MCI_STATUS_CMD_TXDATAAVAILBL    (1 << 20)
  83
  84 #define MCI_DATACTL_ENABLE              1
  85 #define MCI_DATACTL_CONT_TO_CARD        0
  86 #define MCI_DATACTL_CARD_TO_CONT        2
  87 #define MCI_DATACTL_BLOCK_TRANS         0
  88 #define MCI_DATACTL_STREAM_TRANS        4
  89 #define MCI_DATACTL_DMA_ENABLE          8
  90
  91 #define INDX(CMD_INDX)    ((CMD_INDX & 0x3F) | MCI_CPSM_ENABLED)
  92
  93 #define MCI_CPSM_ENABLED            (1 << 10)
  94 #define MCI_CPSM_WAIT_RESPONSE      (1 << 6)
  95 #define MCI_CPSM_LONG_RESPONSE      (1 << 7)
  96
  97 #define MCI_TRACE(txt)  DEBUG((EFI_D_BLKIO, "ARM_MCI: " txt "\n"))
  98
  99 EFI_STATUS
 100 EFIAPI
 101 MciGetDriverName (
 102   IN  EFI_COMPONENT_NAME_PROTOCOL  *This,
 103   IN  CHAR8                        *Language,
 104   OUT CHAR16                       **DriverName
 105   );
 106
 107 EFI_STATUS
 108 EFIAPI
 109 MciGetControllerName (
 110   IN  EFI_COMPONENT_NAME_PROTOCOL                     *This,
 111   IN  EFI_HANDLE                                      ControllerHandle,
 112   IN  EFI_HANDLE                                      ChildHandle        OPTIONAL,
 113   IN  CHAR8                                           *Language,
 114   OUT CHAR16                                          **ControllerName
 115   );
 116
 117 #endif