ArmPkg/Drivers/PL34xDmc/PL341Dmc.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2011, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #include <Library/IoLib.h>
  16 #include <Library/DebugLib.h>
  17 #include <Drivers/PL341Dmc.h>
  18
  19 // Macros for writing to DDR2 controller.
  20 #define DmcWriteReg(reg,val)                    MmioWrite32(DmcBase + reg, val)
  21 #define DmcReadReg(reg)                         MmioRead32(DmcBase + reg)
  22
  23 // Macros for writing/reading to DDR2 PHY controller
  24 #define DmcPhyWriteReg(reg,val)                    MmioWrite32(DmcPhyBase + reg, val)
  25 #define DmcPhyReadReg(reg)                         MmioRead32(DmcPhyBase + reg)
  26
  27 // Initialise PL341 Dynamic Memory Controller
  28 VOID
  29 PL341DmcInit (
  30   IN  PL341_DMC_CONFIG *DmcConfig
  31   )
  32 {
  33   UINTN DmcBase;
  34   UINTN Index;
  35   UINT32 Chip;
  36
  37   DmcBase = DmcConfig->base;
  38
  39   // Set config mode
  40   DmcWriteReg(DMC_COMMAND_REG, DMC_COMMAND_CONFIGURE);
  41
  42   //
  43   // Setup the QoS AXI ID bits
  44   //
  45   if (DmcConfig->HasQos) {
  46     // CLCD AXIID = 000
  47     DmcWriteReg(DMC_ID_0_CFG_REG, DMC_ID_CFG_QOS_ENABLE | DMC_ID_CFG_QOS_MIN);
  48
  49     // Default disable QoS
  50     DmcWriteReg(DMC_ID_1_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
  51     DmcWriteReg(DMC_ID_2_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
  52     DmcWriteReg(DMC_ID_3_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
  53     DmcWriteReg(DMC_ID_4_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
  54     DmcWriteReg(DMC_ID_5_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
  55     DmcWriteReg(DMC_ID_6_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
  56     DmcWriteReg(DMC_ID_7_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
  57     DmcWriteReg(DMC_ID_8_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
  58     DmcWriteReg(DMC_ID_9_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
  59     DmcWriteReg(DMC_ID_10_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
  60     DmcWriteReg(DMC_ID_11_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
  61     DmcWriteReg(DMC_ID_12_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
  62     DmcWriteReg(DMC_ID_13_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
  63     DmcWriteReg(DMC_ID_14_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
  64     DmcWriteReg(DMC_ID_15_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
  65   }
  66
  67   //
  68   // Initialise memory controlller
  69   //
  70   DmcWriteReg(DMC_REFRESH_PRD_REG, DmcConfig->refresh_prd);
  71   DmcWriteReg(DMC_CAS_LATENCY_REG, DmcConfig->cas_latency);
  72   DmcWriteReg(DMC_WRITE_LATENCY_REG, DmcConfig->write_latency);
  73   DmcWriteReg(DMC_T_MRD_REG, DmcConfig->t_mrd);
  74   DmcWriteReg(DMC_T_RAS_REG, DmcConfig->t_ras);
  75   DmcWriteReg(DMC_T_RC_REG, DmcConfig->t_rc);
  76   DmcWriteReg(DMC_T_RCD_REG, DmcConfig->t_rcd);
  77   DmcWriteReg(DMC_T_RFC_REG, DmcConfig->t_rfc);
  78   DmcWriteReg(DMC_T_RP_REG, DmcConfig->t_rp);
  79   DmcWriteReg(DMC_T_RRD_REG, DmcConfig->t_rrd);
  80   DmcWriteReg(DMC_T_WR_REG, DmcConfig->t_wr);
  81   DmcWriteReg(DMC_T_WTR_REG, DmcConfig->t_wtr);
  82   DmcWriteReg(DMC_T_XP_REG, DmcConfig->t_xp);
  83   DmcWriteReg(DMC_T_XSR_REG, DmcConfig->t_xsr);
  84   DmcWriteReg(DMC_T_ESR_REG, DmcConfig->t_esr);
  85   DmcWriteReg(DMC_T_FAW_REG, DmcConfig->t_faw);
  86   DmcWriteReg(DMC_T_WRLAT_DIFF, DmcConfig->t_wdata_en);
  87   DmcWriteReg(DMC_T_RDATA_EN, DmcConfig->t_data_en);
  88
  89   //
  90   // Initialise PL341 Mem Config Registers
  91   //
  92
  93   // Set PL341 Memory Config
  94   DmcWriteReg(DMC_MEMORY_CONFIG_REG, DmcConfig->MemoryCfg);
  95
  96   // Set PL341 Memory Config 2
  97   DmcWriteReg(DMC_MEMORY_CFG2_REG, DmcConfig->MemoryCfg2);
  98
  99   // Set PL341 Chip Select <n>
 100   DmcWriteReg(DMC_CHIP_0_CFG_REG, DmcConfig->ChipCfg0);
 101   DmcWriteReg(DMC_CHIP_1_CFG_REG, DmcConfig->ChipCfg1);
 102   DmcWriteReg(DMC_CHIP_2_CFG_REG, DmcConfig->ChipCfg2);
 103   DmcWriteReg(DMC_CHIP_3_CFG_REG, DmcConfig->ChipCfg3);
 104
 105   // Delay
 106   for (Index = 0; Index < 10; Index++) {
 107     DmcReadReg(DMC_STATUS_REG);
 108   }
 109
 110   // Set PL341 Memory Config 3
 111   DmcWriteReg(DMC_MEMORY_CFG3_REG, DmcConfig->MemoryCfg3);
 112
 113   if (DmcConfig->IsUserCfg) {
 114     //
 115     // Set Test Chip PHY Registers via PL341 User Config Reg
 116     // Note that user_cfgX registers are Write Only
 117     //
 118     // DLL Freq set = 250MHz - 266MHz
 119     //
 120     DmcWriteReg(DMC_USER_0_CFG_REG, DmcConfig->User0Cfg);
 121
 122     // user_config2
 123     // ------------
 124     // Set defaults before calibrating the DDR2 buffer impendence
 125     // - Disable ODT
 126     // - Default drive strengths
 127     DmcWriteReg(DMC_USER_2_CFG_REG, 0x40000198);
 128
 129     //
 130     // Auto calibrate the DDR2 buffers impendence
 131     //
 132     while (!(DmcReadReg(DMC_USER_STATUS_REG) & 0x100));
 133
 134     // Set the output driven strength
 135     DmcWriteReg(DMC_USER_2_CFG_REG, 0x40800000 | DmcConfig->User2Cfg);
 136
 137     //
 138     // Set PL341 Feature Control Register
 139     //
 140     // Disable early BRESP - use to optimise CLCD performance
 141     DmcWriteReg(DMC_FEATURE_CRTL_REG, 0x00000001);
 142   }
 143
 144   //
 145   // Config memories
 146   //
 147   for (Chip = 0; Chip < DmcConfig->MaxChip; Chip++) {
 148     // Send nop
 149     DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_NOP);
 150
 151     // Pre-charge all
 152     DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL);
 153
 154     // Delay
 155     for (Index = 0; Index < 10; Index++) {
 156       DmcReadReg(DMC_STATUS_REG);
 157     }
 158
 159     // Set (EMR2) extended mode register 2
 160     DmcWriteReg(DMC_DIRECT_CMD_REG,
 161       DMC_DIRECT_CMD_CHIP_ADDR(Chip) |
 162       DMC_DIRECT_CMD_BANKADDR(2) |
 163       DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);
 164
 165     // Set (EMR3) extended mode register 3
 166     DmcWriteReg(DMC_DIRECT_CMD_REG,
 167       DMC_DIRECT_CMD_CHIP_ADDR(Chip) |
 168       DMC_DIRECT_CMD_BANKADDR(3) |
 169       DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);
 170
 171     //
 172     // Set (EMR) Extended Mode Register
 173     //
 174     // Put into OCD default state
 175     DmcWriteReg(DMC_DIRECT_CMD_REG,DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_BANKADDR(1) | DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);
 176
 177     //
 178     // Set (MR) mode register - With DLL reset
 179     //
 180     DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_EXTMODEREG | DmcConfig->ModeReg | DDR2_MR_DLL_RESET);
 181
 182     // Pre-charge all
 183     DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL);
 184     // Auto-refresh
 185     DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH);
 186     // Auto-refresh
 187     DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH);
 188
 189     //
 190     // Set (MR) mode register - Without DLL reset
 191     //
 192     DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_EXTMODEREG | DmcConfig->ModeReg);
 193
 194     // Delay
 195     for (Index = 0; Index < 10; Index++) {
 196       DmcReadReg(DMC_STATUS_REG);
 197     }
 198
 199     //
 200     // Set (EMR) extended mode register - Enable OCD defaults
 201     //
 202     DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | (0x00090000) |
 203         (1 << DDR_MODESET_SHFT) | (DDR_EMR_OCD_DEFAULT << DDR_EMR_OCD_SHIFT) | DmcConfig->ExtModeReg);
 204
 205     // Delay
 206     for (Index = 0; Index < 10; Index++) {
 207       DmcReadReg(DMC_STATUS_REG);
 208     }
 209
 210     // Set (EMR) extended mode register - OCD Exit
 211     DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | (0x00090000) |
 212         (1 << DDR_MODESET_SHFT) | (DDR_EMR_OCD_NS << DDR_EMR_OCD_SHIFT) | DmcConfig->ExtModeReg);
 213   }
 214
 215   // Move DDR2 Controller to Ready state by issueing GO command
 216   DmcWriteReg(DMC_COMMAND_REG, DMC_COMMAND_GO);
 217
 218   // wait for ready
 219   while (!(DmcReadReg(DMC_STATUS_REG) & DMC_STATUS_READY));
 220
 221 }