ArmPkg/Drivers/PL35xSmc/InitializeSMC.S

   1 #
   2 #  Copyright (c) 2011, ARM Limited. All rights reserved.
   3 #
   4 #  This program and the accompanying materials
   5 #  are licensed and made available under the terms and conditions of the BSD License
   6 #  which accompanies this distribution.  The full text of the license may be found at
   7 #  http:#opensource.org/licenses/bsd-license.php
   8 #
   9 #  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 #
  12 #
  13
  14 #include <AsmMacroIoLib.h>
  15 #include <Library/PcdLib.h>
  16 #include <AutoGen.h>
  17 #include <Drivers/PL354Smc.h>
  18
  19 #Start of the code section
  20 .text
  21
  22 #Maintain 8 byte alignment
  23 .align 3
  24
  25
  26 GCC_ASM_EXPORT(SMCInitializeNOR)
  27 GCC_ASM_EXPORT(SMCInitializeSRAM)
  28 GCC_ASM_EXPORT(SMCInitializePeripherals)
  29 GCC_ASM_EXPORT(SMCInitializeVRAM)
  30
  31
  32 # CS0  CS0-Interf0     NOR1 flash on the motherboard
  33 # CS1  CS1-Interf0     Reserved for the motherboard
  34 # CS2  CS2-Interf0     SRAM on the motherboard
  35 # CS3  CS3-Interf0     memory-mapped Ethernet and USB controllers on the motherboard
  36 # CS4  CS0-Interf1     NOR2 flash on the motherboard
  37 # CS5  CS1-Interf1     memory-mapped peripherals
  38 # CS6  CS2-Interf1     memory-mapped peripherals
  39 # CS7  CS3-Interf1     system memory-mapped peripherals on the motherboard.
  40
  41 // IN r1 SmcBase
  42 // IN r2 ChipSelect
  43 // NOTE: This code is been called before any stack has been setup. It means some registers
  44 //       could be overwritten (case of 'r0')
  45 ASM_PFX(SMCInitializeNOR):
  46 #
  47 # Setup NOR1 (CS0-Interface0)
  48 #
  49
  50   # Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)
  51      #Read cycle timeout = 0xA (0:3)
  52      #Write cycle timeout = 0x3(7:4)
  53      #OE Assertion Delay = 0x9(11:8)
  54      #WE Assertion delay = 0x3(15:12)
  55      #Page cycle timeout = 0x2(19:16)
  56   LoadConstantToReg (0x0002393A,r0)       @ldr     r0, = 0x0002393A
  57   str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
  58
  59   # Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)
  60      # 0x00000002 = MemoryWidth: 32bit
  61      # 0x00000028 = ReadMemoryBurstLength:continuous
  62      # 0x00000280 = WriteMemoryBurstLength:continuous
  63      # 0x00000800 = Set Address Valid
  64   LoadConstantToReg (0x00000AAA,r0)       @ldr     r0, = 0x00000AAA
  65   str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
  66
  67  # Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers
  68      # 0x00000000 = ChipSelect0-Interface 0
  69      # 0x00400000 = CmdTypes: UpdateRegs
  70   LoadConstantToReg (0x00400000,r0)       @ldr     r0, = 0x00400000
  71   str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
  72
  73   bx lr
  74
  75 ASM_PFX(SMCInitializeSRAM):
  76 #
  77 # Setup SRAM (CS2-Interface0)
  78 #
  79   LoadConstantToReg (0x00027158,r0)       @ldr     r0, = 0x00027158
  80   str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
  81
  82   # 0x00000002 = MemoryWidth: 32bit
  83   # 0x00000800 = Set Address Valid
  84   LoadConstantToReg (0x00000802,r0)       @ldr     r0, = 0x00000802
  85   str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
  86
  87   # 0x01000000 = ChipSelect2-Interface 0
  88   # 0x00400000 = CmdTypes: UpdateRegs
  89   LoadConstantToReg (0x01400000,r0)       @ldr     r0, = 0x01400000
  90   str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
  91
  92   bx    lr
  93
  94 ASM_PFX(SMCInitializePeripherals):
  95 #
  96 # USB/Eth/VRAM (CS3-Interface0)
  97 #
  98   LoadConstantToReg (0x000CD2AA,r0)      @ldr     r0, = 0x000CD2AA
  99   str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
 100
 101   # 0x00000002 = MemoryWidth: 32bit
 102   # 0x00000004 = Memory reads are synchronous
 103   # 0x00000040 = Memory writes are synchronous
 104   LoadConstantToReg (0x00000046,r0)      @ldr     r0, = 0x00000046
 105   str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
 106
 107   # 0x01800000 = ChipSelect3-Interface 0
 108   # 0x00400000 = CmdTypes: UpdateRegs
 109   LoadConstantToReg (0x01C00000,r0)      @ldr     r0, = 0x01C00000
 110   str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
 111
 112 #
 113 # Setup NOR3 (CS0-Interface1)
 114 #
 115   LoadConstantToReg (0x0002393A,r0)      @ldr     r0, = 0x0002393A
 116   str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
 117
 118   # 0x00000002 = MemoryWidth: 32bit
 119   # 0x00000028 = ReadMemoryBurstLength:continuous
 120   # 0x00000280 = WriteMemoryBurstLength:continuous
 121   # 0x00000800 = Set Address Valid
 122   LoadConstantToReg (0x00000AAA,r0)      @ldr     r0, = 0x00000AAA
 123   str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
 124
 125   # 0x02000000 = ChipSelect0-Interface 1
 126   # 0x00400000 = CmdTypes: UpdateRegs
 127   LoadConstantToReg (0x02400000,r0)      @ldr     r0, = 0x02400000
 128   str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
 129
 130 #
 131 # Setup Peripherals (CS3-Interface1)
 132 #
 133   LoadConstantToReg (0x00025156,r0)      @ldr     r0, = 0x00025156
 134   str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
 135
 136   # 0x00000002 = MemoryWidth: 32bit
 137   # 0x00000004 = Memory reads are synchronous
 138   # 0x00000040 = Memory writes are synchronous
 139   LoadConstantToReg (0x00000046,r0)      @ldr     r0, = 0x00000046
 140   str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
 141
 142   # 0x03800000 = ChipSelect3-Interface 1
 143   # 0x00400000 = CmdTypes: UpdateRegs
 144   LoadConstantToReg (0x03C00000,r0)      @ldr     r0, = 0x03C00000
 145   str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
 146   bx    lr
 147
 148 // IN r1 SmcBase
 149 // IN r2 VideoSRamBase
 150 // NOTE: This code is been called before any stack has been setup. It means some registers
 151 //       could be overwritten (case of 'r0')
 152 ASM_PFX(SMCInitializeVRAM):
 153 #
 154 # Setup VRAM (CS1-Interface0)
 155 #
 156   LoadConstantToReg (0x00049249,r0)      @ldr     r0, =  0x00049249
 157   str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
 158
 159   # 0x00000002 = MemoryWidth: 32bit
 160   # 0x00000004 = Memory reads are synchronous
 161   # 0x00000040 = Memory writes are synchronous
 162   LoadConstantToReg (0x00000046,r0)      @ldr     r0, = 0x00000046
 163   str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
 164
 165   # 0x00800000 = ChipSelect1-Interface 0
 166   # 0x00400000 = CmdTypes: UpdateRegs
 167   LoadConstantToReg (0x00C00000,r0)      @ldr     r0, = 0x00C00000
 168   str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
 169
 170 #
 171 # Page mode setup for VRAM
 172 #
 173   #read current state
 174   ldr     r0, [r2, #0]
 175   ldr     r0, [r2, #0]
 176   LoadConstantToReg (0x00000000,r0)      @ldr     r0, = 0x00000000
 177   str     r0, [r2, #0]
 178   ldr     r0, [r2, #0]
 179
 180   #enable page mode
 181   ldr     r0, [r2, #0]
 182   ldr     r0, [r2, #0]
 183   LoadConstantToReg (0x00000000,r0)      @ldr     r0, = 0x00000000
 184   str     r0, [r2, #0]
 185   LoadConstantToReg (0x00900090,r0)      @ldr     r0, = 0x00900090
 186   str     r0, [r2, #0]
 187
 188   #confirm page mode enabled
 189   ldr     r0, [r2, #0]
 190   ldr     r0, [r2, #0]
 191   LoadConstantToReg (0x00000000,r0)      @ldr     r0, = 0x00000000
 192   str     r0, [r2, #0]
 193   ldr     r0, [r2, #0]
 194
 195   bx    lr
 196
 197 ASM_FUNCTION_REMOVE_IF_UNREFERENCED