ArmPkg/Drivers/PL35xSmc/InitializeSMC.S

   1 #
   2 #  Copyright (c) 2011, ARM Limited. All rights reserved.
   3 #
   4 #  This program and the accompanying materials
   5 #  are licensed and made available under the terms and conditions of the BSD License
   6 #  which accompanies this distribution.  The full text of the license may be found at
   7 #  http:#opensource.org/licenses/bsd-license.php
   8 #
   9 #  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 #
  12 #
  13
  14 #include <AsmMacroIoLib.h>
  15 #include <Library/PcdLib.h>
  16 #include <AutoGen.h>
  17 #include <AsmMacroIoLib.h>
  18
  19 #Start of the code section
  20 .text
  21
  22 #Maintain 8 byte alignment
  23 .align 3
  24
  25 #Export Initialize SMC symbol
  26 GCC_ASM_EXPORT(InitializeSMC)
  27
  28 # Static memory configuation definitions for SMC
  29 .set        SmcDirectCmd,              0x10
  30 .set        SmcSetCycles,              0x14
  31 .set        SmcSetOpMode,              0x18
  32
  33 # CS0  CS0-Interf0     NOR1 flash on the motherboard
  34 # CS1  CS1-Interf0     Reserved for the motherboard
  35 # CS2  CS2-Interf0     SRAM on the motherboard
  36 # CS3  CS3-Interf0     memory-mapped Ethernet and USB controllers on the motherboard
  37 # CS4  CS0-Interf1     NOR2 flash on the motherboard
  38 # CS5  CS1-Interf1     memory-mapped peripherals
  39 # CS6  CS2-Interf1     memory-mapped peripherals
  40 # CS7  CS3-Interf1     system memory-mapped peripherals on the motherboard.
  41
  42 # IN r1 SmcBase
  43 # IN r2 VideoSRamBase
  44 # NOTE: This code is been called before any stack has been setup. It means some registers
  45 #       could be overwritten (case of 'r0')
  46
  47
  48 ASM_PFX(InitializeSMC):
  49 #
  50 # Setup NOR1 (CS0-Interface0)
  51 #
  52
  53   #Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)
  54      #Read cycle timeout = 0xA (0:3)
  55      #Write cycle timeout = 0x3(7:4)
  56      #OE Assertion Delay = 0x9(11:8)
  57      #WE Assertion delay = 0x3(15:12)
  58      #Page cycle timeout = 0x2(19:16)
  59   LoadConstantToReg (0x0002393A,r0)       @ldr     r0, = 0x0002393A
  60   str     r0, [r1, #SmcSetCycles]
  61
  62   #Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)
  63      # 0x00000002 = MemoryWidth: 32bit
  64      # 0x00000028 = ReadMemoryBurstLength:continuous
  65      # 0x00000280 = WriteMemoryBurstLength:continuous
  66      # 0x00000800 = Set Address Valid
  67   LoadConstantToReg (0x00000AAA,r0)       @ldr     r0, = 0x00000AAA
  68   str     r0, [r1, #SmcSetOpMode]
  69
  70  #Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers
  71      # 0x00000000 = ChipSelect0-Interface 0
  72      # 0x00400000 = CmdTypes: UpdateRegs
  73   LoadConstantToReg (0x00400000,r0)       @ldr     r0, = 0x00400000
  74   str     r0, [r1, #SmcDirectCmd]
  75
  76
  77 #
  78 # Setup SRAM (CS2-Interface0)
  79 #
  80   LoadConstantToReg (0x00027158,r0)       @ldr     r0, = 0x00027158
  81   str     r0, [r1, #SmcSetCycles]
  82
  83   # 0x00000002 = MemoryWidth: 32bit
  84   # 0x00000800 = Set Address Valid
  85   LoadConstantToReg (0x00000802,r0)       @ldr     r0, = 0x00000802
  86   str     r0, [r1, #SmcSetOpMode]
  87
  88   # 0x01000000 = ChipSelect2-Interface 0
  89   # 0x00400000 = CmdTypes: UpdateRegs
  90   LoadConstantToReg (0x01400000,r0)       @ldr     r0, = 0x01400000
  91   str     r0, [r1, #SmcDirectCmd]
  92
  93 #
  94 # USB/Eth/VRAM (CS3-Interface0)
  95 #
  96   LoadConstantToReg (0x000CD2AA,r0)      @ldr     r0, = 0x000CD2AA
  97   str     r0, [r1, #SmcSetCycles]
  98
  99   # 0x00000002 = MemoryWidth: 32bit
 100   # 0x00000004 = Memory reads are synchronous
 101   # 0x00000040 = Memory writes are synchronous
 102   LoadConstantToReg (0x00000046,r0)      @ldr     r0, = 0x00000046
 103   str     r0, [r1, #SmcSetOpMode]
 104
 105   # 0x01800000 = ChipSelect3-Interface 0
 106   # 0x00400000 = CmdTypes: UpdateRegs
 107   LoadConstantToReg (0x01C00000,r0)      @ldr     r0, = 0x01C00000
 108   str     r0, [r1, #SmcDirectCmd]
 109
 110 #
 111 # Setup NOR3 (CS0-Interface1)
 112 #
 113   LoadConstantToReg (0x0002393A,r0)      @ldr     r0, = 0x0002393A
 114   str     r0, [r1, #SmcSetCycles]
 115
 116   # 0x00000002 = MemoryWidth: 32bit
 117   # 0x00000028 = ReadMemoryBurstLength:continuous
 118   # 0x00000280 = WriteMemoryBurstLength:continuous
 119   # 0x00000800 = Set Address Valid
 120   LoadConstantToReg (0x00000AAA,r0)      @ldr     r0, = 0x00000AAA
 121   str     r0, [r1, #SmcSetOpMode]
 122
 123   # 0x02000000 = ChipSelect0-Interface 1
 124   # 0x00400000 = CmdTypes: UpdateRegs
 125   LoadConstantToReg (0x02400000,r0)      @ldr     r0, = 0x02400000
 126   str     r0, [r1, #SmcDirectCmd]
 127
 128 #
 129 # Setup Peripherals (CS3-Interface1)
 130 #
 131   LoadConstantToReg (0x00025156,r0)      @ldr     r0, = 0x00025156
 132   str     r0, [r1, #SmcSetCycles]
 133
 134   # 0x00000002 = MemoryWidth: 32bit
 135   # 0x00000004 = Memory reads are synchronous
 136   # 0x00000040 = Memory writes are synchronous
 137   LoadConstantToReg (0x00000046,r0)      @ldr     r0, = 0x00000046
 138   str     r0, [r1, #SmcSetOpMode]
 139
 140   # 0x03800000 = ChipSelect3-Interface 1
 141   # 0x00400000 = CmdTypes: UpdateRegs
 142   LoadConstantToReg (0x03C00000,r0)      @ldr     r0, = 0x03C00000
 143   str     r0, [r1, #SmcDirectCmd]
 144
 145 #
 146 # Setup VRAM (CS1-Interface0)
 147 #
 148   LoadConstantToReg (0x00049249,r0)      @ldr     r0, =  0x00049249
 149   str     r0, [r1, #SmcSetCycles]
 150
 151   # 0x00000002 = MemoryWidth: 32bit
 152   # 0x00000004 = Memory reads are synchronous
 153   # 0x00000040 = Memory writes are synchronous
 154   LoadConstantToReg (0x00000046,r0)      @ldr     r0, = 0x00000046
 155   str     r0, [r1, #SmcSetOpMode]
 156
 157   # 0x00800000 = ChipSelect1-Interface 0
 158   # 0x00400000 = CmdTypes: UpdateRegs
 159   LoadConstantToReg (0x00C00000,r0)      @ldr     r0, = 0x00C00000
 160   str     r0, [r1, #SmcDirectCmd]
 161
 162 #
 163 # Page mode setup for VRAM
 164 #
 165   #read current state
 166   ldr     r0, [r2, #0]
 167   ldr     r0, [r2, #0]
 168   LoadConstantToReg (0x00000000,r0)      @ldr     r0, = 0x00000000
 169   str     r0, [r2, #0]
 170   ldr     r0, [r2, #0]
 171
 172   #enable page mode
 173   ldr     r0, [r2, #0]
 174   ldr     r0, [r2, #0]
 175   LoadConstantToReg (0x00000000,r0)      @ldr     r0, = 0x00000000
 176   str     r0, [r2, #0]
 177   LoadConstantToReg (0x00900090,r0)      @ldr     r0, = 0x00900090
 178   str     r0, [r2, #0]
 179
 180   #confirm page mode enabled
 181   ldr     r0, [r2, #0]
 182   ldr     r0, [r2, #0]
 183   LoadConstantToReg (0x00000000,r0)      @ldr     r0, = 0x00000000
 184   str     r0, [r2, #0]
 185   ldr     r0, [r2, #0]
 186
 187   bx    lr
 188
 189 ASM_FUNCTION_REMOVE_IF_UNREFERENCED