Sync up ArmPkg with patch from mailing list. Changed name of BdsLib.h to BdsUnixLib...
[mirror_edk2.git] / ArmPkg / Drivers / PL35xSmc / InitializeSMC.asm
1 //
2 // Copyright (c) 2011, ARM Limited. All rights reserved.
3 //
4 // This program and the accompanying materials
5 // are licensed and made available under the terms and conditions of the BSD License
6 // which accompanies this distribution. The full text of the license may be found at
7 // http://opensource.org/licenses/bsd-license.php
8 //
9 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
11 //
12 //
13
14 #include <AsmMacroIoLib.h>
15 #include <Library/PcdLib.h>
16 #include <AutoGen.h>
17
18 INCLUDE AsmMacroIoLib.inc
19
20 EXPORT InitializeSMC
21
22 PRESERVE8
23 AREA ModuleInitializeSMC, CODE, READONLY
24
25 // Static memory configuation definitions for SMC
26 SmcDirectCmd EQU 0x10
27 SmcSetCycles EQU 0x14
28 SmcSetOpMode EQU 0x18
29
30 // CS0 CS0-Interf0 NOR1 flash on the motherboard
31 // CS1 CS1-Interf0 Reserved for the motherboard
32 // CS2 CS2-Interf0 SRAM on the motherboard
33 // CS3 CS3-Interf0 memory-mapped Ethernet and USB controllers on the motherboard
34 // CS4 CS0-Interf1 NOR2 flash on the motherboard
35 // CS5 CS1-Interf1 memory-mapped peripherals
36 // CS6 CS2-Interf1 memory-mapped peripherals
37 // CS7 CS3-Interf1 system memory-mapped peripherals on the motherboard.
38
39 // IN r1 SmcBase
40 // IN r2 VideoSRamBase
41 // NOTE: This code is been called before any stack has been setup. It means some registers
42 // could be overwritten (case of 'r0')
43 InitializeSMC
44 //
45 // Setup NOR1 (CS0-Interface0)
46 //
47
48 //Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)
49 //Read cycle timeout = 0xA (0:3)
50 //Write cycle timeout = 0x3(7:4)
51 //OE Assertion Delay = 0x9(11:8)
52 //WE Assertion delay = 0x3(15:12)
53 //Page cycle timeout = 0x2(19:16)
54 ldr r0, = 0x0002393A
55 str r0, [r1, #SmcSetCycles]
56
57 //Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)
58 // 0x00000002 = MemoryWidth: 32bit
59 // 0x00000028 = ReadMemoryBurstLength:continuous
60 // 0x00000280 = WriteMemoryBurstLength:continuous
61 // 0x00000800 = Set Address Valid
62 ldr r0, = 0x00000AAA
63 str r0, [r1, #SmcSetOpMode]
64
65 //Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers
66 // 0x00000000 = ChipSelect0-Interface 0
67 // 0x00400000 = CmdTypes: UpdateRegs
68 ldr r0, = 0x00400000
69 str r0, [r1, #SmcDirectCmd]
70
71 //
72 // Setup SRAM (CS2-Interface0)
73 //
74 ldr r0, = 0x00027158
75 str r0, [r1, #SmcSetCycles]
76
77 // 0x00000002 = MemoryWidth: 32bit
78 // 0x00000800 = Set Address Valid
79 ldr r0, = 0x00000802
80 str r0, [r1, #SmcSetOpMode]
81
82 // 0x01000000 = ChipSelect2-Interface 0
83 // 0x00400000 = CmdTypes: UpdateRegs
84 ldr r0, = 0x01400000
85 str r0, [r1, #SmcDirectCmd]
86
87 //
88 // USB/Eth/VRAM (CS3-Interface0)
89 //
90 ldr r0, = 0x000CD2AA
91 str r0, [r1, #SmcSetCycles]
92
93 // 0x00000002 = MemoryWidth: 32bit
94 // 0x00000004 = Memory reads are synchronous
95 // 0x00000040 = Memory writes are synchronous
96 ldr r0, = 0x00000046
97 str r0, [r1, #SmcSetOpMode]
98
99 // 0x01800000 = ChipSelect3-Interface 0
100 // 0x00400000 = CmdTypes: UpdateRegs
101 ldr r0, = 0x01C00000
102 str r0, [r1, #SmcDirectCmd]
103
104 //
105 // Setup NOR3 (CS0-Interface1)
106 //
107 ldr r0, = 0x0002393A
108 str r0, [r1, #SmcSetCycles]
109
110 // 0x00000002 = MemoryWidth: 32bit
111 // 0x00000028 = ReadMemoryBurstLength:continuous
112 // 0x00000280 = WriteMemoryBurstLength:continuous
113 // 0x00000800 = Set Address Valid
114 ldr r0, = 0x00000AAA
115 str r0, [r1, #SmcSetOpMode]
116
117 // 0x02000000 = ChipSelect0-Interface 1
118 // 0x00400000 = CmdTypes: UpdateRegs
119 ldr r0, = 0x02400000
120 str r0, [r1, #SmcDirectCmd]
121
122 //
123 // Setup Peripherals (CS3-Interface1)
124 //
125 ldr r0, = 0x00025156
126 str r0, [r1, #SmcSetCycles]
127
128 // 0x00000002 = MemoryWidth: 32bit
129 // 0x00000004 = Memory reads are synchronous
130 // 0x00000040 = Memory writes are synchronous
131 ldr r0, = 0x00000046
132 str r0, [r1, #SmcSetOpMode]
133
134 // 0x03800000 = ChipSelect3-Interface 1
135 // 0x00400000 = CmdTypes: UpdateRegs
136 ldr r0, = 0x03C00000
137 str r0, [r1, #SmcDirectCmd]
138
139 //
140 // Setup VRAM (CS1-Interface0)
141 //
142 ldr r0, = 0x00049249
143 str r0, [r1, #SmcSetCycles]
144
145 // 0x00000002 = MemoryWidth: 32bit
146 // 0x00000004 = Memory reads are synchronous
147 // 0x00000040 = Memory writes are synchronous
148 ldr r0, = 0x00000046
149 str r0, [r1, #SmcSetOpMode]
150
151 // 0x00800000 = ChipSelect1-Interface 0
152 // 0x00400000 = CmdTypes: UpdateRegs
153 ldr r0, = 0x00C00000
154 str r0, [r1, #SmcDirectCmd]
155
156 //
157 // Page mode setup for VRAM
158 //
159 //read current state
160 ldr r0, [r2, #0]
161 ldr r0, [r2, #0]
162 ldr r0, = 0x00000000
163 str r0, [r2, #0]
164 ldr r0, [r2, #0]
165
166 //enable page mode
167 ldr r0, [r2, #0]
168 ldr r0, [r2, #0]
169 ldr r0, = 0x00000000
170 str r0, [r2, #0]
171 ldr r0, = 0x00900090
172 str r0, [r2, #0]
173
174 //confirm page mode enabled
175 ldr r0, [r2, #0]
176 ldr r0, [r2, #0]
177 ldr r0, = 0x00000000
178 str r0, [r2, #0]
179 ldr r0, [r2, #0]
180
181 bx lr
182
183 END