Fix issue with fixing tabs.
[mirror_edk2.git] / ArmPkg / Drivers / PL390Gic / PL390GicNonSec.c
1 /** @file
2 *
3 * Copyright (c) 2011, ARM Limited. All rights reserved.
4 *
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
9 *
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12 *
13 **/
14
15 #include <Library/IoLib.h>
16 #include <Drivers/PL390Gic.h>
17
18
19 VOID
20 EFIAPI
21 PL390GicEnableInterruptInterface (
22 IN INTN GicInterruptInterfaceBase
23 )
24 {
25 /*
26 * Enable the CPU interface in Non-Secure world
27 * Note: The ICCICR register is banked when Security extensions are implemented
28 */
29 MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,0x00000001);
30 }
31
32 VOID
33 EFIAPI
34 PL390GicEnableDistributor (
35 IN INTN GicDistributorBase
36 )
37 {
38 /*
39 * Enable GIC distributor in Non-Secure world.
40 * Note: The ICDDCR register is banked when Security extensions are implemented
41 */
42 MmioWrite32(GicDistributorBase + GIC_ICDDCR, 0x00000001);
43 }
44
45 VOID
46 EFIAPI
47 PL390GicSendSgiTo (
48 IN INTN GicDistributorBase,
49 IN INTN TargetListFilter,
50 IN INTN CPUTargetList
51 )
52 {
53 MmioWrite32(GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));
54 }
55
56 UINT32
57 EFIAPI
58 PL390GicAcknowledgeSgiFrom (
59 IN INTN GicInterruptInterfaceBase,
60 IN INTN CoreId
61 )
62 {
63 INTN InterruptId;
64
65 InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
66
67 //Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
68 if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {
69 //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
70 MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
71 return 1;
72 } else {
73 return 0;
74 }
75 }
76
77 UINT32
78 EFIAPI
79 PL390GicAcknowledgeSgi2From (
80 IN INTN GicInterruptInterfaceBase,
81 IN INTN CoreId,
82 IN INTN SgiId
83 )
84 {
85 INTN InterruptId;
86
87 InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
88
89 //Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
90 if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {
91 //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
92 MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
93 return 1;
94 } else {
95 return 0;
96 }
97 }