ArmPkg/Drivers/PL390Gic/PL390GicSec.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #include <Base.h>
  16 #include <Library/ArmLib.h>
  17 #include <Library/DebugLib.h>
  18 #include <Library/IoLib.h>
  19 #include <Library/ArmGicLib.h>
  20
  21 /*
  22  * This function configures the all interrupts to be Non-secure.
  23  *
  24  */
  25 VOID
  26 EFIAPI
  27 ArmGicSetupNonSecure (
  28   IN  UINTN         MpId,
  29   IN  INTN          GicDistributorBase,
  30   IN  INTN          GicInterruptInterfaceBase
  31   )
  32 {
  33   UINTN InterruptId;
  34   UINTN CachedPriorityMask;
  35   UINTN Index;
  36
  37   CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR);
  38
  39   // Set priority Mask so that no interrupts get through to CPU
  40   MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);
  41
  42   // Check if there are any pending interrupts
  43   //TODO: could be extended to take Peripheral interrupts into consideration, but at the moment only SGI's are taken into consideration.
  44   while(0 != (MmioRead32 (GicDistributorBase + ARM_GIC_ICDICPR) & 0xF)) {
  45     // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
  46     InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
  47
  48     // Write to End of interrupt signal
  49     MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);
  50   }
  51
  52   // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).
  53   if (IS_PRIMARY_CORE(MpId)) {
  54     // Ensure all GIC interrupts are Non-Secure
  55     for (Index = 0; Index < (PcdGet32(PcdGicNumInterrupts) / 32); Index++) {
  56       MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);
  57     }
  58   } else {
  59     // The secondary cores only set the Non Secure bit to their banked PPIs
  60     MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);
  61   }
  62
  63   // Ensure all interrupts can get through the priority mask
  64   MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);
  65 }
  66
  67 /*
  68  * This function configures the interrupts set by the mask to be secure.
  69  *
  70  */
  71 VOID
  72 EFIAPI
  73 ArmGicSetSecureInterrupts (
  74   IN  UINTN         GicDistributorBase,
  75   IN  UINTN*        GicSecureInterruptMask,
  76   IN  UINTN         GicSecureInterruptMaskSize
  77   )
  78 {
  79   UINTN  Index;
  80   UINT32 InterruptStatus;
  81
  82   // We must not have more interrupts defined by the mask than the number of available interrupts
  83   ASSERT(GicSecureInterruptMaskSize <= (PcdGet32(PcdGicNumInterrupts) / 32));
  84
  85   // Set all the interrupts defined by the mask as Secure
  86   for (Index = 0; Index < GicSecureInterruptMaskSize; Index++) {
  87     InterruptStatus = MmioRead32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4));
  88     MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), InterruptStatus & (~GicSecureInterruptMask[Index]));
  89   }
  90 }
  91
  92 VOID
  93 EFIAPI
  94 ArmGicEnableInterruptInterface (
  95   IN  INTN          GicInterruptInterfaceBase
  96   )
  97 {
  98   // Set Priority Mask to allow interrupts
  99   MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);
 100
 101   // Enable CPU interface in Secure world
 102   // Enable CPU inteface in Non-secure World
 103   // Signal Secure Interrupts to CPU using FIQ line *
 104   MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,
 105       ARM_GIC_ICCICR_ENABLE_SECURE |
 106       ARM_GIC_ICCICR_ENABLE_NS |
 107       ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);
 108 }
 109
 110 VOID
 111 EFIAPI
 112 ArmGicEnableDistributor (
 113   IN  INTN          GicDistributorBase
 114   )
 115 {
 116   // Turn on the GIC distributor
 117   MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 1);
 118 }