ArmPkg/ArmGicLib: Added function ArmGicSetSecureInterrupts() to define the secure...
[mirror_edk2.git] / ArmPkg / Drivers / PL390Gic / PL390GicSec.c
1 /** @file
2 *
3 * Copyright (c) 2011, ARM Limited. All rights reserved.
4 *
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
9 *
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12 *
13 **/
14
15 #include <Base.h>
16 #include <Library/DebugLib.h>
17 #include <Library/IoLib.h>
18 #include <Library/ArmGicLib.h>
19
20 /*
21 * This function configures the all interrupts to be Non-secure.
22 *
23 */
24 VOID
25 EFIAPI
26 ArmGicSetupNonSecure (
27 IN INTN GicDistributorBase,
28 IN INTN GicInterruptInterfaceBase
29 )
30 {
31 UINTN InterruptId;
32 UINTN CachedPriorityMask;
33 UINTN Index;
34
35 CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR);
36
37 // Set priority Mask so that no interrupts get through to CPU
38 MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);
39
40 // Check if there are any pending interrupts
41 //TODO: could be extended to take Peripheral interrupts into consideration, but at the moment only SGI's are taken into consideration.
42 while(0 != (MmioRead32 (GicDistributorBase + ARM_GIC_ICDICPR) & 0xF)) {
43 // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
44 InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
45
46 // Write to End of interrupt signal
47 MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);
48 }
49
50 // Ensure all GIC interrupts are Non-Secure
51 for (Index = 0; Index < (PcdGet32(PcdGicNumInterrupts) / 32); Index++) {
52 MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);
53 }
54
55 // Ensure all interrupts can get through the priority mask
56 MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);
57 }
58
59 /*
60 * This function configures the interrupts set by the mask to be secure.
61 *
62 */
63 VOID
64 EFIAPI
65 ArmGicSetSecureInterrupts (
66 IN UINTN GicDistributorBase,
67 IN UINTN* GicSecureInterruptMask,
68 IN UINTN GicSecureInterruptMaskSize
69 )
70 {
71 UINTN Index;
72 UINT32 InterruptStatus;
73
74 // We must not have more interrupts defined by the mask than the number of available interrupts
75 ASSERT(GicSecureInterruptMaskSize <= (PcdGet32(PcdGicNumInterrupts) / 32));
76
77 // Set all the interrupts defined by the mask as Secure
78 for (Index = 0; Index < GicSecureInterruptMaskSize; Index++) {
79 InterruptStatus = MmioRead32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4));
80 MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), InterruptStatus & (~GicSecureInterruptMask[Index]));
81 }
82 }
83
84 VOID
85 EFIAPI
86 ArmGicEnableInterruptInterface (
87 IN INTN GicInterruptInterfaceBase
88 )
89 {
90 // Set Priority Mask to allow interrupts
91 MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);
92
93 // Enable CPU interface in Secure world
94 // Enable CPU inteface in Non-secure World
95 // Signal Secure Interrupts to CPU using FIQ line *
96 MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,
97 ARM_GIC_ICCICR_ENABLE_SECURE |
98 ARM_GIC_ICCICR_ENABLE_NS |
99 ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);
100 }
101
102 VOID
103 EFIAPI
104 ArmGicEnableDistributor (
105 IN INTN GicDistributorBase
106 )
107 {
108 // Turn on the GIC distributor
109 MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 1);
110 }