Sync up ArmPkg with patch from mailing list. Changed name of BdsLib.h to BdsUnixLib...
[mirror_edk2.git] / ArmPkg / Drivers / PL390Gic / PL390GicSec.c
1 /** @file
2 *
3 * Copyright (c) 2011, ARM Limited. All rights reserved.
4 *
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
9 *
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12 *
13 **/
14
15 #include <Library/IoLib.h>
16 #include <Drivers/PL390Gic.h>
17
18 /*
19 * This function configures the all interrupts to be Non-secure.
20 *
21 */
22 VOID
23 EFIAPI
24 PL390GicSetupNonSecure (
25 IN INTN GicDistributorBase,
26 IN INTN GicInterruptInterfaceBase
27 )
28 {
29 UINTN CachedPriorityMask = MmioRead32(GicInterruptInterfaceBase + GIC_ICCPMR);
30
31 //Set priority Mask so that no interrupts get through to CPU
32 MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0);
33
34 //Check if there are any pending interrupts
35 while(0 != (MmioRead32(GicDistributorBase + GIC_ICDICPR) & 0xF))
36 {
37 //Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
38 UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
39
40 //Write to End of interrupt signal
41 MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
42 }
43
44 // Ensure all GIC interrupts are Non-Secure
45 MmioWrite32(GicDistributorBase + GIC_ICDISR, 0xffffffff); // IRQs 0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]
46 MmioWrite32(GicDistributorBase + GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt
47 MmioWrite32(GicDistributorBase + GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)
48
49 // Ensure all interrupts can get through the priority mask
50 MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, CachedPriorityMask);
51 }
52
53 VOID
54 EFIAPI
55 PL390GicEnableInterruptInterface (
56 IN INTN GicInterruptInterfaceBase
57 )
58 {
59 MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0x000000FF); /* Set Priority Mask to allow interrupts */
60
61 /*
62 * Enable CPU interface in Secure world
63 * Enable CPU inteface in Non-secure World
64 * Signal Secure Interrupts to CPU using FIQ line *
65 */
66 MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,
67 GIC_ICCICR_ENABLE_SECURE(1) |
68 GIC_ICCICR_ENABLE_NS(1) |
69 GIC_ICCICR_ACK_CTL(0) |
70 GIC_ICCICR_SIGNAL_SECURE_TO_FIQ(1) |
71 GIC_ICCICR_USE_SBPR(0));
72 }
73
74 VOID
75 EFIAPI
76 PL390GicEnableDistributor (
77 IN INTN GicDistributorBase
78 )
79 {
80 MmioWrite32(GicDistributorBase + GIC_ICDDCR, 1); // turn on the GIC distributor
81 }
82
83 VOID
84 EFIAPI
85 PL390GicSendSgiTo (
86 IN INTN GicDistributorBase,
87 IN INTN TargetListFilter,
88 IN INTN CPUTargetList
89 )
90 {
91 MmioWrite32(GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));
92 }
93
94 UINT32
95 EFIAPI
96 PL390GicAcknowledgeSgiFrom (
97 IN INTN GicInterruptInterfaceBase,
98 IN INTN CoreId
99 )
100 {
101 INTN InterruptId;
102
103 InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
104
105 //Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
106 if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {
107 //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
108 MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
109 return 1;
110 } else {
111 return 0;
112 }
113 }
114
115 UINT32
116 EFIAPI
117 PL390GicAcknowledgeSgi2From (
118 IN INTN GicInterruptInterfaceBase,
119 IN INTN CoreId,
120 IN INTN SgiId
121 )
122 {
123 INTN InterruptId;
124
125 InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
126
127 //Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
128 if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {
129 //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
130 MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
131 return 1;
132 } else {
133 return 0;
134 }
135 }